SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 125545289 | 99560 | 0 | 0 |
late_debug_enable_rd_A | 125545289 | 15089 | 0 | 0 |
late_debug_enable_regwen_rd_A | 125545289 | 14012 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 125545289 | 99560 | 0 | 0 |
T56 | 54169 | 2 | 0 | 0 |
T57 | 56943 | 7 | 0 | 0 |
T58 | 330836 | 32469 | 0 | 0 |
T65 | 161111 | 1143 | 0 | 0 |
T72 | 6351 | 416 | 0 | 0 |
T73 | 16985 | 13 | 0 | 0 |
T74 | 309454 | 6 | 0 | 0 |
T75 | 14317 | 61 | 0 | 0 |
T77 | 11628 | 278 | 0 | 0 |
T78 | 20352 | 519 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 125545289 | 15089 | 0 | 0 |
T56 | 54169 | 52 | 0 | 0 |
T58 | 330836 | 5353 | 0 | 0 |
T65 | 161111 | 262 | 0 | 0 |
T75 | 14317 | 63 | 0 | 0 |
T76 | 242799 | 72 | 0 | 0 |
T89 | 6418 | 24 | 0 | 0 |
T90 | 9843 | 16 | 0 | 0 |
T97 | 15585 | 2 | 0 | 0 |
T121 | 15561 | 51 | 0 | 0 |
T122 | 449224 | 2430 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 125545289 | 14012 | 0 | 0 |
T56 | 54169 | 48 | 0 | 0 |
T58 | 330836 | 4714 | 0 | 0 |
T65 | 161111 | 221 | 0 | 0 |
T75 | 14317 | 34 | 0 | 0 |
T76 | 242799 | 85 | 0 | 0 |
T88 | 7147 | 7 | 0 | 0 |
T89 | 6418 | 30 | 0 | 0 |
T90 | 9843 | 7 | 0 | 0 |
T96 | 455803 | 958 | 0 | 0 |
T121 | 15561 | 64 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |