Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8419314 8418022 0 0
selKnown1 44506437 44505145 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8419314 8418022 0 0
T1 499 497 0 0
T2 15953 15950 0 0
T3 379 376 0 0
T4 2719 2715 0 0
T5 0 12 0 0
T6 0 6 0 0
T10 92487 92483 0 0
T11 20147 20143 0 0
T18 140893 140889 0 0
T26 9826 9822 0 0
T30 12 22 0 0
T35 947 943 0 0
T41 13294 13290 0 0
T42 2 0 0 0
T43 0 20 0 0
T44 0 20 0 0
T48 0 4 0 0
T49 0 20 0 0
T50 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 44506437 44505145 0 0
T1 2494 2492 0 0
T2 48232 48230 0 0
T3 7431 7429 0 0
T4 27443 27439 0 0
T5 0 10 0 0
T6 0 12 0 0
T10 636455 636451 0 0
T11 87164 87160 0 0
T18 210447 210443 0 0
T26 78553 78549 0 0
T30 24 22 0 0
T35 2964 2960 0 0
T41 139391 139387 0 0
T42 2 0 0 0
T43 0 20 0 0
T44 0 20 0 0
T48 0 4 0 0
T49 0 20 0 0
T50 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2139101 2138888 0 0
selKnown1 38226620 38226407 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2139101 2138888 0 0
T1 249 248 0 0
T2 7971 7970 0 0
T3 189 188 0 0
T4 1358 1357 0 0
T10 46236 46235 0 0
T11 10072 10071 0 0
T18 70438 70437 0 0
T26 4909 4908 0 0
T35 472 471 0 0
T41 6646 6645 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 38226620 38226407 0 0
T1 2245 2244 0 0
T2 40261 40260 0 0
T3 7242 7241 0 0
T4 26083 26082 0 0
T10 590205 590204 0 0
T11 77090 77089 0 0
T18 139993 139992 0 0
T26 73636 73635 0 0
T35 2490 2489 0 0
T41 132743 132742 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 540 327 0 0
selKnown1 525 312 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 540 327 0 0
T4 1 0 0 0
T5 0 6 0 0
T6 0 6 0 0
T10 7 6 0 0
T11 1 0 0 0
T18 8 7 0 0
T26 4 3 0 0
T30 12 11 0 0
T35 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T44 0 10 0 0
T48 0 2 0 0
T49 0 10 0 0
T50 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 525 312 0 0
T4 1 0 0 0
T5 0 5 0 0
T6 0 6 0 0
T10 7 6 0 0
T11 1 0 0 0
T18 8 7 0 0
T26 4 3 0 0
T30 12 11 0 0
T35 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T44 0 10 0 0
T48 0 2 0 0
T49 0 10 0 0
T50 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6277851 6277418 0 0
selKnown1 6277636 6277203 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6277851 6277418 0 0
T1 250 249 0 0
T2 7972 7971 0 0
T3 189 188 0 0
T4 1359 1358 0 0
T10 46237 46236 0 0
T11 10073 10072 0 0
T18 70439 70438 0 0
T26 4909 4908 0 0
T35 473 472 0 0
T41 6646 6645 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6277636 6277203 0 0
T1 249 248 0 0
T2 7971 7970 0 0
T3 189 188 0 0
T4 1358 1357 0 0
T10 46236 46235 0 0
T11 10072 10071 0 0
T18 70438 70437 0 0
T26 4909 4908 0 0
T35 472 471 0 0
T41 6646 6645 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1822 1389 0 0
selKnown1 1656 1223 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822 1389 0 0
T2 10 9 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 6 0 0
T10 7 6 0 0
T11 1 0 0 0
T18 8 7 0 0
T26 4 3 0 0
T30 0 11 0 0
T35 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T44 0 10 0 0
T48 0 2 0 0
T49 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1656 1223 0 0
T4 1 0 0 0
T5 0 5 0 0
T6 0 6 0 0
T10 7 6 0 0
T11 1 0 0 0
T18 8 7 0 0
T26 4 3 0 0
T30 12 11 0 0
T35 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T43 0 10 0 0
T44 0 10 0 0
T48 0 2 0 0
T49 0 10 0 0
T50 1 0 0 0

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