SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 213 | 213 | 0 | 0 |
OutputsKnown_A | 38226620 | 38191626 | 0 | 0 |
gen_no_flops.OutputDelay_A | 38226620 | 38191626 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 213 | 213 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T41 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38226620 | 38191626 | 0 | 0 |
T1 | 2245 | 2195 | 0 | 0 |
T2 | 40261 | 40205 | 0 | 0 |
T3 | 7242 | 7144 | 0 | 0 |
T4 | 26083 | 26013 | 0 | 0 |
T10 | 590205 | 589772 | 0 | 0 |
T11 | 77090 | 77036 | 0 | 0 |
T18 | 139993 | 139458 | 0 | 0 |
T26 | 73636 | 73367 | 0 | 0 |
T35 | 2490 | 2430 | 0 | 0 |
T41 | 132743 | 132672 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 38226620 | 38191626 | 0 | 0 |
T1 | 2245 | 2195 | 0 | 0 |
T2 | 40261 | 40205 | 0 | 0 |
T3 | 7242 | 7144 | 0 | 0 |
T4 | 26083 | 26013 | 0 | 0 |
T10 | 590205 | 589772 | 0 | 0 |
T11 | 77090 | 77036 | 0 | 0 |
T18 | 139993 | 139458 | 0 | 0 |
T26 | 73636 | 73367 | 0 | 0 |
T35 | 2490 | 2430 | 0 | 0 |
T41 | 132743 | 132672 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |