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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.18 95.77 81.52 89.91 75.00 86.50 98.42 55.12


Total test records in report: 444
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T81 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2108781291 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:22 PM PDT 24 567304099 ps
T89 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1786265152 Jul 23 06:10:30 PM PDT 24 Jul 23 06:10:47 PM PDT 24 2315626847 ps
T311 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2080774191 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:33 PM PDT 24 11890165300 ps
T312 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.374259915 Jul 23 06:09:48 PM PDT 24 Jul 23 06:09:50 PM PDT 24 175654348 ps
T90 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.405215025 Jul 23 06:10:16 PM PDT 24 Jul 23 06:10:26 PM PDT 24 617574737 ps
T91 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.861050773 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:31 PM PDT 24 125378504 ps
T82 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.899532480 Jul 23 06:10:15 PM PDT 24 Jul 23 06:10:19 PM PDT 24 366019401 ps
T313 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2869763412 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:26 PM PDT 24 1468542516 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1774679604 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:48 PM PDT 24 16164888458 ps
T92 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2212514256 Jul 23 06:10:10 PM PDT 24 Jul 23 06:10:14 PM PDT 24 184549666 ps
T96 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1951140520 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:40 PM PDT 24 3985060018 ps
T93 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.339311634 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:29 PM PDT 24 373624061 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1115307654 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:21 PM PDT 24 1265846703 ps
T315 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1982095485 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:27 PM PDT 24 10656541216 ps
T316 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.516382101 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:07 PM PDT 24 47621177 ps
T84 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.549955245 Jul 23 06:10:15 PM PDT 24 Jul 23 06:10:23 PM PDT 24 922061952 ps
T94 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1197112975 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:09 PM PDT 24 201221902 ps
T95 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3220735918 Jul 23 06:10:13 PM PDT 24 Jul 23 06:10:17 PM PDT 24 267732735 ps
T85 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2410674121 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:13 PM PDT 24 287865119 ps
T317 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.143618565 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:28 PM PDT 24 5995992284 ps
T318 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.656100034 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:17 PM PDT 24 192721053 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3323030716 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:57 PM PDT 24 375824735 ps
T129 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2274522121 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:42 PM PDT 24 1720485776 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.302804197 Jul 23 06:10:03 PM PDT 24 Jul 23 06:10:06 PM PDT 24 66128741 ps
T127 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.344571443 Jul 23 06:09:53 PM PDT 24 Jul 23 06:10:00 PM PDT 24 711820090 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2472350325 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:27 PM PDT 24 206041309 ps
T101 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.634737401 Jul 23 06:09:54 PM PDT 24 Jul 23 06:09:58 PM PDT 24 253359883 ps
T321 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1143554839 Jul 23 06:10:08 PM PDT 24 Jul 23 06:10:22 PM PDT 24 5774910564 ps
T322 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.41146299 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:54 PM PDT 24 34056341189 ps
T152 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1606270721 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:10 PM PDT 24 1030790213 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.841631266 Jul 23 06:09:54 PM PDT 24 Jul 23 06:11:08 PM PDT 24 19697056199 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2180229278 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:10 PM PDT 24 101675936 ps
T324 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.242251140 Jul 23 06:10:13 PM PDT 24 Jul 23 06:10:37 PM PDT 24 26058859047 ps
T325 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3862609517 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:06 PM PDT 24 1440253128 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.774017137 Jul 23 06:09:47 PM PDT 24 Jul 23 06:09:49 PM PDT 24 956178406 ps
T327 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1447137583 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:15 PM PDT 24 227026021 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.730866439 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:01 PM PDT 24 307522432 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2987055859 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:15 PM PDT 24 472724335 ps
T158 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1062065447 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:41 PM PDT 24 1010257115 ps
T103 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.330925391 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:25 PM PDT 24 163132822 ps
T330 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3143646807 Jul 23 06:09:54 PM PDT 24 Jul 23 06:10:22 PM PDT 24 8502213886 ps
T167 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1673702582 Jul 23 06:10:08 PM PDT 24 Jul 23 06:11:13 PM PDT 24 57293937967 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3775727589 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:37 PM PDT 24 7553078166 ps
T331 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2823617222 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:29 PM PDT 24 323790312 ps
T160 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3940241096 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:46 PM PDT 24 4490310100 ps
T155 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3096239483 Jul 23 06:10:15 PM PDT 24 Jul 23 06:10:32 PM PDT 24 1343478707 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560869559 Jul 23 06:10:00 PM PDT 24 Jul 23 06:10:03 PM PDT 24 170387150 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3272500145 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:02 PM PDT 24 545858401 ps
T334 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.389232803 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:32 PM PDT 24 731144865 ps
T335 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3644296698 Jul 23 06:10:20 PM PDT 24 Jul 23 06:10:31 PM PDT 24 543421197 ps
T110 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1547858128 Jul 23 06:10:02 PM PDT 24 Jul 23 06:10:07 PM PDT 24 749697740 ps
T156 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1659441270 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:20 PM PDT 24 2807075324 ps
T336 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2781525854 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:09 PM PDT 24 139678978 ps
T337 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4140274595 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:12 PM PDT 24 273156639 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2256548728 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:13 PM PDT 24 364517238 ps
T121 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.264517674 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:30 PM PDT 24 1324375865 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3162687987 Jul 23 06:09:55 PM PDT 24 Jul 23 06:10:04 PM PDT 24 1982557302 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3181347002 Jul 23 06:09:54 PM PDT 24 Jul 23 06:10:01 PM PDT 24 810971714 ps
T341 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.653809931 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:30 PM PDT 24 1108292435 ps
T165 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3621179518 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:21 PM PDT 24 2488409852 ps
T122 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.301941371 Jul 23 06:10:29 PM PDT 24 Jul 23 06:10:44 PM PDT 24 198138971 ps
T342 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1582463014 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:37 PM PDT 24 11837757212 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4190643480 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:30 PM PDT 24 557554881 ps
T344 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3248913098 Jul 23 06:10:16 PM PDT 24 Jul 23 06:10:20 PM PDT 24 348615133 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4119873222 Jul 23 06:10:10 PM PDT 24 Jul 23 06:10:15 PM PDT 24 131522094 ps
T157 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2408106008 Jul 23 06:10:24 PM PDT 24 Jul 23 06:10:53 PM PDT 24 1767880378 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2481628535 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:19 PM PDT 24 246332775 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1026653477 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:12 PM PDT 24 10361979865 ps
T347 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3268524423 Jul 23 06:10:21 PM PDT 24 Jul 23 06:10:29 PM PDT 24 258408145 ps
T99 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1998483465 Jul 23 06:10:00 PM PDT 24 Jul 23 06:10:06 PM PDT 24 3082921027 ps
T348 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.908011747 Jul 23 06:09:54 PM PDT 24 Jul 23 06:09:58 PM PDT 24 130728322 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1990596159 Jul 23 06:10:00 PM PDT 24 Jul 23 06:11:53 PM PDT 24 40171549551 ps
T111 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2732198318 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:17 PM PDT 24 209893442 ps
T112 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3557634675 Jul 23 06:10:21 PM PDT 24 Jul 23 06:10:28 PM PDT 24 623622245 ps
T105 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3712125329 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:10 PM PDT 24 46311233 ps
T350 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2829705305 Jul 23 06:09:59 PM PDT 24 Jul 23 06:10:02 PM PDT 24 310404546 ps
T351 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.421349708 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:06 PM PDT 24 180058083 ps
T352 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.601303632 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:24 PM PDT 24 5322933179 ps
T353 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2792335276 Jul 23 06:09:53 PM PDT 24 Jul 23 06:10:23 PM PDT 24 2975602438 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3492250116 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:53 PM PDT 24 1518677206 ps
T166 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.403058789 Jul 23 06:10:23 PM PDT 24 Jul 23 06:11:01 PM PDT 24 5014741623 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1140821878 Jul 23 06:10:03 PM PDT 24 Jul 23 06:10:06 PM PDT 24 68637257 ps
T356 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2663568903 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:05 PM PDT 24 290294476 ps
T113 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3485006470 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:26 PM PDT 24 92573645 ps
T357 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.380570004 Jul 23 06:10:20 PM PDT 24 Jul 23 06:10:27 PM PDT 24 489785436 ps
T358 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.261089064 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:36 PM PDT 24 13911890435 ps
T114 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4048332192 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:53 PM PDT 24 3850006709 ps
T168 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.782266263 Jul 23 06:10:15 PM PDT 24 Jul 23 06:11:02 PM PDT 24 12088396075 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2947041299 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:00 PM PDT 24 69869693 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3141024669 Jul 23 06:10:04 PM PDT 24 Jul 23 06:10:11 PM PDT 24 816349515 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4220499772 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:23 PM PDT 24 72352314 ps
T362 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2127114616 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:19 PM PDT 24 219110387 ps
T363 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2539744753 Jul 23 06:10:02 PM PDT 24 Jul 23 06:13:27 PM PDT 24 81524600577 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1118943629 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:10 PM PDT 24 37616885 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2002371185 Jul 23 06:10:12 PM PDT 24 Jul 23 06:13:07 PM PDT 24 60274575087 ps
T366 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.997434473 Jul 23 06:10:08 PM PDT 24 Jul 23 06:10:11 PM PDT 24 391858614 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3194379908 Jul 23 06:09:36 PM PDT 24 Jul 23 06:10:01 PM PDT 24 27819914809 ps
T123 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1199273735 Jul 23 06:10:10 PM PDT 24 Jul 23 06:10:20 PM PDT 24 1865583791 ps
T124 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.787759785 Jul 23 06:10:20 PM PDT 24 Jul 23 06:10:34 PM PDT 24 3663975854 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3608876452 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:04 PM PDT 24 178091682 ps
T115 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.530842445 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:50 PM PDT 24 97024009 ps
T369 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2399270354 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:07 PM PDT 24 111632247 ps
T370 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154484098 Jul 23 06:09:40 PM PDT 24 Jul 23 06:10:15 PM PDT 24 8279734187 ps
T371 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2044446826 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:34 PM PDT 24 4877177782 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.354614279 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:15 PM PDT 24 457089817 ps
T373 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4039052384 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:14 PM PDT 24 122778627 ps
T374 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1794428443 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:04 PM PDT 24 46340257 ps
T375 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.101441919 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:03 PM PDT 24 246674190 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1895188640 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:19 PM PDT 24 190416666 ps
T377 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2833845698 Jul 23 06:10:36 PM PDT 24 Jul 23 06:10:43 PM PDT 24 649480670 ps
T378 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2573154621 Jul 23 06:10:13 PM PDT 24 Jul 23 06:10:18 PM PDT 24 616924500 ps
T379 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.421209874 Jul 23 06:10:20 PM PDT 24 Jul 23 06:10:51 PM PDT 24 17217733128 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3655224628 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:09 PM PDT 24 302168238 ps
T381 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2850897607 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:16 PM PDT 24 187728773 ps
T159 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2715048387 Jul 23 06:09:50 PM PDT 24 Jul 23 06:10:15 PM PDT 24 5088545413 ps
T382 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.986087007 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:56 PM PDT 24 110964717 ps
T383 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.211891814 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:29 PM PDT 24 36240633593 ps
T384 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3231715410 Jul 23 06:10:20 PM PDT 24 Jul 23 06:10:28 PM PDT 24 191610240 ps
T385 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.201052213 Jul 23 06:10:22 PM PDT 24 Jul 23 06:11:52 PM PDT 24 34002171893 ps
T162 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4156442223 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:14 PM PDT 24 1619984465 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3912307943 Jul 23 06:09:55 PM PDT 24 Jul 23 06:10:00 PM PDT 24 166409631 ps
T386 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3947168310 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:12 PM PDT 24 360093627 ps
T387 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3609114085 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:25 PM PDT 24 389631034 ps
T388 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2767860931 Jul 23 06:10:14 PM PDT 24 Jul 23 06:10:20 PM PDT 24 669160740 ps
T117 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1459490776 Jul 23 06:10:26 PM PDT 24 Jul 23 06:10:38 PM PDT 24 422488466 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2603883736 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:03 PM PDT 24 647008854 ps
T125 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3100236788 Jul 23 06:10:04 PM PDT 24 Jul 23 06:10:10 PM PDT 24 634047484 ps
T390 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3361953928 Jul 23 06:10:13 PM PDT 24 Jul 23 06:10:20 PM PDT 24 389582897 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3667597785 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:56 PM PDT 24 24721624304 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.753842147 Jul 23 06:09:59 PM PDT 24 Jul 23 06:10:39 PM PDT 24 21192329779 ps
T392 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.827178453 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:13 PM PDT 24 501951356 ps
T393 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3076479795 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:15 PM PDT 24 1577706324 ps
T394 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3630876425 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:11 PM PDT 24 291261205 ps
T395 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.254449578 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:17 PM PDT 24 7284993792 ps
T396 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1972560774 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:21 PM PDT 24 339358726 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1206259403 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:57 PM PDT 24 6227903913 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3592361007 Jul 23 06:09:52 PM PDT 24 Jul 23 06:10:44 PM PDT 24 32288191639 ps
T399 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1641199843 Jul 23 06:09:49 PM PDT 24 Jul 23 06:10:03 PM PDT 24 6538715079 ps
T400 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.655497663 Jul 23 06:10:03 PM PDT 24 Jul 23 06:10:06 PM PDT 24 113042759 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4018296877 Jul 23 06:09:59 PM PDT 24 Jul 23 06:11:20 PM PDT 24 48982303751 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1020140284 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:56 PM PDT 24 286462838 ps
T403 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2663382505 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:48 PM PDT 24 8287078128 ps
T404 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3487462829 Jul 23 06:10:22 PM PDT 24 Jul 23 06:11:15 PM PDT 24 59009694278 ps
T405 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1897529744 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:51 PM PDT 24 2513844532 ps
T406 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3383899993 Jul 23 06:10:08 PM PDT 24 Jul 23 06:10:12 PM PDT 24 406846555 ps
T153 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3879504692 Jul 23 06:09:51 PM PDT 24 Jul 23 06:10:04 PM PDT 24 1936993493 ps
T407 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3170142236 Jul 23 06:10:29 PM PDT 24 Jul 23 06:10:39 PM PDT 24 394522223 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4210947042 Jul 23 06:09:45 PM PDT 24 Jul 23 06:09:47 PM PDT 24 450239345 ps
T409 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1448336413 Jul 23 06:10:15 PM PDT 24 Jul 23 06:10:29 PM PDT 24 4637577471 ps
T410 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1592310845 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:10 PM PDT 24 302730942 ps
T411 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3751375148 Jul 23 06:10:24 PM PDT 24 Jul 23 06:10:54 PM PDT 24 10842380167 ps
T106 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2835862316 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:32 PM PDT 24 857047718 ps
T412 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.122990769 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:25 PM PDT 24 5723724162 ps
T413 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3299561077 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:20 PM PDT 24 3231433447 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.362901243 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:05 PM PDT 24 4963570703 ps
T414 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1178032972 Jul 23 06:10:07 PM PDT 24 Jul 23 06:10:10 PM PDT 24 258513827 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3687766202 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:11 PM PDT 24 1125259648 ps
T415 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1917656766 Jul 23 06:09:40 PM PDT 24 Jul 23 06:10:09 PM PDT 24 602197919 ps
T416 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3298219360 Jul 23 06:10:00 PM PDT 24 Jul 23 06:10:04 PM PDT 24 475931902 ps
T417 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2571653002 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:23 PM PDT 24 185327980 ps
T418 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2819115205 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:58 PM PDT 24 77004973 ps
T419 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.607349148 Jul 23 06:10:31 PM PDT 24 Jul 23 06:10:42 PM PDT 24 124572094 ps
T420 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2523008833 Jul 23 06:09:55 PM PDT 24 Jul 23 06:10:45 PM PDT 24 35203706657 ps
T164 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3749887928 Jul 23 06:10:18 PM PDT 24 Jul 23 06:10:32 PM PDT 24 1545413193 ps
T421 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2667523203 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:36 PM PDT 24 29622957788 ps
T422 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4033389502 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:19 PM PDT 24 7994093642 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2831285587 Jul 23 06:10:02 PM PDT 24 Jul 23 06:10:21 PM PDT 24 29455424142 ps
T424 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2164171446 Jul 23 06:10:39 PM PDT 24 Jul 23 06:11:57 PM PDT 24 28360374668 ps
T425 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2779091259 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:23 PM PDT 24 679530417 ps
T119 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1859215115 Jul 23 06:10:01 PM PDT 24 Jul 23 06:11:18 PM PDT 24 7626553429 ps
T426 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.914503907 Jul 23 06:10:14 PM PDT 24 Jul 23 06:10:20 PM PDT 24 1013404107 ps
T427 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3256914906 Jul 23 06:09:52 PM PDT 24 Jul 23 06:09:55 PM PDT 24 212109293 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1294127653 Jul 23 06:10:06 PM PDT 24 Jul 23 06:11:28 PM PDT 24 7207130285 ps
T428 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3327465974 Jul 23 06:09:51 PM PDT 24 Jul 23 06:09:56 PM PDT 24 252798002 ps
T161 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4074646717 Jul 23 06:10:09 PM PDT 24 Jul 23 06:10:24 PM PDT 24 3363267205 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4196761262 Jul 23 06:09:52 PM PDT 24 Jul 23 06:11:55 PM PDT 24 90268467468 ps
T430 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1282075147 Jul 23 06:10:03 PM PDT 24 Jul 23 06:10:26 PM PDT 24 11224346668 ps
T431 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.990151980 Jul 23 06:10:00 PM PDT 24 Jul 23 06:10:04 PM PDT 24 362070348 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1538966507 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:51 PM PDT 24 98968765 ps
T433 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3849982596 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:09 PM PDT 24 3808348071 ps
T163 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1485492789 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:33 PM PDT 24 2714986414 ps
T434 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3164959156 Jul 23 06:10:42 PM PDT 24 Jul 23 06:10:53 PM PDT 24 383967872 ps
T435 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3270732511 Jul 23 06:10:03 PM PDT 24 Jul 23 06:10:14 PM PDT 24 2975143066 ps
T436 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1622350711 Jul 23 06:10:21 PM PDT 24 Jul 23 06:10:30 PM PDT 24 383537207 ps
T154 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1639692588 Jul 23 06:10:08 PM PDT 24 Jul 23 06:10:19 PM PDT 24 533919837 ps
T437 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1145459415 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:10 PM PDT 24 385482026 ps
T438 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2968001117 Jul 23 06:09:54 PM PDT 24 Jul 23 06:10:00 PM PDT 24 619061124 ps
T439 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1823345415 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:26 PM PDT 24 343558835 ps
T440 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2239589758 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:13 PM PDT 24 1341386627 ps
T441 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2035548064 Jul 23 06:10:12 PM PDT 24 Jul 23 06:10:16 PM PDT 24 113626314 ps
T442 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2111911045 Jul 23 06:09:50 PM PDT 24 Jul 23 06:09:54 PM PDT 24 144352198 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1791636561 Jul 23 06:09:51 PM PDT 24 Jul 23 06:09:55 PM PDT 24 57456522 ps
T443 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.459579756 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:32 PM PDT 24 4654357439 ps
T444 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1100752515 Jul 23 06:09:44 PM PDT 24 Jul 23 06:09:53 PM PDT 24 5772862551 ps

Test location /workspace/coverage/default/41.rv_dm_stress_all.238559152
Short name T4
Test name
Test status
Simulation time 3620387740 ps
CPU time 2.26 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 213284 kb
Host smart-f019897f-ac95-4f9a-906a-107b98e82af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238559152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.238559152
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2912944501
Short name T2
Test name
Test status
Simulation time 6656278245 ps
CPU time 5.64 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:21 PM PDT 24
Peak memory 205344 kb
Host smart-452b0cde-5a69-43c6-9792-582a45cbe540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912944501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2912944501
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4057905937
Short name T61
Test name
Test status
Simulation time 37945688732 ps
CPU time 58.29 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:55 PM PDT 24
Peak memory 221544 kb
Host smart-4f5de4b6-cab4-49f8-a9cb-9d97c1453827
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057905937 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.4057905937
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3366372720
Short name T30
Test name
Test status
Simulation time 424159344 ps
CPU time 0.98 seconds
Started Jul 23 06:14:21 PM PDT 24
Finished Jul 23 06:14:23 PM PDT 24
Peak memory 204964 kb
Host smart-abc52191-e2d2-415b-acb8-69a22808da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366372720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3366372720
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.896092407
Short name T33
Test name
Test status
Simulation time 13846847618 ps
CPU time 15.44 seconds
Started Jul 23 06:15:04 PM PDT 24
Finished Jul 23 06:15:20 PM PDT 24
Peak memory 213536 kb
Host smart-6a4eccdb-5229-4812-9d46-751fec758de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896092407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.896092407
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.748637159
Short name T78
Test name
Test status
Simulation time 418135096 ps
CPU time 5.3 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:16 PM PDT 24
Peak memory 213256 kb
Host smart-13af1ab4-6be9-45f3-9b11-1b56fabdee47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748637159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.748637159
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1951140520
Short name T96
Test name
Test status
Simulation time 3985060018 ps
CPU time 17.51 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:40 PM PDT 24
Peak memory 213332 kb
Host smart-29388324-1d9f-4dd2-b5a4-5a49702d345e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951140520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
951140520
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2659381702
Short name T1
Test name
Test status
Simulation time 67221238 ps
CPU time 0.8 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 205052 kb
Host smart-07c57979-6eea-4e96-90e3-8a3fe6f07a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659381702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2659381702
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4021203207
Short name T21
Test name
Test status
Simulation time 1132444168 ps
CPU time 3.97 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:25 PM PDT 24
Peak memory 205056 kb
Host smart-f04f3ab4-dee4-4db7-bbb0-79635307fdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021203207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4021203207
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1868457830
Short name T284
Test name
Test status
Simulation time 27625588703 ps
CPU time 82.92 seconds
Started Jul 23 06:14:41 PM PDT 24
Finished Jul 23 06:16:04 PM PDT 24
Peak memory 213592 kb
Host smart-38924eb7-98a6-4306-a4b0-7a0516935ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868457830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1868457830
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.209060261
Short name T15
Test name
Test status
Simulation time 3305398437 ps
CPU time 2.52 seconds
Started Jul 23 06:15:28 PM PDT 24
Finished Jul 23 06:15:32 PM PDT 24
Peak memory 205164 kb
Host smart-007e8b92-0313-45e8-8f4e-2e78f252e372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209060261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.209060261
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.920464666
Short name T52
Test name
Test status
Simulation time 395866272 ps
CPU time 1.46 seconds
Started Jul 23 06:14:38 PM PDT 24
Finished Jul 23 06:14:40 PM PDT 24
Peak memory 229624 kb
Host smart-d833021c-a522-4a58-b94e-1289e9fcab0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920464666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.920464666
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2108781291
Short name T81
Test name
Test status
Simulation time 567304099 ps
CPU time 6.43 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:22 PM PDT 24
Peak memory 213304 kb
Host smart-27d1b27e-79d8-4e33-8bf3-96398d5e58fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108781291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2108781291
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3036174875
Short name T59
Test name
Test status
Simulation time 103770466 ps
CPU time 0.88 seconds
Started Jul 23 06:14:16 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 215456 kb
Host smart-b9c1bebb-843e-4851-9a61-1af5a4b95d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036174875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3036174875
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2324942801
Short name T76
Test name
Test status
Simulation time 1910077896 ps
CPU time 3.62 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 205148 kb
Host smart-da112454-75b8-4993-ab0b-4a2d58e0a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324942801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2324942801
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3920664651
Short name T9
Test name
Test status
Simulation time 4501553768 ps
CPU time 13.39 seconds
Started Jul 23 06:15:22 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 213464 kb
Host smart-f3249de7-b51b-42eb-8367-7224c3399f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920664651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3920664651
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1914472913
Short name T44
Test name
Test status
Simulation time 2520492407 ps
CPU time 9.25 seconds
Started Jul 23 06:15:19 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 205180 kb
Host smart-645bc49f-034d-4d98-8f99-a22337160134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914472913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1914472913
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1022824876
Short name T62
Test name
Test status
Simulation time 3486163166 ps
CPU time 17.87 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:10:13 PM PDT 24
Peak memory 213288 kb
Host smart-4b1afd05-2c26-4127-ab9d-e0d0c383c23b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022824876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1022824876
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2212514256
Short name T92
Test name
Test status
Simulation time 184549666 ps
CPU time 2.1 seconds
Started Jul 23 06:10:10 PM PDT 24
Finished Jul 23 06:10:14 PM PDT 24
Peak memory 213220 kb
Host smart-f1e9ac2a-f5bc-4950-a859-e0fb652171ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212514256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2212514256
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2993495391
Short name T41
Test name
Test status
Simulation time 97070484 ps
CPU time 0.87 seconds
Started Jul 23 06:14:11 PM PDT 24
Finished Jul 23 06:14:14 PM PDT 24
Peak memory 213140 kb
Host smart-ee8d3bff-1585-452a-b4e6-95e13fbcc9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993495391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2993495391
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3814332912
Short name T24
Test name
Test status
Simulation time 4277865465 ps
CPU time 3.44 seconds
Started Jul 23 06:15:32 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 213364 kb
Host smart-0956ff55-c746-45a5-a98e-57c47ce7cd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814332912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3814332912
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1723766981
Short name T43
Test name
Test status
Simulation time 124424897 ps
CPU time 0.84 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:15 PM PDT 24
Peak memory 204988 kb
Host smart-8bdf9b3e-6c83-40a7-a130-672361323bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723766981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1723766981
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1294127653
Short name T109
Test name
Test status
Simulation time 7207130285 ps
CPU time 79.95 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:11:28 PM PDT 24
Peak memory 213336 kb
Host smart-6f928614-cf78-4193-86ed-e0694ff2cb96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294127653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1294127653
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.807581943
Short name T55
Test name
Test status
Simulation time 333966149 ps
CPU time 1.57 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204928 kb
Host smart-5691b094-f160-443c-b6e0-e597f271dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807581943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.807581943
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1953200218
Short name T131
Test name
Test status
Simulation time 4077505403 ps
CPU time 14.17 seconds
Started Jul 23 06:14:38 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 213552 kb
Host smart-ef6e114e-0b47-4a4e-805e-031bd8f833fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953200218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1953200218
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3158315157
Short name T173
Test name
Test status
Simulation time 985324331 ps
CPU time 3.28 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:02 PM PDT 24
Peak memory 213396 kb
Host smart-30f94327-4ade-4691-95e0-ce8b2ec4b1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158315157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3158315157
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1491090278
Short name T20
Test name
Test status
Simulation time 867944469 ps
CPU time 1.99 seconds
Started Jul 23 06:14:25 PM PDT 24
Finished Jul 23 06:14:28 PM PDT 24
Peak memory 204992 kb
Host smart-543bca7b-884d-45e3-8a2a-071d37aaf0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491090278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1491090278
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1947677623
Short name T45
Test name
Test status
Simulation time 433105533 ps
CPU time 1.32 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 204980 kb
Host smart-14f8a269-374f-4b7c-bb69-84b447416935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947677623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1947677623
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.923315410
Short name T32
Test name
Test status
Simulation time 318278934 ps
CPU time 0.8 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 204972 kb
Host smart-f59baf1d-6002-4046-8a1d-7dfb7b312280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923315410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.923315410
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2215230724
Short name T86
Test name
Test status
Simulation time 1075435628 ps
CPU time 4.3 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 205052 kb
Host smart-7700cb12-ad85-402c-8dcd-15cf7faccc79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215230724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2215230724
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.811661870
Short name T39
Test name
Test status
Simulation time 833043387 ps
CPU time 1.57 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:23 PM PDT 24
Peak memory 204984 kb
Host smart-48a3d675-82d5-4fbd-bb1b-3d213f4a6520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811661870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.811661870
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.508737586
Short name T14
Test name
Test status
Simulation time 7155906073 ps
CPU time 19.9 seconds
Started Jul 23 06:14:28 PM PDT 24
Finished Jul 23 06:14:49 PM PDT 24
Peak memory 205212 kb
Host smart-7a70ab32-0399-4506-9a15-746eabd7b3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508737586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.508737586
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3454335528
Short name T134
Test name
Test status
Simulation time 3539177650 ps
CPU time 7.31 seconds
Started Jul 23 06:14:55 PM PDT 24
Finished Jul 23 06:15:03 PM PDT 24
Peak memory 213440 kb
Host smart-fc1d4bf5-f407-4b38-a480-4771286eaecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454335528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3454335528
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.730866439
Short name T328
Test name
Test status
Simulation time 307522432 ps
CPU time 1.26 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:01 PM PDT 24
Peak memory 204808 kb
Host smart-bf9571c7-119e-4590-a857-eca1d6de80e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730866439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.730866439
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1026653477
Short name T98
Test name
Test status
Simulation time 10361979865 ps
CPU time 8.58 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:12 PM PDT 24
Peak memory 205036 kb
Host smart-458b8631-f1d2-479c-8cca-e54b78fa326d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026653477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1026653477
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2002371185
Short name T365
Test name
Test status
Simulation time 60274575087 ps
CPU time 171.73 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:13:07 PM PDT 24
Peak memory 221472 kb
Host smart-874a35c9-322f-41aa-95d0-1d431f7e3170
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002371185 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2002371185
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1485492789
Short name T163
Test name
Test status
Simulation time 2714986414 ps
CPU time 18.19 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:33 PM PDT 24
Peak memory 213296 kb
Host smart-a8177c7a-8796-43a4-b60a-3cff39fa5990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485492789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
485492789
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.1500152471
Short name T25
Test name
Test status
Simulation time 505805534 ps
CPU time 0.85 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204984 kb
Host smart-83d7305e-97c4-4559-98f4-0937baf8657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500152471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1500152471
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1848388102
Short name T151
Test name
Test status
Simulation time 6943737065 ps
CPU time 6.53 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 213428 kb
Host smart-e6cb1746-0bf1-427f-8df1-babb0ac6b395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848388102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1848388102
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2898827063
Short name T139
Test name
Test status
Simulation time 205872359 ps
CPU time 1.02 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 204920 kb
Host smart-e9d41afa-d90e-4565-bd75-6c61eedd5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898827063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2898827063
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4002176678
Short name T34
Test name
Test status
Simulation time 19070837546 ps
CPU time 13.11 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:11 PM PDT 24
Peak memory 213548 kb
Host smart-d42dc208-74af-4e60-ab8a-e852537eeca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002176678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4002176678
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3098528993
Short name T130
Test name
Test status
Simulation time 4259222667 ps
CPU time 3.94 seconds
Started Jul 23 06:14:58 PM PDT 24
Finished Jul 23 06:15:03 PM PDT 24
Peak memory 215228 kb
Host smart-4c42a59f-9a42-4c05-b85f-a7499ea02443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098528993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3098528993
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2988971271
Short name T147
Test name
Test status
Simulation time 9753749446 ps
CPU time 24.72 seconds
Started Jul 23 06:15:19 PM PDT 24
Finished Jul 23 06:15:45 PM PDT 24
Peak memory 213408 kb
Host smart-800fdde8-0373-4a4b-819d-e404dce37ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988971271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2988971271
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1917656766
Short name T415
Test name
Test status
Simulation time 602197919 ps
CPU time 26.94 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:10:09 PM PDT 24
Peak memory 213264 kb
Host smart-0d7e63d9-c264-4087-84b8-d8ceb2053f29
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917656766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1917656766
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.753842147
Short name T118
Test name
Test status
Simulation time 21192329779 ps
CPU time 37.56 seconds
Started Jul 23 06:09:59 PM PDT 24
Finished Jul 23 06:10:39 PM PDT 24
Peak memory 213180 kb
Host smart-a3734cbe-ea46-40aa-930d-2c200895b4ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753842147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.753842147
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1547858128
Short name T110
Test name
Test status
Simulation time 749697740 ps
CPU time 2.44 seconds
Started Jul 23 06:10:02 PM PDT 24
Finished Jul 23 06:10:07 PM PDT 24
Peak memory 213276 kb
Host smart-445d7cf8-5174-465b-802e-863d02796ec3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547858128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1547858128
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2603883736
Short name T389
Test name
Test status
Simulation time 647008854 ps
CPU time 2.16 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:03 PM PDT 24
Peak memory 215092 kb
Host smart-9719b8b9-c1d1-4365-bb8b-ae24a8841150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603883736 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2603883736
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3912307943
Short name T116
Test name
Test status
Simulation time 166409631 ps
CPU time 1.49 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 213276 kb
Host smart-d74c5f6b-a40e-4290-bf4a-897268bec4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912307943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3912307943
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3194379908
Short name T367
Test name
Test status
Simulation time 27819914809 ps
CPU time 22.84 seconds
Started Jul 23 06:09:36 PM PDT 24
Finished Jul 23 06:10:01 PM PDT 24
Peak memory 205060 kb
Host smart-bcd5a58f-81e0-46e1-bf10-cb32f7a6bd60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194379908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3194379908
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1538966507
Short name T432
Test name
Test status
Simulation time 98968765 ps
CPU time 0.9 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:51 PM PDT 24
Peak memory 204704 kb
Host smart-a6a621be-0065-4051-a58b-2aa8508763c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538966507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1538966507
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3162687987
Short name T339
Test name
Test status
Simulation time 1982557302 ps
CPU time 6.36 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 204936 kb
Host smart-fb1d80b8-a188-4419-9234-7f94e9f201f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162687987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3162687987
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1206259403
Short name T397
Test name
Test status
Simulation time 6227903913 ps
CPU time 9.23 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:57 PM PDT 24
Peak memory 204988 kb
Host smart-b2486537-196e-46b8-804f-e7dc0afa21b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206259403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
206259403
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1897529744
Short name T405
Test name
Test status
Simulation time 2513844532 ps
CPU time 2.81 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:51 PM PDT 24
Peak memory 204872 kb
Host smart-26efcf7b-2e7f-40ae-a2d8-1e240d71c1b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897529744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1897529744
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2523008833
Short name T420
Test name
Test status
Simulation time 35203706657 ps
CPU time 46.53 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:10:45 PM PDT 24
Peak memory 205020 kb
Host smart-3874f57d-aea7-4894-95a6-88b47ba70be2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523008833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2523008833
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4210947042
Short name T408
Test name
Test status
Simulation time 450239345 ps
CPU time 1.28 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:09:47 PM PDT 24
Peak memory 204780 kb
Host smart-625ab4ad-c27c-4741-a7ba-387b9b03c7a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210947042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.4210947042
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.986087007
Short name T382
Test name
Test status
Simulation time 110964717 ps
CPU time 0.77 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 204796 kb
Host smart-008d2916-af4b-4eb8-9281-189f83c4aa22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986087007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.986087007
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560869559
Short name T332
Test name
Test status
Simulation time 170387150 ps
CPU time 0.72 seconds
Started Jul 23 06:10:00 PM PDT 24
Finished Jul 23 06:10:03 PM PDT 24
Peak memory 204768 kb
Host smart-735308e1-963f-4874-b0c9-63eb9b24684e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560869559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.560869559
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2947041299
Short name T359
Test name
Test status
Simulation time 69869693 ps
CPU time 0.73 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 204800 kb
Host smart-ce8aa1d6-adb1-4d5f-9479-6f46a2e62449
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947041299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2947041299
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3687766202
Short name T108
Test name
Test status
Simulation time 1125259648 ps
CPU time 8.08 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:11 PM PDT 24
Peak memory 205096 kb
Host smart-d475ae90-b313-4303-aaaf-62ea9b0f5ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687766202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3687766202
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3298219360
Short name T416
Test name
Test status
Simulation time 475931902 ps
CPU time 2.51 seconds
Started Jul 23 06:10:00 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 213276 kb
Host smart-972733f4-625c-4fac-bc1a-2023aa3fdf36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298219360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3298219360
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2715048387
Short name T159
Test name
Test status
Simulation time 5088545413 ps
CPU time 23.53 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 213260 kb
Host smart-3f33e0d9-dbcd-438a-9c23-324d2d989284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715048387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2715048387
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.459579756
Short name T443
Test name
Test status
Simulation time 4654357439 ps
CPU time 32.78 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 205100 kb
Host smart-ead9e7f2-7131-446f-8af3-d8665ac5891e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459579756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.459579756
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3775727589
Short name T104
Test name
Test status
Simulation time 7553078166 ps
CPU time 38 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:37 PM PDT 24
Peak memory 213272 kb
Host smart-9556c50f-458b-44dd-bdec-ed9e774ef934
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775727589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3775727589
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2111911045
Short name T442
Test name
Test status
Simulation time 144352198 ps
CPU time 1.9 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:09:54 PM PDT 24
Peak memory 213276 kb
Host smart-f26603f2-9a22-4818-a8b5-3e360f4d5fb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111911045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2111911045
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3327465974
Short name T428
Test name
Test status
Simulation time 252798002 ps
CPU time 2.62 seconds
Started Jul 23 06:09:51 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 213284 kb
Host smart-064f94de-f3a6-4a3b-bd21-deb74c2d7d75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327465974 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3327465974
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3272500145
Short name T333
Test name
Test status
Simulation time 545858401 ps
CPU time 1.55 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:02 PM PDT 24
Peak memory 213320 kb
Host smart-5919b819-57fb-4aa8-ba77-cb9cde57c5ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272500145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3272500145
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3592361007
Short name T398
Test name
Test status
Simulation time 32288191639 ps
CPU time 50.07 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:10:44 PM PDT 24
Peak memory 204924 kb
Host smart-cf31fc30-d09c-4ab4-a1a8-0ee3350c27a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592361007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3592361007
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1990596159
Short name T349
Test name
Test status
Simulation time 40171549551 ps
CPU time 110.7 seconds
Started Jul 23 06:10:00 PM PDT 24
Finished Jul 23 06:11:53 PM PDT 24
Peak memory 205036 kb
Host smart-05047ea1-6599-4442-ab7a-8b0760355c05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990596159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1990596159
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2026022453
Short name T298
Test name
Test status
Simulation time 1895138067 ps
CPU time 2.42 seconds
Started Jul 23 06:10:04 PM PDT 24
Finished Jul 23 06:10:08 PM PDT 24
Peak memory 204952 kb
Host smart-b47596b8-214b-440c-a188-f9107a57abd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026022453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
026022453
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1100752515
Short name T444
Test name
Test status
Simulation time 5772862551 ps
CPU time 8.68 seconds
Started Jul 23 06:09:44 PM PDT 24
Finished Jul 23 06:09:53 PM PDT 24
Peak memory 205052 kb
Host smart-b44901cc-cf26-47c4-a12d-876eeb11fbc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100752515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1100752515
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2327039513
Short name T73
Test name
Test status
Simulation time 1035547989 ps
CPU time 3.23 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:10:01 PM PDT 24
Peak memory 204796 kb
Host smart-7baacf8c-a38d-4329-8cb6-17d3d4e631be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327039513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2327039513
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3256914906
Short name T427
Test name
Test status
Simulation time 212109293 ps
CPU time 0.87 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 204804 kb
Host smart-6f0ae498-6ab4-4eb0-b4b5-5fd75c126e15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256914906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
256914906
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1794428443
Short name T374
Test name
Test status
Simulation time 46340257 ps
CPU time 0.79 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 204768 kb
Host smart-db538812-bcb3-4a8d-b837-535fbc0f270d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794428443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1794428443
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.655497663
Short name T400
Test name
Test status
Simulation time 113042759 ps
CPU time 0.95 seconds
Started Jul 23 06:10:03 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 204816 kb
Host smart-5ea23acd-1a0d-44e2-b47f-b14f525a5ad2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655497663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.655497663
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.362901243
Short name T107
Test name
Test status
Simulation time 4963570703 ps
CPU time 5.89 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:05 PM PDT 24
Peak memory 205076 kb
Host smart-ec6e42e7-6a9f-4a5c-9f92-ce33b8b501d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362901243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.362901243
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2831285587
Short name T423
Test name
Test status
Simulation time 29455424142 ps
CPU time 16.59 seconds
Started Jul 23 06:10:02 PM PDT 24
Finished Jul 23 06:10:21 PM PDT 24
Peak memory 221388 kb
Host smart-ce8c6f55-ec2c-4f03-8418-f81613e28b1d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831285587 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2831285587
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1115307654
Short name T83
Test name
Test status
Simulation time 1265846703 ps
CPU time 7.75 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:21 PM PDT 24
Peak memory 213320 kb
Host smart-dcc1c0f9-fa5c-4e5e-a8d7-78dcb395c244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115307654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1115307654
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1641199843
Short name T399
Test name
Test status
Simulation time 6538715079 ps
CPU time 12.41 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:10:03 PM PDT 24
Peak memory 213328 kb
Host smart-58ebfb74-83ef-4969-88ce-2a692e5bdbaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641199843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1641199843
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3361953928
Short name T390
Test name
Test status
Simulation time 389582897 ps
CPU time 3.96 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 219776 kb
Host smart-2b98e50b-7239-4fee-b531-d4d21a3eb7aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361953928 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3361953928
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3485006470
Short name T113
Test name
Test status
Simulation time 92573645 ps
CPU time 2.07 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:26 PM PDT 24
Peak memory 213272 kb
Host smart-adc800cc-89a9-4525-9d2d-ebf05cc889e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485006470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3485006470
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3751375148
Short name T411
Test name
Test status
Simulation time 10842380167 ps
CPU time 21.43 seconds
Started Jul 23 06:10:24 PM PDT 24
Finished Jul 23 06:10:54 PM PDT 24
Peak memory 205012 kb
Host smart-b7b3b873-d945-4ddb-b70f-6a24c9f479d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751375148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3751375148
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.254449578
Short name T395
Test name
Test status
Simulation time 7284993792 ps
CPU time 3.55 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:17 PM PDT 24
Peak memory 205020 kb
Host smart-58276b9c-75c4-475c-9e20-5b277b28ec13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254449578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.254449578
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3609114085
Short name T387
Test name
Test status
Simulation time 389631034 ps
CPU time 0.95 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:25 PM PDT 24
Peak memory 204832 kb
Host smart-5cbab245-8d13-4423-9941-df333d8e0355
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609114085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3609114085
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.899532480
Short name T82
Test name
Test status
Simulation time 366019401 ps
CPU time 2.39 seconds
Started Jul 23 06:10:15 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 213208 kb
Host smart-b0de5e6a-d737-4010-bab0-88c2360eff94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899532480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.899532480
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4156442223
Short name T162
Test name
Test status
Simulation time 1619984465 ps
CPU time 9.88 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:14 PM PDT 24
Peak memory 213260 kb
Host smart-37c5b508-f48b-4a87-b01f-95e5a54f69e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156442223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4
156442223
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4039052384
Short name T373
Test name
Test status
Simulation time 122778627 ps
CPU time 3.01 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:14 PM PDT 24
Peak memory 219196 kb
Host smart-96b4e1f8-304a-4810-b42c-98fe283e8bcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039052384 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4039052384
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.636044782
Short name T88
Test name
Test status
Simulation time 188589783 ps
CPU time 2.36 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:27 PM PDT 24
Peak memory 213244 kb
Host smart-d8f1eb9a-1efe-4097-bd3e-81829c13b8ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636044782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.636044782
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2667523203
Short name T421
Test name
Test status
Simulation time 29622957788 ps
CPU time 28.25 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:36 PM PDT 24
Peak memory 205056 kb
Host smart-75bc4e2b-36a5-44ad-95fe-8b108486e331
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667523203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2667523203
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3299561077
Short name T413
Test name
Test status
Simulation time 3231433447 ps
CPU time 5.4 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 204976 kb
Host smart-a207151f-fe69-4637-b594-2756d3e5b734
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299561077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3299561077
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1178032972
Short name T414
Test name
Test status
Simulation time 258513827 ps
CPU time 1.41 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 204828 kb
Host smart-fe08f716-6fac-4bea-a5be-226dfa0871af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178032972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1178032972
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.827178453
Short name T392
Test name
Test status
Simulation time 501951356 ps
CPU time 4.38 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:13 PM PDT 24
Peak memory 205020 kb
Host smart-44f2f1cc-9187-42ac-938f-7ca9286ab2f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827178453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.827178453
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2481628535
Short name T346
Test name
Test status
Simulation time 246332775 ps
CPU time 4.12 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 219492 kb
Host smart-8be93443-c0ea-44bf-bca2-75d4880fe573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481628535 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2481628535
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.339311634
Short name T93
Test name
Test status
Simulation time 373624061 ps
CPU time 1.56 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:29 PM PDT 24
Peak memory 213232 kb
Host smart-47915324-c4a5-4ce8-a481-40db32b168cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339311634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.339311634
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.143618565
Short name T317
Test name
Test status
Simulation time 5995992284 ps
CPU time 14.79 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 205012 kb
Host smart-7cf9016f-b385-4725-9b6d-d8abba09ceba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143618565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.143618565
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1573272961
Short name T305
Test name
Test status
Simulation time 2093304863 ps
CPU time 2.47 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:30 PM PDT 24
Peak memory 205048 kb
Host smart-61add18e-074b-4bb1-bdc7-3b4c39d37a73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573272961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1573272961
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2712783063
Short name T309
Test name
Test status
Simulation time 608263071 ps
CPU time 1.43 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 204736 kb
Host smart-a2506219-b37c-4dcd-a13c-f4f90e1f83d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712783063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2712783063
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3100236788
Short name T125
Test name
Test status
Simulation time 634047484 ps
CPU time 4.31 seconds
Started Jul 23 06:10:04 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 204972 kb
Host smart-bde117d1-d74a-436e-9a65-024388a39464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100236788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3100236788
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1823345415
Short name T439
Test name
Test status
Simulation time 343558835 ps
CPU time 6.29 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:26 PM PDT 24
Peak memory 213332 kb
Host smart-233199ce-167e-43fd-9664-508db6150e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823345415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1823345415
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1062065447
Short name T158
Test name
Test status
Simulation time 1010257115 ps
CPU time 10.85 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:41 PM PDT 24
Peak memory 213300 kb
Host smart-2e845137-6168-452e-86c9-47ddeee26238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062065447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
062065447
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4119873222
Short name T345
Test name
Test status
Simulation time 131522094 ps
CPU time 4.11 seconds
Started Jul 23 06:10:10 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 219460 kb
Host smart-df923d2d-07f0-43da-b4a0-8c13727d17cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119873222 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4119873222
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4220499772
Short name T361
Test name
Test status
Simulation time 72352314 ps
CPU time 1.47 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 213224 kb
Host smart-da1cb077-c234-45fe-9dd5-bc9a009a7ab5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220499772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4220499772
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3398680615
Short name T301
Test name
Test status
Simulation time 15375348790 ps
CPU time 39.66 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:37 PM PDT 24
Peak memory 205044 kb
Host smart-b227fe41-584a-4864-8114-217d59375d31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398680615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3398680615
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1448336413
Short name T409
Test name
Test status
Simulation time 4637577471 ps
CPU time 12.61 seconds
Started Jul 23 06:10:15 PM PDT 24
Finished Jul 23 06:10:29 PM PDT 24
Peak memory 205036 kb
Host smart-407509b8-5e2f-433c-b065-f0eb27147835
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448336413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1448336413
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2781525854
Short name T336
Test name
Test status
Simulation time 139678978 ps
CPU time 1.03 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:09 PM PDT 24
Peak memory 204812 kb
Host smart-6dd4e76b-f8b0-4d0c-b3c3-3d301c0765a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781525854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2781525854
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1622350711
Short name T436
Test name
Test status
Simulation time 383537207 ps
CPU time 3.62 seconds
Started Jul 23 06:10:21 PM PDT 24
Finished Jul 23 06:10:30 PM PDT 24
Peak memory 205052 kb
Host smart-4272bdf8-50ba-4d34-8970-1f0f8a1c05c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622350711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1622350711
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1895188640
Short name T376
Test name
Test status
Simulation time 190416666 ps
CPU time 4.75 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 213480 kb
Host smart-e4391d85-169b-4658-8233-73b9e24af108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895188640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1895188640
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.421349708
Short name T351
Test name
Test status
Simulation time 180058083 ps
CPU time 2.59 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 218668 kb
Host smart-5f9bebf4-1c1c-442a-b69c-036d917add2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421349708 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.421349708
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2164171446
Short name T424
Test name
Test status
Simulation time 28360374668 ps
CPU time 73.14 seconds
Started Jul 23 06:10:39 PM PDT 24
Finished Jul 23 06:11:57 PM PDT 24
Peak memory 205048 kb
Host smart-d4d319bf-c49b-48a0-9f53-f664f5a8da0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164171446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2164171446
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1282075147
Short name T430
Test name
Test status
Simulation time 11224346668 ps
CPU time 21.17 seconds
Started Jul 23 06:10:03 PM PDT 24
Finished Jul 23 06:10:26 PM PDT 24
Peak memory 204804 kb
Host smart-4b9cff8f-f32a-4615-af02-8d1a10333a4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282075147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1282075147
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2579458107
Short name T74
Test name
Test status
Simulation time 273857530 ps
CPU time 0.72 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:16 PM PDT 24
Peak memory 204836 kb
Host smart-095d54f3-2848-4ed1-a85f-19e20893d3ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579458107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2579458107
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1145459415
Short name T437
Test name
Test status
Simulation time 385482026 ps
CPU time 3.74 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 205060 kb
Host smart-a2cf997d-8ba9-4191-a863-25c3a4368ff6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145459415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1145459415
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2410674121
Short name T85
Test name
Test status
Simulation time 287865119 ps
CPU time 6.14 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:13 PM PDT 24
Peak memory 213296 kb
Host smart-e3c07818-eeac-4ad2-8cb9-b5e49a18cb3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410674121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2410674121
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2274522121
Short name T129
Test name
Test status
Simulation time 1720485776 ps
CPU time 17.53 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:42 PM PDT 24
Peak memory 213140 kb
Host smart-49b8e49f-e63e-4362-8cb0-fb01a3c8f687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274522121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
274522121
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3231715410
Short name T384
Test name
Test status
Simulation time 191610240 ps
CPU time 3.88 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 221404 kb
Host smart-a6a4bc22-5366-413c-b610-3fd6c3480ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231715410 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3231715410
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1972560774
Short name T396
Test name
Test status
Simulation time 339358726 ps
CPU time 1.61 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:21 PM PDT 24
Peak memory 213144 kb
Host smart-a4b17d50-dd47-4bfe-adff-7df10766db94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972560774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1972560774
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.242251140
Short name T324
Test name
Test status
Simulation time 26058859047 ps
CPU time 20.79 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:37 PM PDT 24
Peak memory 204988 kb
Host smart-ac1b6948-eab9-496e-9d68-d96a444abe51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242251140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.242251140
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2044446826
Short name T371
Test name
Test status
Simulation time 4877177782 ps
CPU time 14.53 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:34 PM PDT 24
Peak memory 205040 kb
Host smart-e7983bdd-a348-4bbe-af50-9b8fd63e9c00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044446826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2044446826
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.380570004
Short name T357
Test name
Test status
Simulation time 489785436 ps
CPU time 1.4 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:27 PM PDT 24
Peak memory 204752 kb
Host smart-2f8e21b5-4a13-49fa-8392-9f1f478530ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380570004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.380570004
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.861050773
Short name T91
Test name
Test status
Simulation time 125378504 ps
CPU time 3.65 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:31 PM PDT 24
Peak memory 205036 kb
Host smart-a556b6f5-74df-4a7f-a01c-285f043ab23f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861050773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.861050773
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3248913098
Short name T344
Test name
Test status
Simulation time 348615133 ps
CPU time 2.39 seconds
Started Jul 23 06:10:16 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 213292 kb
Host smart-b57aee15-6b34-4e8e-87e9-afc912e252d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248913098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3248913098
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1639692588
Short name T154
Test name
Test status
Simulation time 533919837 ps
CPU time 8.87 seconds
Started Jul 23 06:10:08 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 213216 kb
Host smart-3f362ff9-a69f-4a17-8e42-8d7ed6c765b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639692588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
639692588
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.607349148
Short name T419
Test name
Test status
Simulation time 124572094 ps
CPU time 2.43 seconds
Started Jul 23 06:10:31 PM PDT 24
Finished Jul 23 06:10:42 PM PDT 24
Peak memory 218188 kb
Host smart-53c8827d-5994-4af4-988e-48a2e49fb161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607349148 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.607349148
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2035548064
Short name T441
Test name
Test status
Simulation time 113626314 ps
CPU time 2.5 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:16 PM PDT 24
Peak memory 213232 kb
Host smart-247f26fc-0d3b-4537-89dc-40c326381f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035548064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2035548064
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1982095485
Short name T315
Test name
Test status
Simulation time 10656541216 ps
CPU time 19.49 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:27 PM PDT 24
Peak memory 205028 kb
Host smart-8cbe8303-65eb-4477-9ba3-b0c62bd08b2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982095485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1982095485
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2080774191
Short name T311
Test name
Test status
Simulation time 11890165300 ps
CPU time 12.98 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:33 PM PDT 24
Peak memory 205020 kb
Host smart-4d1e2a32-cd99-41c7-9819-77097a7d69c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080774191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2080774191
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2823617222
Short name T331
Test name
Test status
Simulation time 323790312 ps
CPU time 0.82 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:29 PM PDT 24
Peak memory 204836 kb
Host smart-3328515c-f6d9-4afb-a9af-c96ee8c8d01c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823617222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2823617222
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3164959156
Short name T434
Test name
Test status
Simulation time 383967872 ps
CPU time 6.35 seconds
Started Jul 23 06:10:42 PM PDT 24
Finished Jul 23 06:10:53 PM PDT 24
Peak memory 205108 kb
Host smart-0de082a7-a228-44d1-9460-fb8d0a8e7446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164959156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3164959156
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3644296698
Short name T335
Test name
Test status
Simulation time 543421197 ps
CPU time 5.92 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:31 PM PDT 24
Peak memory 213276 kb
Host smart-d4154d3d-dc2a-4553-be98-d65522064cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644296698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3644296698
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2408106008
Short name T157
Test name
Test status
Simulation time 1767880378 ps
CPU time 21.09 seconds
Started Jul 23 06:10:24 PM PDT 24
Finished Jul 23 06:10:53 PM PDT 24
Peak memory 213128 kb
Host smart-80d6026a-bd6e-4bd9-a3c8-f8df50adf56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408106008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
408106008
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2767860931
Short name T388
Test name
Test status
Simulation time 669160740 ps
CPU time 3.74 seconds
Started Jul 23 06:10:14 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 218504 kb
Host smart-0953cd09-ba70-4075-a443-5595f3505600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767860931 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2767860931
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2290994508
Short name T87
Test name
Test status
Simulation time 227133859 ps
CPU time 2.39 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 213192 kb
Host smart-f31b3d4e-3616-4125-aa78-9d4db8016840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290994508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2290994508
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.713057392
Short name T300
Test name
Test status
Simulation time 27423801667 ps
CPU time 80.6 seconds
Started Jul 23 06:10:29 PM PDT 24
Finished Jul 23 06:11:58 PM PDT 24
Peak memory 205012 kb
Host smart-bb5d0c59-9071-4d29-9167-bbefb0032afb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713057392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.713057392
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.601303632
Short name T352
Test name
Test status
Simulation time 5322933179 ps
CPU time 8.7 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:24 PM PDT 24
Peak memory 205288 kb
Host smart-a0a4b0de-c397-47c5-94d1-03215bbe887a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601303632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.601303632
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2829705305
Short name T350
Test name
Test status
Simulation time 310404546 ps
CPU time 0.84 seconds
Started Jul 23 06:09:59 PM PDT 24
Finished Jul 23 06:10:02 PM PDT 24
Peak memory 204792 kb
Host smart-0ffc6c1c-f00d-4c8f-bc99-32f9a23e6ed4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829705305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2829705305
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2835862316
Short name T106
Test name
Test status
Simulation time 857047718 ps
CPU time 7.33 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 205092 kb
Host smart-ce8a9661-61c3-4d52-85c2-59f616eef118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835862316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2835862316
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2573154621
Short name T378
Test name
Test status
Simulation time 616924500 ps
CPU time 3.2 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:18 PM PDT 24
Peak memory 213264 kb
Host smart-6481b9bc-b12b-4548-8914-7362e501eb13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573154621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2573154621
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.403058789
Short name T166
Test name
Test status
Simulation time 5014741623 ps
CPU time 30.53 seconds
Started Jul 23 06:10:23 PM PDT 24
Finished Jul 23 06:11:01 PM PDT 24
Peak memory 213316 kb
Host smart-e23f66c6-cee6-4a09-86c2-7ac58cb5fce3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403058789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.403058789
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2127114616
Short name T362
Test name
Test status
Simulation time 219110387 ps
CPU time 3.8 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 218500 kb
Host smart-8d698756-5c34-460c-a501-71e5ae820b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127114616 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2127114616
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3557634675
Short name T112
Test name
Test status
Simulation time 623622245 ps
CPU time 2.5 seconds
Started Jul 23 06:10:21 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 213316 kb
Host smart-cf5bb3e7-631a-484d-99bd-ee52cf378f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557634675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3557634675
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.744948025
Short name T306
Test name
Test status
Simulation time 22192820904 ps
CPU time 19.75 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 205040 kb
Host smart-6d9478b3-2f2e-4437-a3af-2ecb3ce75be1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744948025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.744948025
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.261089064
Short name T358
Test name
Test status
Simulation time 13911890435 ps
CPU time 22.95 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:36 PM PDT 24
Peak memory 204992 kb
Host smart-257a0dda-5515-48d8-9270-f38f10920b3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261089064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.261089064
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2571653002
Short name T417
Test name
Test status
Simulation time 185327980 ps
CPU time 0.92 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 204828 kb
Host smart-6e36c0c4-4b90-4663-b8c4-6f04f80687bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571653002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2571653002
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.405215025
Short name T90
Test name
Test status
Simulation time 617574737 ps
CPU time 7.85 seconds
Started Jul 23 06:10:16 PM PDT 24
Finished Jul 23 06:10:26 PM PDT 24
Peak memory 205040 kb
Host smart-fcab8f63-c004-499d-bc79-483534ba2cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405215025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.405215025
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.990151980
Short name T431
Test name
Test status
Simulation time 362070348 ps
CPU time 1.98 seconds
Started Jul 23 06:10:00 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 213316 kb
Host smart-c2212079-9444-41b6-a9f2-efcdfa495a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990151980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.990151980
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3940241096
Short name T160
Test name
Test status
Simulation time 4490310100 ps
CPU time 25.65 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:46 PM PDT 24
Peak memory 213224 kb
Host smart-a66bbc82-a4b2-48ea-b173-427d6a08d153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940241096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
940241096
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.389232803
Short name T334
Test name
Test status
Simulation time 731144865 ps
CPU time 3.84 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 221140 kb
Host smart-87890017-a142-47f8-8519-654d606fa0c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389232803 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.389232803
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3220735918
Short name T95
Test name
Test status
Simulation time 267732735 ps
CPU time 1.59 seconds
Started Jul 23 06:10:13 PM PDT 24
Finished Jul 23 06:10:17 PM PDT 24
Peak memory 213188 kb
Host smart-19c15308-0007-4b29-b7a8-c0d0d75a9dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220735918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3220735918
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.201052213
Short name T385
Test name
Test status
Simulation time 34002171893 ps
CPU time 82.78 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:11:52 PM PDT 24
Peak memory 205024 kb
Host smart-03244c70-84e2-4dc5-b743-9b0f9de14294
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201052213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.201052213
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.756221643
Short name T303
Test name
Test status
Simulation time 14825929185 ps
CPU time 25.01 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 205008 kb
Host smart-c3b3a59f-d4e3-423a-b86b-51a265794670
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756221643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.756221643
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2833845698
Short name T377
Test name
Test status
Simulation time 649480670 ps
CPU time 1.31 seconds
Started Jul 23 06:10:36 PM PDT 24
Finished Jul 23 06:10:43 PM PDT 24
Peak memory 204832 kb
Host smart-93073f58-6e60-4717-adc2-0f143f817109
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833845698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2833845698
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.787759785
Short name T124
Test name
Test status
Simulation time 3663975854 ps
CPU time 8.72 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:34 PM PDT 24
Peak memory 205048 kb
Host smart-14880348-3a74-4e5f-9166-9638f1a80394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787759785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.787759785
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.549955245
Short name T84
Test name
Test status
Simulation time 922061952 ps
CPU time 5.67 seconds
Started Jul 23 06:10:15 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 213344 kb
Host smart-571e9452-ac6a-4fbe-8d23-3e1928775e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549955245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.549955245
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3621179518
Short name T165
Test name
Test status
Simulation time 2488409852 ps
CPU time 10.89 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:21 PM PDT 24
Peak memory 213312 kb
Host smart-935b9246-3cf3-4496-8eea-2c4e169a1931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621179518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
621179518
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154484098
Short name T370
Test name
Test status
Simulation time 8279734187 ps
CPU time 33.37 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 213228 kb
Host smart-d8fbc41f-b09f-4e0b-81c0-0d76aa62512b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154484098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.4154484098
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.841631266
Short name T102
Test name
Test status
Simulation time 19697056199 ps
CPU time 71.28 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:11:08 PM PDT 24
Peak memory 205036 kb
Host smart-2bdfeea2-caa6-4633-8438-b9419c9745b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841631266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.841631266
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1791636561
Short name T120
Test name
Test status
Simulation time 57456522 ps
CPU time 1.57 seconds
Started Jul 23 06:09:51 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 213256 kb
Host smart-67f37a08-d278-4a09-b4f0-1454aa524a3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791636561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1791636561
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3181347002
Short name T340
Test name
Test status
Simulation time 810971714 ps
CPU time 4.07 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:01 PM PDT 24
Peak memory 221300 kb
Host smart-04faa36b-8a6a-454a-a830-504f61cfdf59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181347002 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3181347002
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.530842445
Short name T115
Test name
Test status
Simulation time 97024009 ps
CPU time 2.37 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 213284 kb
Host smart-6d6cbc45-0e04-4976-adb4-7985bed68bf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530842445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.530842445
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1774679604
Short name T314
Test name
Test status
Simulation time 16164888458 ps
CPU time 47.24 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:48 PM PDT 24
Peak memory 205068 kb
Host smart-bd0ee7a9-e9b9-4040-8bcc-c85338557d61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774679604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1774679604
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4018296877
Short name T401
Test name
Test status
Simulation time 48982303751 ps
CPU time 78.99 seconds
Started Jul 23 06:09:59 PM PDT 24
Finished Jul 23 06:11:20 PM PDT 24
Peak memory 204992 kb
Host smart-71a9a1b5-e998-4fc0-8c93-7c23cd55adb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018296877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.4018296877
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1998483465
Short name T99
Test name
Test status
Simulation time 3082921027 ps
CPU time 3.88 seconds
Started Jul 23 06:10:00 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 205092 kb
Host smart-ac0458f2-5a6f-4224-8293-ddfa1a2c2a39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998483465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1998483465
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.252446161
Short name T307
Test name
Test status
Simulation time 2706667729 ps
CPU time 4.27 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 205016 kb
Host smart-526b8dd5-e3ad-4a2c-9da5-ca2f6c893e05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252446161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.252446161
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3630876425
Short name T394
Test name
Test status
Simulation time 291261205 ps
CPU time 1 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:11 PM PDT 24
Peak memory 204716 kb
Host smart-69008266-858d-40cd-ac21-6ceaaccde824
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630876425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3630876425
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3143646807
Short name T330
Test name
Test status
Simulation time 8502213886 ps
CPU time 25.4 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:22 PM PDT 24
Peak memory 205056 kb
Host smart-30812d5f-9209-4162-add8-890c0040fb53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143646807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3143646807
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3300410716
Short name T304
Test name
Test status
Simulation time 276558363 ps
CPU time 0.83 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 204804 kb
Host smart-d78467c7-22af-4942-8ca6-6eaeb383d09e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300410716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3300410716
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.774017137
Short name T326
Test name
Test status
Simulation time 956178406 ps
CPU time 1.12 seconds
Started Jul 23 06:09:47 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 204804 kb
Host smart-7084f118-a614-4154-8062-bfe571f5aa29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774017137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.774017137
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1140821878
Short name T355
Test name
Test status
Simulation time 68637257 ps
CPU time 0.68 seconds
Started Jul 23 06:10:03 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 204624 kb
Host smart-54b55144-48b2-4158-ac21-0f844b724323
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140821878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1140821878
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.516382101
Short name T316
Test name
Test status
Simulation time 47621177 ps
CPU time 0.69 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:07 PM PDT 24
Peak memory 204828 kb
Host smart-9465ba37-3228-4a9d-a8b3-ad627a57fe78
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516382101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.516382101
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.264517674
Short name T121
Test name
Test status
Simulation time 1324375865 ps
CPU time 8.07 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:30 PM PDT 24
Peak memory 205004 kb
Host smart-34f26591-4c89-4f62-8545-5d6dc67f38fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264517674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.264517674
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2472350325
Short name T320
Test name
Test status
Simulation time 206041309 ps
CPU time 4.8 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:27 PM PDT 24
Peak memory 213288 kb
Host smart-c50408e2-6a1e-47f5-ab26-a0567a796f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472350325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2472350325
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2792335276
Short name T353
Test name
Test status
Simulation time 2975602438 ps
CPU time 27.84 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 205060 kb
Host smart-1a39feb8-cfcd-4661-bd9a-37e174b560cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792335276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2792335276
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2732198318
Short name T111
Test name
Test status
Simulation time 209893442 ps
CPU time 1.68 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:17 PM PDT 24
Peak memory 213268 kb
Host smart-84c4b96d-e2d7-4f2e-8932-2e7754bb70b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732198318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2732198318
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.344571443
Short name T127
Test name
Test status
Simulation time 711820090 ps
CPU time 4.21 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 221320 kb
Host smart-c400a9d0-e38c-47b0-8f43-8e73daad8e18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344571443 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.344571443
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3323030716
Short name T100
Test name
Test status
Simulation time 375824735 ps
CPU time 2.33 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:57 PM PDT 24
Peak memory 213236 kb
Host smart-0bc9b483-47b4-4b9d-9bfb-96811165942b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323030716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3323030716
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4196761262
Short name T429
Test name
Test status
Simulation time 90268467468 ps
CPU time 120.93 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:11:55 PM PDT 24
Peak memory 205148 kb
Host smart-2f8f3967-6d1b-4628-b785-7ea283ad5097
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196761262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4196761262
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3191334981
Short name T302
Test name
Test status
Simulation time 28327514643 ps
CPU time 28.25 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:25 PM PDT 24
Peak memory 205064 kb
Host smart-22c8269f-8496-4295-9435-648e43f801aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191334981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3191334981
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3862609517
Short name T325
Test name
Test status
Simulation time 1440253128 ps
CPU time 2.37 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 204924 kb
Host smart-071b26a1-d41a-48fd-aeb1-a0cabee4eb4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862609517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3862609517
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3849982596
Short name T433
Test name
Test status
Simulation time 3808348071 ps
CPU time 1.98 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:09 PM PDT 24
Peak memory 205016 kb
Host smart-4eac3f9b-a819-4d5f-bd89-b1bd79d69429
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849982596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
849982596
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2987055859
Short name T329
Test name
Test status
Simulation time 472724335 ps
CPU time 1.38 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 204808 kb
Host smart-7d22b71e-f4d5-432d-b1c7-6bf73305b61d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987055859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2987055859
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4033389502
Short name T422
Test name
Test status
Simulation time 7994093642 ps
CPU time 5.3 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 205088 kb
Host smart-8b400bd5-f2f4-4a8b-b268-a7010b23004e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033389502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4033389502
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.374259915
Short name T312
Test name
Test status
Simulation time 175654348 ps
CPU time 1.17 seconds
Started Jul 23 06:09:48 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 204840 kb
Host smart-0c131e42-3659-4cde-afd3-466de26c1c9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374259915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.374259915
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1447137583
Short name T327
Test name
Test status
Simulation time 227026021 ps
CPU time 1.03 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 204716 kb
Host smart-c1d6f020-3a4a-4854-9b5c-6798e911ae2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447137583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
447137583
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.302804197
Short name T319
Test name
Test status
Simulation time 66128741 ps
CPU time 0.69 seconds
Started Jul 23 06:10:03 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 204728 kb
Host smart-95233afd-da0c-4a4a-b919-8bcb49b4b13c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302804197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.302804197
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1118943629
Short name T364
Test name
Test status
Simulation time 37616885 ps
CPU time 0.7 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 204820 kb
Host smart-fa10cc0a-d2f4-42df-b9ef-0f7f9765b53e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118943629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1118943629
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2968001117
Short name T438
Test name
Test status
Simulation time 619061124 ps
CPU time 4.3 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 205020 kb
Host smart-b6f84dcc-a8d7-486e-b079-9692b21bf653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968001117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2968001117
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3667597785
Short name T391
Test name
Test status
Simulation time 24721624304 ps
CPU time 49.34 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:56 PM PDT 24
Peak memory 219688 kb
Host smart-dd863bfd-5187-4a38-b37d-8bdacff0f3bd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667597785 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3667597785
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2819115205
Short name T418
Test name
Test status
Simulation time 77004973 ps
CPU time 2.48 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 213204 kb
Host smart-e9263403-7fb6-4b95-a6b4-0a991dd38896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819115205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2819115205
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3879504692
Short name T153
Test name
Test status
Simulation time 1936993493 ps
CPU time 11.08 seconds
Started Jul 23 06:09:51 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 213260 kb
Host smart-641224e9-9230-4fc5-a990-ca32c6169009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879504692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3879504692
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1859215115
Short name T119
Test name
Test status
Simulation time 7626553429 ps
CPU time 75.18 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:11:18 PM PDT 24
Peak memory 213500 kb
Host smart-bb8acf54-11f6-414d-97ca-0583404283d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859215115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1859215115
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4048332192
Short name T114
Test name
Test status
Simulation time 3850006709 ps
CPU time 38.18 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:53 PM PDT 24
Peak memory 205104 kb
Host smart-637e0384-4594-4347-8234-9091fd0c7133
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048332192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4048332192
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2663568903
Short name T356
Test name
Test status
Simulation time 290294476 ps
CPU time 2.06 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:05 PM PDT 24
Peak memory 213244 kb
Host smart-e0dcec43-10bd-4143-adb9-b4b48692985c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663568903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2663568903
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.4190643480
Short name T343
Test name
Test status
Simulation time 557554881 ps
CPU time 2.37 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:10:30 PM PDT 24
Peak memory 217460 kb
Host smart-26e7a3ef-06e5-4924-a5e6-40ec46ad2a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190643480 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.4190643480
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1197112975
Short name T94
Test name
Test status
Simulation time 201221902 ps
CPU time 1.49 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:09 PM PDT 24
Peak memory 213192 kb
Host smart-ba10ddfd-9af0-41e3-8364-c0286d2109c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197112975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1197112975
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.939608222
Short name T310
Test name
Test status
Simulation time 19506816087 ps
CPU time 21.09 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:41 PM PDT 24
Peak memory 205044 kb
Host smart-10d6f2b7-c12e-4f74-8234-4bda477df7c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939608222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.939608222
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.892885619
Short name T299
Test name
Test status
Simulation time 15575095741 ps
CPU time 23.37 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 204988 kb
Host smart-475f91c5-60e6-4fde-bae0-55aa65fc0750
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892885619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.892885619
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3991708571
Short name T97
Test name
Test status
Simulation time 6291247561 ps
CPU time 5.33 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:53 PM PDT 24
Peak memory 205088 kb
Host smart-9c69fd10-b108-413b-b2c4-18bfa2c6a49a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991708571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3991708571
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3492250116
Short name T354
Test name
Test status
Simulation time 1518677206 ps
CPU time 2.85 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:53 PM PDT 24
Peak memory 204956 kb
Host smart-3ec92725-b8d9-4db2-bc9d-70e6df2d668c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492250116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
492250116
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2060081759
Short name T75
Test name
Test status
Simulation time 404343665 ps
CPU time 1.7 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:12 PM PDT 24
Peak memory 204812 kb
Host smart-361121d0-2ac5-4bb7-bd5f-3a6fce01a7a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060081759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2060081759
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.41146299
Short name T322
Test name
Test status
Simulation time 34056341189 ps
CPU time 42.88 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:54 PM PDT 24
Peak memory 205012 kb
Host smart-bf620835-a276-4f06-b1d2-43c69225a169
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
bit_bash.41146299
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3608876452
Short name T368
Test name
Test status
Simulation time 178091682 ps
CPU time 0.96 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 204700 kb
Host smart-78dbc3b8-8b54-49cb-b9ac-7f3ab8bffde8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608876452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3608876452
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1020140284
Short name T402
Test name
Test status
Simulation time 286462838 ps
CPU time 0.84 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 204796 kb
Host smart-747edce2-4b2e-43d8-80d1-45cab476b030
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020140284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
020140284
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.908011747
Short name T348
Test name
Test status
Simulation time 130728322 ps
CPU time 0.7 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 204724 kb
Host smart-55bc3ed1-375c-4cbd-8e74-f8d597ad6454
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908011747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.908011747
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2180229278
Short name T323
Test name
Test status
Simulation time 101675936 ps
CPU time 0.96 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 204828 kb
Host smart-52a8a39d-af85-4b67-98ab-87652a696c93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180229278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2180229278
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.301941371
Short name T122
Test name
Test status
Simulation time 198138971 ps
CPU time 6.7 seconds
Started Jul 23 06:10:29 PM PDT 24
Finished Jul 23 06:10:44 PM PDT 24
Peak memory 205120 kb
Host smart-b6755240-5ba6-45a8-8435-d3ae854207c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301941371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.301941371
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.782266263
Short name T168
Test name
Test status
Simulation time 12088396075 ps
CPU time 45.14 seconds
Started Jul 23 06:10:15 PM PDT 24
Finished Jul 23 06:11:02 PM PDT 24
Peak memory 221444 kb
Host smart-a975b560-734f-4c88-a687-4fe15c0ec083
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782266263 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.782266263
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2256548728
Short name T338
Test name
Test status
Simulation time 364517238 ps
CPU time 3.8 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:13 PM PDT 24
Peak memory 213288 kb
Host smart-ac201b68-2fbe-4aaf-a3f1-581620e6da3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256548728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2256548728
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1659441270
Short name T156
Test name
Test status
Simulation time 2807075324 ps
CPU time 9.7 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 213336 kb
Host smart-e048f382-7856-44d1-bbe5-5055b54e6e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659441270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1659441270
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.554913348
Short name T80
Test name
Test status
Simulation time 385792554 ps
CPU time 2.45 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:27 PM PDT 24
Peak memory 217924 kb
Host smart-07a6a0d4-7fa6-4121-9c7b-520095a2998d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554913348 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.554913348
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.634737401
Short name T101
Test name
Test status
Simulation time 253359883 ps
CPU time 2.2 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 213156 kb
Host smart-ac314b0d-5a32-4404-926d-dfd3e3d0f755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634737401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.634737401
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2663382505
Short name T403
Test name
Test status
Simulation time 8287078128 ps
CPU time 27.07 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:48 PM PDT 24
Peak memory 204972 kb
Host smart-66427d24-9fb1-4512-9209-acf2bf7985d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663382505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2663382505
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3076479795
Short name T393
Test name
Test status
Simulation time 1577706324 ps
CPU time 1.51 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 204988 kb
Host smart-6b60b175-fb63-4809-89eb-8a9aad2d8d59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076479795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
076479795
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.354614279
Short name T372
Test name
Test status
Simulation time 457089817 ps
CPU time 0.85 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:15 PM PDT 24
Peak memory 204812 kb
Host smart-963bdc35-1a10-4391-9b9f-f4c7df1c8c47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354614279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.354614279
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.330925391
Short name T103
Test name
Test status
Simulation time 163132822 ps
CPU time 3.72 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:25 PM PDT 24
Peak memory 205052 kb
Host smart-c354e7b2-6dfd-486f-a5c8-22b6fcc79d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330925391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.330925391
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1673702582
Short name T167
Test name
Test status
Simulation time 57293937967 ps
CPU time 63.06 seconds
Started Jul 23 06:10:08 PM PDT 24
Finished Jul 23 06:11:13 PM PDT 24
Peak memory 221696 kb
Host smart-0891b492-c0a4-4f3e-9210-65a089651094
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673702582 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1673702582
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.656100034
Short name T318
Test name
Test status
Simulation time 192721053 ps
CPU time 4.57 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:17 PM PDT 24
Peak memory 213236 kb
Host smart-08243652-72da-4e0b-bd17-e03fa9cc8fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656100034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.656100034
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4074646717
Short name T161
Test name
Test status
Simulation time 3363267205 ps
CPU time 13.7 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:24 PM PDT 24
Peak memory 213300 kb
Host smart-fddecf96-ae32-4464-844e-acff82cdd803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074646717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4074646717
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3947168310
Short name T386
Test name
Test status
Simulation time 360093627 ps
CPU time 4.01 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:12 PM PDT 24
Peak memory 221328 kb
Host smart-421421c8-0ed6-4a46-aeb3-21fa25b805bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947168310 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3947168310
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2850897607
Short name T381
Test name
Test status
Simulation time 187728773 ps
CPU time 1.58 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:16 PM PDT 24
Peak memory 213212 kb
Host smart-17cb0f8e-e7ab-46e9-a8cd-f5659fe33b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850897607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2850897607
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2539744753
Short name T363
Test name
Test status
Simulation time 81524600577 ps
CPU time 202.36 seconds
Started Jul 23 06:10:02 PM PDT 24
Finished Jul 23 06:13:27 PM PDT 24
Peak memory 204992 kb
Host smart-03aea388-5919-452b-8ac3-a3ec65a099c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539744753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2539744753
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.122990769
Short name T412
Test name
Test status
Simulation time 5723724162 ps
CPU time 5.07 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:25 PM PDT 24
Peak memory 204992 kb
Host smart-c0229a09-485f-4b34-88d6-157150681399
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122990769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.122990769
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.653809931
Short name T341
Test name
Test status
Simulation time 1108292435 ps
CPU time 1.98 seconds
Started Jul 23 06:10:17 PM PDT 24
Finished Jul 23 06:10:30 PM PDT 24
Peak memory 204796 kb
Host smart-97234866-5e93-45bb-96c8-68035142d99f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653809931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.653809931
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1199273735
Short name T123
Test name
Test status
Simulation time 1865583791 ps
CPU time 8.08 seconds
Started Jul 23 06:10:10 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 205000 kb
Host smart-d6a67b13-85cc-452a-9db0-4f36a53c75ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199273735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1199273735
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1975542032
Short name T79
Test name
Test status
Simulation time 27234010018 ps
CPU time 45.31 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:11:00 PM PDT 24
Peak memory 219864 kb
Host smart-9b78609c-852f-483b-8845-666c77eb9875
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975542032 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1975542032
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2239589758
Short name T440
Test name
Test status
Simulation time 1341386627 ps
CPU time 9.36 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:13 PM PDT 24
Peak memory 213280 kb
Host smart-c7a5d832-d655-4b3e-897c-63e6537703be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239589758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2239589758
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3268524423
Short name T347
Test name
Test status
Simulation time 258408145 ps
CPU time 2.75 seconds
Started Jul 23 06:10:21 PM PDT 24
Finished Jul 23 06:10:29 PM PDT 24
Peak memory 218136 kb
Host smart-0f967d5b-8431-4afd-a1e5-621326dad9aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268524423 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3268524423
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3383899993
Short name T406
Test name
Test status
Simulation time 406846555 ps
CPU time 2.24 seconds
Started Jul 23 06:10:08 PM PDT 24
Finished Jul 23 06:10:12 PM PDT 24
Peak memory 213208 kb
Host smart-45f3ea6e-d128-48cd-8618-da960a222ce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383899993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3383899993
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1582463014
Short name T342
Test name
Test status
Simulation time 11837757212 ps
CPU time 28.97 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:37 PM PDT 24
Peak memory 205012 kb
Host smart-05086d31-6480-42d1-8d5f-3d2aa0821ea0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582463014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1582463014
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3270732511
Short name T435
Test name
Test status
Simulation time 2975143066 ps
CPU time 8.92 seconds
Started Jul 23 06:10:03 PM PDT 24
Finished Jul 23 06:10:14 PM PDT 24
Peak memory 204892 kb
Host smart-18a0256f-324c-47e7-b85e-173aef4de8b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270732511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
270732511
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3170142236
Short name T407
Test name
Test status
Simulation time 394522223 ps
CPU time 0.96 seconds
Started Jul 23 06:10:29 PM PDT 24
Finished Jul 23 06:10:39 PM PDT 24
Peak memory 204808 kb
Host smart-f462f018-46e1-4cc4-bcc3-9e218caa774e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170142236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
170142236
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1786265152
Short name T89
Test name
Test status
Simulation time 2315626847 ps
CPU time 8.58 seconds
Started Jul 23 06:10:30 PM PDT 24
Finished Jul 23 06:10:47 PM PDT 24
Peak memory 205088 kb
Host smart-9574c634-22f9-4148-9904-ed2a10878617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786265152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1786265152
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3487462829
Short name T404
Test name
Test status
Simulation time 59009694278 ps
CPU time 47.75 seconds
Started Jul 23 06:10:22 PM PDT 24
Finished Jul 23 06:11:15 PM PDT 24
Peak memory 223560 kb
Host smart-4366dcd1-1b81-4654-aa27-5aa3f87be152
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487462829 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3487462829
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.101441919
Short name T375
Test name
Test status
Simulation time 246674190 ps
CPU time 4.42 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:03 PM PDT 24
Peak memory 213308 kb
Host smart-8d04385d-aae7-488f-bd82-a2414a2e36f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101441919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.101441919
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3096239483
Short name T155
Test name
Test status
Simulation time 1343478707 ps
CPU time 15.54 seconds
Started Jul 23 06:10:15 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 213252 kb
Host smart-8d9b41a0-92e1-4c85-ad58-2cda5efe076a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096239483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3096239483
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1592310845
Short name T410
Test name
Test status
Simulation time 302730942 ps
CPU time 3.29 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 216640 kb
Host smart-985f4733-2179-4172-9380-4f4ac1d0830b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592310845 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1592310845
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3712125329
Short name T105
Test name
Test status
Simulation time 46311233 ps
CPU time 1.51 seconds
Started Jul 23 06:10:07 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 213288 kb
Host smart-e7582957-ae19-4b83-9cbd-7b3022d0ce9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712125329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3712125329
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.421209874
Short name T379
Test name
Test status
Simulation time 17217733128 ps
CPU time 25.69 seconds
Started Jul 23 06:10:20 PM PDT 24
Finished Jul 23 06:10:51 PM PDT 24
Peak memory 204976 kb
Host smart-325e6a35-deaa-4128-82bb-15242e079f39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421209874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.421209874
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2869763412
Short name T313
Test name
Test status
Simulation time 1468542516 ps
CPU time 3.24 seconds
Started Jul 23 06:10:19 PM PDT 24
Finished Jul 23 06:10:26 PM PDT 24
Peak memory 204956 kb
Host smart-59d448b0-cecf-4cfc-aec0-9517082d7668
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869763412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
869763412
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3655224628
Short name T380
Test name
Test status
Simulation time 302168238 ps
CPU time 1.14 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:09 PM PDT 24
Peak memory 204804 kb
Host smart-d38f753b-accc-4bf9-aa45-3452b77e80ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655224628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
655224628
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.914503907
Short name T426
Test name
Test status
Simulation time 1013404107 ps
CPU time 4.15 seconds
Started Jul 23 06:10:14 PM PDT 24
Finished Jul 23 06:10:20 PM PDT 24
Peak memory 205088 kb
Host smart-835641aa-4d40-4ccc-a03d-dccc88f2923c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914503907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.914503907
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.211891814
Short name T383
Test name
Test status
Simulation time 36240633593 ps
CPU time 13.97 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:29 PM PDT 24
Peak memory 221492 kb
Host smart-4d5019e4-7895-4845-a9d4-7748dca2bae6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211891814 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.211891814
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2399270354
Short name T369
Test name
Test status
Simulation time 111632247 ps
CPU time 2.5 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:07 PM PDT 24
Peak memory 213328 kb
Host smart-08825207-64d7-433b-a9d8-e7f7a82cfcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399270354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2399270354
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1606270721
Short name T152
Test name
Test status
Simulation time 1030790213 ps
CPU time 10.02 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:10 PM PDT 24
Peak memory 213268 kb
Host smart-2d2c12d4-00a7-4e3d-8d0d-535e6a6f9cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606270721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1606270721
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4140274595
Short name T337
Test name
Test status
Simulation time 273156639 ps
CPU time 4.13 seconds
Started Jul 23 06:10:06 PM PDT 24
Finished Jul 23 06:10:12 PM PDT 24
Peak memory 219704 kb
Host smart-40c78589-3024-41a2-aa0c-ae7356097498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140274595 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4140274595
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1459490776
Short name T117
Test name
Test status
Simulation time 422488466 ps
CPU time 2.48 seconds
Started Jul 23 06:10:26 PM PDT 24
Finished Jul 23 06:10:38 PM PDT 24
Peak memory 213224 kb
Host smart-8af11f5f-9220-4da8-9f5d-a2e39072e359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459490776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1459490776
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1834893356
Short name T308
Test name
Test status
Simulation time 16350162091 ps
CPU time 27.87 seconds
Started Jul 23 06:10:02 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 204980 kb
Host smart-c9b3c25e-524a-405d-8a94-1d6e09258478
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834893356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1834893356
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1143554839
Short name T321
Test name
Test status
Simulation time 5774910564 ps
CPU time 12.3 seconds
Started Jul 23 06:10:08 PM PDT 24
Finished Jul 23 06:10:22 PM PDT 24
Peak memory 205004 kb
Host smart-e6dbab22-0997-4541-ab5d-3c10557d223c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143554839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
143554839
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.997434473
Short name T366
Test name
Test status
Simulation time 391858614 ps
CPU time 1.26 seconds
Started Jul 23 06:10:08 PM PDT 24
Finished Jul 23 06:10:11 PM PDT 24
Peak memory 204792 kb
Host smart-b84b858c-f836-4d1e-a472-96eab96b99b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997434473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.997434473
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2779091259
Short name T425
Test name
Test status
Simulation time 679530417 ps
CPU time 8.15 seconds
Started Jul 23 06:10:12 PM PDT 24
Finished Jul 23 06:10:23 PM PDT 24
Peak memory 205040 kb
Host smart-4d107c77-8b81-4ee3-94f6-90ef589d7c58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779091259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2779091259
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2126379691
Short name T60
Test name
Test status
Simulation time 21610358928 ps
CPU time 61.68 seconds
Started Jul 23 06:10:02 PM PDT 24
Finished Jul 23 06:11:06 PM PDT 24
Peak memory 221412 kb
Host smart-b534d729-4a1a-477f-94ab-553644b971ad
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126379691 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2126379691
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3141024669
Short name T360
Test name
Test status
Simulation time 816349515 ps
CPU time 5.42 seconds
Started Jul 23 06:10:04 PM PDT 24
Finished Jul 23 06:10:11 PM PDT 24
Peak memory 213272 kb
Host smart-76955810-102b-4c42-baf7-a005c646d9ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141024669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3141024669
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3749887928
Short name T164
Test name
Test status
Simulation time 1545413193 ps
CPU time 9.88 seconds
Started Jul 23 06:10:18 PM PDT 24
Finished Jul 23 06:10:32 PM PDT 24
Peak memory 213224 kb
Host smart-2b8d3d03-df0a-4606-a0ea-4ec8eeb444ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749887928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3749887928
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4023096934
Short name T207
Test name
Test status
Simulation time 4239805366 ps
CPU time 3.84 seconds
Started Jul 23 06:14:04 PM PDT 24
Finished Jul 23 06:14:09 PM PDT 24
Peak memory 213564 kb
Host smart-54ed0303-bb71-451c-b98e-f93724af4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023096934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4023096934
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1815181827
Short name T236
Test name
Test status
Simulation time 14431488725 ps
CPU time 38.65 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 213624 kb
Host smart-953340bf-b103-4eca-9209-95cc8b9cb525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815181827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1815181827
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2244772689
Short name T12
Test name
Test status
Simulation time 305355863 ps
CPU time 0.89 seconds
Started Jul 23 06:14:08 PM PDT 24
Finished Jul 23 06:14:10 PM PDT 24
Peak memory 204988 kb
Host smart-d7d42cbc-0b6f-44e7-b1e1-6063dfbe8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244772689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2244772689
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3282119847
Short name T19
Test name
Test status
Simulation time 545617505 ps
CPU time 1.59 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 204988 kb
Host smart-a1692659-61c2-49bb-846c-ad31e9369faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282119847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3282119847
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.965617077
Short name T38
Test name
Test status
Simulation time 581397578 ps
CPU time 1.16 seconds
Started Jul 23 06:14:11 PM PDT 24
Finished Jul 23 06:14:14 PM PDT 24
Peak memory 204944 kb
Host smart-44761321-a524-4c16-876b-09ba331c9f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965617077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.965617077
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2457070385
Short name T36
Test name
Test status
Simulation time 751646232 ps
CPU time 1.6 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204948 kb
Host smart-0e69913d-98b2-443a-a84c-7a59741a92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457070385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2457070385
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2126417329
Short name T200
Test name
Test status
Simulation time 388001755 ps
CPU time 1.13 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 204972 kb
Host smart-9c3b2cf4-ee6f-41e1-bd12-2384446c2b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126417329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2126417329
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.462660289
Short name T281
Test name
Test status
Simulation time 1226371578 ps
CPU time 1.55 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:14 PM PDT 24
Peak memory 205340 kb
Host smart-6aa357b8-4680-4ae5-93b5-e0a72849d9b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462660289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.462660289
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3317978262
Short name T42
Test name
Test status
Simulation time 426351802 ps
CPU time 1.04 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:15 PM PDT 24
Peak memory 204932 kb
Host smart-184c0ada-ce38-49c3-8dca-d6a898b9f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317978262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3317978262
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2219642032
Short name T223
Test name
Test status
Simulation time 639391727 ps
CPU time 2.37 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204856 kb
Host smart-d06ed0b1-815d-4bcb-a1be-73599ef30556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219642032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2219642032
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1150833007
Short name T277
Test name
Test status
Simulation time 329904072 ps
CPU time 0.77 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204972 kb
Host smart-0e1535c1-93b6-4700-a574-682ae657cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150833007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1150833007
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3989569259
Short name T267
Test name
Test status
Simulation time 346494029 ps
CPU time 0.9 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:15 PM PDT 24
Peak memory 204920 kb
Host smart-c4af2e03-451f-4ff1-bbdc-20547b5976f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989569259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3989569259
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2166748390
Short name T273
Test name
Test status
Simulation time 824231247 ps
CPU time 3.09 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 204972 kb
Host smart-79a01f31-0c99-4d11-80a9-c4e2d4c91dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166748390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2166748390
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2544818913
Short name T257
Test name
Test status
Simulation time 292257847 ps
CPU time 1.52 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 204948 kb
Host smart-4b9e71d0-b0b6-447d-942c-41efdf234271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544818913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2544818913
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2065311376
Short name T150
Test name
Test status
Simulation time 207227460 ps
CPU time 1.17 seconds
Started Jul 23 06:14:04 PM PDT 24
Finished Jul 23 06:14:06 PM PDT 24
Peak memory 204972 kb
Host smart-c2e72d50-a020-48ed-b8f1-b50da84e4294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065311376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2065311376
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2765957964
Short name T136
Test name
Test status
Simulation time 553293878 ps
CPU time 1.21 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 204940 kb
Host smart-fbe84021-d253-4f35-99cf-5c0cc14bed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765957964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2765957964
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.221014641
Short name T37
Test name
Test status
Simulation time 123030591 ps
CPU time 1.06 seconds
Started Jul 23 06:14:10 PM PDT 24
Finished Jul 23 06:14:11 PM PDT 24
Peak memory 213196 kb
Host smart-1457013e-46ec-49dd-a13d-1311a764b150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221014641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.221014641
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1587977643
Short name T201
Test name
Test status
Simulation time 1126532272 ps
CPU time 2.54 seconds
Started Jul 23 06:14:13 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 205328 kb
Host smart-ac9607d9-dee7-4ef0-9faa-c21c86b9121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587977643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1587977643
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1375542052
Short name T54
Test name
Test status
Simulation time 630682088 ps
CPU time 1.32 seconds
Started Jul 23 06:14:12 PM PDT 24
Finished Jul 23 06:14:16 PM PDT 24
Peak memory 229528 kb
Host smart-1e791adf-6fb8-47f7-8646-5b5148d88ecd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375542052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1375542052
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2589540964
Short name T259
Test name
Test status
Simulation time 711870785 ps
CPU time 2.67 seconds
Started Jul 23 06:14:05 PM PDT 24
Finished Jul 23 06:14:08 PM PDT 24
Peak memory 204976 kb
Host smart-502fe642-51d4-433d-932e-7261fab118ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589540964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2589540964
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.245949062
Short name T72
Test name
Test status
Simulation time 6598241972 ps
CPU time 11 seconds
Started Jul 23 06:14:11 PM PDT 24
Finished Jul 23 06:14:23 PM PDT 24
Peak memory 205184 kb
Host smart-4e58d90b-5f94-442e-9c7a-125adf2b237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245949062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.245949062
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.493459127
Short name T47
Test name
Test status
Simulation time 106149717 ps
CPU time 0.87 seconds
Started Jul 23 06:14:26 PM PDT 24
Finished Jul 23 06:14:27 PM PDT 24
Peak memory 204960 kb
Host smart-5cd8fd45-8c78-45e3-ba93-3f9d34be7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493459127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.493459127
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2614732473
Short name T196
Test name
Test status
Simulation time 36193979 ps
CPU time 0.76 seconds
Started Jul 23 06:14:32 PM PDT 24
Finished Jul 23 06:14:33 PM PDT 24
Peak memory 204956 kb
Host smart-2dcd49f1-766b-4714-9f8b-4d22a755293a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614732473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2614732473
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2468805975
Short name T182
Test name
Test status
Simulation time 11610853460 ps
CPU time 6.17 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 216860 kb
Host smart-541aadca-ec10-4dd5-843a-e4e49a77b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468805975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2468805975
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2752957898
Short name T26
Test name
Test status
Simulation time 1020258577 ps
CPU time 1.25 seconds
Started Jul 23 06:14:16 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 205572 kb
Host smart-e818e46e-7238-402b-aecf-809da291b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752957898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2752957898
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3602565561
Short name T22
Test name
Test status
Simulation time 539605156 ps
CPU time 1.1 seconds
Started Jul 23 06:14:16 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 204984 kb
Host smart-9878b946-a1e9-499b-8e5d-dbe958a0f8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602565561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3602565561
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3010651728
Short name T283
Test name
Test status
Simulation time 219070483 ps
CPU time 1.3 seconds
Started Jul 23 06:14:23 PM PDT 24
Finished Jul 23 06:14:25 PM PDT 24
Peak memory 204932 kb
Host smart-4042b23d-f2a1-4885-974c-3b66b6cb68dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010651728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3010651728
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1455111104
Short name T280
Test name
Test status
Simulation time 212922106 ps
CPU time 0.98 seconds
Started Jul 23 06:14:23 PM PDT 24
Finished Jul 23 06:14:24 PM PDT 24
Peak memory 204936 kb
Host smart-857628a4-9cfe-4e24-97d8-eb78dbba35b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455111104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1455111104
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.861236546
Short name T6
Test name
Test status
Simulation time 111659510 ps
CPU time 1.07 seconds
Started Jul 23 06:14:25 PM PDT 24
Finished Jul 23 06:14:26 PM PDT 24
Peak memory 215152 kb
Host smart-f228cd54-9797-44fe-b743-020f6489388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861236546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.861236546
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3223459000
Short name T239
Test name
Test status
Simulation time 3612778466 ps
CPU time 10.12 seconds
Started Jul 23 06:14:14 PM PDT 24
Finished Jul 23 06:14:26 PM PDT 24
Peak memory 205244 kb
Host smart-120e1a15-9721-4b81-8a71-f61e772a5c7a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223459000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3223459000
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.2189974501
Short name T56
Test name
Test status
Simulation time 627012682 ps
CPU time 2.39 seconds
Started Jul 23 06:14:24 PM PDT 24
Finished Jul 23 06:14:27 PM PDT 24
Peak memory 204900 kb
Host smart-11e8cd2b-4784-4a68-a367-9d7c436a9f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189974501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2189974501
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1924273281
Short name T228
Test name
Test status
Simulation time 443010919 ps
CPU time 1.66 seconds
Started Jul 23 06:14:19 PM PDT 24
Finished Jul 23 06:14:21 PM PDT 24
Peak memory 204864 kb
Host smart-a8ed3a64-69be-45ae-a194-580b09276e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924273281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1924273281
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3599568273
Short name T268
Test name
Test status
Simulation time 1091271938 ps
CPU time 3.5 seconds
Started Jul 23 06:14:18 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 204928 kb
Host smart-49783168-f991-4114-9bad-ad12eac9833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599568273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3599568273
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.375182800
Short name T70
Test name
Test status
Simulation time 2450308018 ps
CPU time 5.65 seconds
Started Jul 23 06:14:23 PM PDT 24
Finished Jul 23 06:14:30 PM PDT 24
Peak memory 205028 kb
Host smart-003455f7-c597-4d9d-a432-c7f2f175d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375182800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.375182800
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2814702732
Short name T237
Test name
Test status
Simulation time 165115172 ps
CPU time 0.79 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:21 PM PDT 24
Peak memory 204964 kb
Host smart-71ad884b-cbca-489c-9f33-29462a710e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814702732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2814702732
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1139786967
Short name T180
Test name
Test status
Simulation time 759535232 ps
CPU time 1.35 seconds
Started Jul 23 06:14:21 PM PDT 24
Finished Jul 23 06:14:23 PM PDT 24
Peak memory 204972 kb
Host smart-4925434d-76b7-441f-a5c0-a66070dc3ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139786967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1139786967
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3243294260
Short name T178
Test name
Test status
Simulation time 591251141 ps
CPU time 1.46 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 204956 kb
Host smart-832769a2-4a26-41f8-a2df-abac297d5ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243294260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3243294260
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.336762188
Short name T177
Test name
Test status
Simulation time 386656728 ps
CPU time 1.61 seconds
Started Jul 23 06:14:21 PM PDT 24
Finished Jul 23 06:14:23 PM PDT 24
Peak memory 213068 kb
Host smart-35a734f3-5400-4786-88ed-79a5a53c78f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336762188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.336762188
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2406076221
Short name T46
Test name
Test status
Simulation time 708639966 ps
CPU time 1.94 seconds
Started Jul 23 06:14:28 PM PDT 24
Finished Jul 23 06:14:30 PM PDT 24
Peak memory 204944 kb
Host smart-4c4c8eb1-a9c0-455f-908f-fbb4b712ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406076221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2406076221
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3996526136
Short name T40
Test name
Test status
Simulation time 38052502 ps
CPU time 0.92 seconds
Started Jul 23 06:14:24 PM PDT 24
Finished Jul 23 06:14:26 PM PDT 24
Peak memory 213172 kb
Host smart-00e6f468-1f9b-40c8-b172-d0149183d1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996526136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3996526136
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3603900013
Short name T77
Test name
Test status
Simulation time 1621844304 ps
CPU time 1.79 seconds
Started Jul 23 06:14:20 PM PDT 24
Finished Jul 23 06:14:22 PM PDT 24
Peak memory 205168 kb
Host smart-e2b2e374-b1cc-4346-ab03-8d752c092e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603900013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3603900013
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2792982866
Short name T64
Test name
Test status
Simulation time 1711267636 ps
CPU time 3.08 seconds
Started Jul 23 06:14:31 PM PDT 24
Finished Jul 23 06:14:35 PM PDT 24
Peak memory 229236 kb
Host smart-25a6b1d0-0208-4e6b-be94-d15eb3ea18cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792982866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2792982866
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2706887022
Short name T282
Test name
Test status
Simulation time 901723180 ps
CPU time 1.14 seconds
Started Jul 23 06:14:16 PM PDT 24
Finished Jul 23 06:14:18 PM PDT 24
Peak memory 205148 kb
Host smart-d432e23c-ca00-4ac1-b56f-ac44061f80f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706887022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2706887022
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2032340759
Short name T229
Test name
Test status
Simulation time 163677397 ps
CPU time 0.76 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:14:57 PM PDT 24
Peak memory 205024 kb
Host smart-251964c5-c449-458a-b19f-03e462751622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032340759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2032340759
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3077882625
Short name T186
Test name
Test status
Simulation time 7102308270 ps
CPU time 3.68 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:01 PM PDT 24
Peak memory 213592 kb
Host smart-50e2c238-80c0-4fbc-a8e3-755ce467fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077882625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3077882625
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.515471901
Short name T256
Test name
Test status
Simulation time 1751909603 ps
CPU time 2.38 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:01 PM PDT 24
Peak memory 205260 kb
Host smart-1d2f5062-96b6-44be-82b2-0d97d80805ce
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515471901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.515471901
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.945981767
Short name T219
Test name
Test status
Simulation time 12898999834 ps
CPU time 4.8 seconds
Started Jul 23 06:14:59 PM PDT 24
Finished Jul 23 06:15:05 PM PDT 24
Peak memory 205344 kb
Host smart-9741db14-4cf3-4d64-984c-2d97ebdd3322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945981767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.945981767
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3175893533
Short name T193
Test name
Test status
Simulation time 52518717 ps
CPU time 0.77 seconds
Started Jul 23 06:14:58 PM PDT 24
Finished Jul 23 06:15:00 PM PDT 24
Peak memory 205064 kb
Host smart-ebf6d51e-0119-4ffe-b7be-145199a1a195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175893533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3175893533
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2426471985
Short name T212
Test name
Test status
Simulation time 2130127144 ps
CPU time 4.02 seconds
Started Jul 23 06:14:53 PM PDT 24
Finished Jul 23 06:14:58 PM PDT 24
Peak memory 213540 kb
Host smart-da549044-1ce1-4864-9957-3210ee202cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426471985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2426471985
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3117581067
Short name T197
Test name
Test status
Simulation time 1505589149 ps
CPU time 2.57 seconds
Started Jul 23 06:15:03 PM PDT 24
Finished Jul 23 06:15:07 PM PDT 24
Peak memory 205340 kb
Host smart-cd6f232d-4cd0-4e1f-8c5f-29bb8716a965
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117581067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3117581067
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1345465615
Short name T233
Test name
Test status
Simulation time 7506915902 ps
CPU time 6.14 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:05 PM PDT 24
Peak memory 205312 kb
Host smart-d2cfa059-2c60-403e-9a0f-d2e0d28edc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345465615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1345465615
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2016348944
Short name T71
Test name
Test status
Simulation time 2472046145 ps
CPU time 3.61 seconds
Started Jul 23 06:14:59 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 213368 kb
Host smart-8550fffe-60e6-4057-9ef7-d55e5f414d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016348944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2016348944
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2128412714
Short name T240
Test name
Test status
Simulation time 78441447 ps
CPU time 0.76 seconds
Started Jul 23 06:14:58 PM PDT 24
Finished Jul 23 06:15:01 PM PDT 24
Peak memory 205008 kb
Host smart-d3fcb5f6-8e5e-43f8-b587-58e0a36e9c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128412714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2128412714
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3070205274
Short name T287
Test name
Test status
Simulation time 20767431005 ps
CPU time 55.25 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 213600 kb
Host smart-552270bf-cdbb-4fd3-a4db-e945fa61c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070205274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3070205274
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.538916159
Short name T187
Test name
Test status
Simulation time 9436944341 ps
CPU time 10.77 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:10 PM PDT 24
Peak memory 215116 kb
Host smart-0bea33b2-3d94-409c-a0bf-db4c2dc44404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538916159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.538916159
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2867179232
Short name T274
Test name
Test status
Simulation time 1469059233 ps
CPU time 1.89 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:00 PM PDT 24
Peak memory 213440 kb
Host smart-9ed40d2d-cb99-40f7-a54a-c7240a322e26
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867179232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2867179232
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2358275657
Short name T294
Test name
Test status
Simulation time 2313755562 ps
CPU time 4.48 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:02 PM PDT 24
Peak memory 205340 kb
Host smart-26c4885b-3395-4c3b-95e5-110e524f0986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358275657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2358275657
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3440308823
Short name T68
Test name
Test status
Simulation time 59417848 ps
CPU time 0.76 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:14:58 PM PDT 24
Peak memory 205044 kb
Host smart-21e4d382-a837-450b-bb26-f8feff76d206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440308823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3440308823
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2088877397
Short name T255
Test name
Test status
Simulation time 3930412805 ps
CPU time 4.28 seconds
Started Jul 23 06:15:03 PM PDT 24
Finished Jul 23 06:15:08 PM PDT 24
Peak memory 213540 kb
Host smart-b9951192-0f27-4e4b-93c6-ad29131e4e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088877397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2088877397
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.481459262
Short name T249
Test name
Test status
Simulation time 4513537341 ps
CPU time 2.25 seconds
Started Jul 23 06:14:59 PM PDT 24
Finished Jul 23 06:15:02 PM PDT 24
Peak memory 213532 kb
Host smart-5adc7cb3-7313-435c-ad3b-6cd5c4d30737
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481459262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.481459262
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3189094674
Short name T289
Test name
Test status
Simulation time 1893777193 ps
CPU time 6.44 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 205292 kb
Host smart-2d2f926a-125e-4651-8573-6ed554070115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189094674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3189094674
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.384518612
Short name T17
Test name
Test status
Simulation time 5938917459 ps
CPU time 5.15 seconds
Started Jul 23 06:15:02 PM PDT 24
Finished Jul 23 06:15:08 PM PDT 24
Peak memory 213448 kb
Host smart-ecad5704-b2d2-4c3a-bf38-56d314b839c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384518612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.384518612
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.438446568
Short name T185
Test name
Test status
Simulation time 157145300 ps
CPU time 0.83 seconds
Started Jul 23 06:15:03 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 205036 kb
Host smart-a4e1b1f9-c589-45ff-8e11-13981c2dd79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438446568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.438446568
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2427894944
Short name T231
Test name
Test status
Simulation time 3790696419 ps
CPU time 2.87 seconds
Started Jul 23 06:15:02 PM PDT 24
Finished Jul 23 06:15:06 PM PDT 24
Peak memory 213632 kb
Host smart-f10bea14-aba0-4e45-a888-af91cd1bd3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427894944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2427894944
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.968263365
Short name T27
Test name
Test status
Simulation time 1260957119 ps
CPU time 1.91 seconds
Started Jul 23 06:15:01 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 205260 kb
Host smart-5beb809b-3490-4acb-8caa-49b739e7fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968263365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.968263365
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.101621795
Short name T65
Test name
Test status
Simulation time 754939004 ps
CPU time 2 seconds
Started Jul 23 06:15:00 PM PDT 24
Finished Jul 23 06:15:03 PM PDT 24
Peak memory 205180 kb
Host smart-8bfbe1bc-dfff-4067-b4be-3f5cf9ef0d4a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101621795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.101621795
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.81442306
Short name T262
Test name
Test status
Simulation time 2749460540 ps
CPU time 2.94 seconds
Started Jul 23 06:15:04 PM PDT 24
Finished Jul 23 06:15:08 PM PDT 24
Peak memory 213584 kb
Host smart-b0b3d631-429d-41ca-ba1b-d7e3e1555d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81442306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.81442306
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3538646100
Short name T66
Test name
Test status
Simulation time 42267970 ps
CPU time 0.74 seconds
Started Jul 23 06:15:00 PM PDT 24
Finished Jul 23 06:15:01 PM PDT 24
Peak memory 205052 kb
Host smart-10274f4c-333c-468b-a4e2-4680ae203398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538646100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3538646100
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1144948239
Short name T35
Test name
Test status
Simulation time 19503027592 ps
CPU time 17.96 seconds
Started Jul 23 06:15:02 PM PDT 24
Finished Jul 23 06:15:21 PM PDT 24
Peak memory 213548 kb
Host smart-d103e34c-4834-4fd6-aab1-36d2b400c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144948239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1144948239
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3801378996
Short name T28
Test name
Test status
Simulation time 4532540339 ps
CPU time 4.23 seconds
Started Jul 23 06:15:01 PM PDT 24
Finished Jul 23 06:15:06 PM PDT 24
Peak memory 213552 kb
Host smart-9a968be2-8c5f-4756-ada6-59bb39be9ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801378996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3801378996
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2067261302
Short name T13
Test name
Test status
Simulation time 3974725965 ps
CPU time 2.95 seconds
Started Jul 23 06:15:01 PM PDT 24
Finished Jul 23 06:15:05 PM PDT 24
Peak memory 213604 kb
Host smart-f700de89-9edd-4eb5-b282-192411806a81
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067261302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2067261302
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.121100344
Short name T258
Test name
Test status
Simulation time 6177181802 ps
CPU time 6.15 seconds
Started Jul 23 06:15:03 PM PDT 24
Finished Jul 23 06:15:10 PM PDT 24
Peak memory 213520 kb
Host smart-8c5af3a6-634b-4e68-a0ed-f62424516d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121100344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.121100344
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3447039315
Short name T210
Test name
Test status
Simulation time 38851960 ps
CPU time 0.71 seconds
Started Jul 23 06:15:05 PM PDT 24
Finished Jul 23 06:15:06 PM PDT 24
Peak memory 205064 kb
Host smart-4fdb3100-f3d2-49d8-b679-44d132f83dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447039315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3447039315
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1304050237
Short name T246
Test name
Test status
Simulation time 137717139992 ps
CPU time 96.75 seconds
Started Jul 23 06:15:08 PM PDT 24
Finished Jul 23 06:16:46 PM PDT 24
Peak memory 213604 kb
Host smart-1c992c4b-380b-42f1-8e7a-19d913984618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304050237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1304050237
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.730131768
Short name T140
Test name
Test status
Simulation time 1691442369 ps
CPU time 2.36 seconds
Started Jul 23 06:15:01 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 213560 kb
Host smart-34cb20a1-5d6b-4798-b501-501cd63e829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730131768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.730131768
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3518220174
Short name T270
Test name
Test status
Simulation time 2433508892 ps
CPU time 3.53 seconds
Started Jul 23 06:15:02 PM PDT 24
Finished Jul 23 06:15:06 PM PDT 24
Peak memory 213600 kb
Host smart-a7d2f02a-f88e-4516-91b7-f407157c8473
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518220174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3518220174
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2119853380
Short name T238
Test name
Test status
Simulation time 6689522561 ps
CPU time 9.16 seconds
Started Jul 23 06:15:03 PM PDT 24
Finished Jul 23 06:15:13 PM PDT 24
Peak memory 205404 kb
Host smart-8ecb13e2-7efa-48f9-8d49-ff8eddd15bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119853380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2119853380
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1507144186
Short name T251
Test name
Test status
Simulation time 96252263 ps
CPU time 0.77 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:14 PM PDT 24
Peak memory 205032 kb
Host smart-9f5396aa-8c45-4f55-9221-50da6bb314fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507144186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1507144186
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1906606892
Short name T213
Test name
Test status
Simulation time 73953134718 ps
CPU time 221.98 seconds
Started Jul 23 06:15:14 PM PDT 24
Finished Jul 23 06:18:57 PM PDT 24
Peak memory 221712 kb
Host smart-c666b5f9-96e9-428d-97f2-6d374bf22bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906606892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1906606892
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3615636459
Short name T224
Test name
Test status
Simulation time 2156472938 ps
CPU time 3.81 seconds
Started Jul 23 06:15:08 PM PDT 24
Finished Jul 23 06:15:12 PM PDT 24
Peak memory 205340 kb
Host smart-ac5db466-731b-4b44-bc4b-71c4d3e232da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615636459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3615636459
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3032813972
Short name T209
Test name
Test status
Simulation time 8464248092 ps
CPU time 22.85 seconds
Started Jul 23 06:15:06 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 213540 kb
Host smart-87272317-2c4e-45ad-87ba-7ed4bc475706
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032813972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3032813972
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2011123425
Short name T227
Test name
Test status
Simulation time 2272778903 ps
CPU time 4.44 seconds
Started Jul 23 06:15:09 PM PDT 24
Finished Jul 23 06:15:14 PM PDT 24
Peak memory 205404 kb
Host smart-22546f6c-6c54-49a9-912b-db14896357d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011123425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2011123425
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1034512009
Short name T3
Test name
Test status
Simulation time 4492903634 ps
CPU time 12.78 seconds
Started Jul 23 06:15:15 PM PDT 24
Finished Jul 23 06:15:28 PM PDT 24
Peak memory 205212 kb
Host smart-4121b9ca-e0d8-46a0-a12e-00a2138192ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034512009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1034512009
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3037910592
Short name T243
Test name
Test status
Simulation time 108213550 ps
CPU time 0.76 seconds
Started Jul 23 06:15:14 PM PDT 24
Finished Jul 23 06:15:15 PM PDT 24
Peak memory 205028 kb
Host smart-ac011fbd-cb8b-494f-a018-2ecd6e80d4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037910592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3037910592
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.898724071
Short name T288
Test name
Test status
Simulation time 40321258246 ps
CPU time 112.2 seconds
Started Jul 23 06:15:11 PM PDT 24
Finished Jul 23 06:17:04 PM PDT 24
Peak memory 213620 kb
Host smart-db5cd310-adad-44f4-bda5-417e41c40f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898724071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.898724071
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2249734203
Short name T220
Test name
Test status
Simulation time 1662011045 ps
CPU time 1.43 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:14 PM PDT 24
Peak memory 213432 kb
Host smart-ec0d682f-6474-48ed-9273-093530ad993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249734203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2249734203
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1811858817
Short name T254
Test name
Test status
Simulation time 1627673464 ps
CPU time 3.35 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:16 PM PDT 24
Peak memory 205492 kb
Host smart-15683361-657c-4dc0-ac2e-97def2cfcf88
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811858817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1811858817
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.656905416
Short name T67
Test name
Test status
Simulation time 4252245855 ps
CPU time 11.34 seconds
Started Jul 23 06:15:11 PM PDT 24
Finished Jul 23 06:15:23 PM PDT 24
Peak memory 205288 kb
Host smart-abbd0dbe-be76-4bdb-a20b-978c5ef185a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656905416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.656905416
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.17214465
Short name T137
Test name
Test status
Simulation time 7297267840 ps
CPU time 18.59 seconds
Started Jul 23 06:15:11 PM PDT 24
Finished Jul 23 06:15:30 PM PDT 24
Peak memory 205240 kb
Host smart-e6d29cbb-682a-4605-a299-11fca1c609e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17214465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.17214465
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2630514214
Short name T235
Test name
Test status
Simulation time 58693615 ps
CPU time 0.72 seconds
Started Jul 23 06:15:20 PM PDT 24
Finished Jul 23 06:15:21 PM PDT 24
Peak memory 204940 kb
Host smart-1d6730e3-7b57-4a4e-bdfa-0975422dac9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630514214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2630514214
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3661804862
Short name T128
Test name
Test status
Simulation time 10279649388 ps
CPU time 3.51 seconds
Started Jul 23 06:15:14 PM PDT 24
Finished Jul 23 06:15:18 PM PDT 24
Peak memory 213800 kb
Host smart-0ce94649-2563-4a1c-a5dc-947b1d7ce198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661804862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3661804862
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2675692088
Short name T146
Test name
Test status
Simulation time 3866786722 ps
CPU time 6.75 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:19 PM PDT 24
Peak memory 205336 kb
Host smart-7549b102-7f46-4965-9d87-b4fe44c11c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675692088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2675692088
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2765144922
Short name T285
Test name
Test status
Simulation time 6013156547 ps
CPU time 6.27 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:19 PM PDT 24
Peak memory 213560 kb
Host smart-4010d5c9-0504-4cf9-8462-cb4f3a718040
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765144922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2765144922
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2973598688
Short name T149
Test name
Test status
Simulation time 2580285309 ps
CPU time 5.78 seconds
Started Jul 23 06:15:12 PM PDT 24
Finished Jul 23 06:15:19 PM PDT 24
Peak memory 205340 kb
Host smart-bd084889-5244-4a1f-9274-94a2cdec2ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973598688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2973598688
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2672255597
Short name T179
Test name
Test status
Simulation time 2839775868 ps
CPU time 9.04 seconds
Started Jul 23 06:15:20 PM PDT 24
Finished Jul 23 06:15:30 PM PDT 24
Peak memory 205164 kb
Host smart-b7f818a5-e652-4219-b37d-b51df50e26bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672255597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2672255597
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3428551863
Short name T198
Test name
Test status
Simulation time 130714592 ps
CPU time 1.04 seconds
Started Jul 23 06:14:38 PM PDT 24
Finished Jul 23 06:14:40 PM PDT 24
Peak memory 205004 kb
Host smart-ab9b99c8-4aab-4eca-b6e8-37eb3913ec27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428551863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3428551863
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3403692191
Short name T297
Test name
Test status
Simulation time 1312902932 ps
CPU time 2.37 seconds
Started Jul 23 06:14:33 PM PDT 24
Finished Jul 23 06:14:36 PM PDT 24
Peak memory 213544 kb
Host smart-c27fd017-3786-43e2-b297-a4f4899085b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403692191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3403692191
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.931535687
Short name T143
Test name
Test status
Simulation time 8484177940 ps
CPU time 8.52 seconds
Started Jul 23 06:14:28 PM PDT 24
Finished Jul 23 06:14:37 PM PDT 24
Peak memory 213624 kb
Host smart-4cd1e57a-5161-4641-b0e2-3db4bea359cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931535687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.931535687
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1617984517
Short name T145
Test name
Test status
Simulation time 2723528969 ps
CPU time 3.32 seconds
Started Jul 23 06:14:33 PM PDT 24
Finished Jul 23 06:14:37 PM PDT 24
Peak memory 213552 kb
Host smart-b65220b8-2e71-4031-b4ef-ed05da148dfb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617984517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1617984517
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1904360890
Short name T216
Test name
Test status
Simulation time 172876762 ps
CPU time 0.91 seconds
Started Jul 23 06:14:31 PM PDT 24
Finished Jul 23 06:14:32 PM PDT 24
Peak memory 204956 kb
Host smart-a563a7ac-974d-4b3d-8ce0-931a26181cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904360890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1904360890
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2138814218
Short name T265
Test name
Test status
Simulation time 1038242788 ps
CPU time 2.85 seconds
Started Jul 23 06:14:31 PM PDT 24
Finished Jul 23 06:14:35 PM PDT 24
Peak memory 205296 kb
Host smart-94b94389-60df-4d20-b630-cdce0a7aed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138814218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2138814218
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.442261531
Short name T135
Test name
Test status
Simulation time 3049245680 ps
CPU time 5.25 seconds
Started Jul 23 06:14:32 PM PDT 24
Finished Jul 23 06:14:38 PM PDT 24
Peak memory 213900 kb
Host smart-762e7e59-b5c9-4e5e-a614-9abf31b7802c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442261531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.442261531
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2783020014
Short name T293
Test name
Test status
Simulation time 164112210 ps
CPU time 0.87 seconds
Started Jul 23 06:15:17 PM PDT 24
Finished Jul 23 06:15:18 PM PDT 24
Peak memory 204956 kb
Host smart-7f7a8d1d-4b4e-4cf1-993a-04713d9f6513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783020014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2783020014
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2722316459
Short name T23
Test name
Test status
Simulation time 5097321705 ps
CPU time 9.43 seconds
Started Jul 23 06:15:19 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 213360 kb
Host smart-487aaf18-c087-44df-a3f2-adc9622cb116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722316459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2722316459
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2788100907
Short name T195
Test name
Test status
Simulation time 96003485 ps
CPU time 0.78 seconds
Started Jul 23 06:15:18 PM PDT 24
Finished Jul 23 06:15:19 PM PDT 24
Peak memory 205056 kb
Host smart-c28c7cf8-7fe2-4f7f-8f5b-e279f5dd31d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788100907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2788100907
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.985407958
Short name T184
Test name
Test status
Simulation time 70421612 ps
CPU time 0.72 seconds
Started Jul 23 06:15:21 PM PDT 24
Finished Jul 23 06:15:23 PM PDT 24
Peak memory 204964 kb
Host smart-9f67769f-161a-48c6-b0ed-dd22393b8ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985407958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.985407958
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2731694855
Short name T16
Test name
Test status
Simulation time 5313018432 ps
CPU time 7.76 seconds
Started Jul 23 06:15:21 PM PDT 24
Finished Jul 23 06:15:30 PM PDT 24
Peak memory 205192 kb
Host smart-44c985c5-609c-497b-a3a4-bbc343cdb3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731694855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2731694855
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1295250219
Short name T264
Test name
Test status
Simulation time 203817206 ps
CPU time 0.76 seconds
Started Jul 23 06:15:20 PM PDT 24
Finished Jul 23 06:15:22 PM PDT 24
Peak memory 205024 kb
Host smart-c2933622-e91c-48ee-aa04-b44511e60759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295250219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1295250219
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1862651283
Short name T31
Test name
Test status
Simulation time 4795302703 ps
CPU time 5.91 seconds
Started Jul 23 06:15:20 PM PDT 24
Finished Jul 23 06:15:27 PM PDT 24
Peak memory 213464 kb
Host smart-aed5305f-8faa-4884-9b19-502c35cead20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862651283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1862651283
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.57445631
Short name T211
Test name
Test status
Simulation time 69352375 ps
CPU time 0.79 seconds
Started Jul 23 06:15:21 PM PDT 24
Finished Jul 23 06:15:22 PM PDT 24
Peak memory 205044 kb
Host smart-b28880e1-f2e0-46ff-ba60-fc35f2f9dfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57445631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.57445631
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2878557398
Short name T176
Test name
Test status
Simulation time 11252493587 ps
CPU time 31.88 seconds
Started Jul 23 06:15:21 PM PDT 24
Finished Jul 23 06:15:54 PM PDT 24
Peak memory 213348 kb
Host smart-2c0ce029-61d2-4070-a3cf-1f0447c499db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878557398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2878557398
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2602491073
Short name T248
Test name
Test status
Simulation time 104468931 ps
CPU time 0.8 seconds
Started Jul 23 06:15:21 PM PDT 24
Finished Jul 23 06:15:23 PM PDT 24
Peak memory 204960 kb
Host smart-fe0d1f0b-2d24-47ab-9858-65befdd69f25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602491073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2602491073
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2257225430
Short name T11
Test name
Test status
Simulation time 2874536592 ps
CPU time 8.58 seconds
Started Jul 23 06:15:20 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 213344 kb
Host smart-dd843756-8f3d-4de5-8712-195beb2c40e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257225430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2257225430
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.318608547
Short name T188
Test name
Test status
Simulation time 61923007 ps
CPU time 0.73 seconds
Started Jul 23 06:15:22 PM PDT 24
Finished Jul 23 06:15:23 PM PDT 24
Peak memory 205036 kb
Host smart-89a609df-ecd1-4cbf-b4c9-c434ff2b8db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318608547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.318608547
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2336798482
Short name T244
Test name
Test status
Simulation time 42875645 ps
CPU time 0.74 seconds
Started Jul 23 06:15:23 PM PDT 24
Finished Jul 23 06:15:24 PM PDT 24
Peak memory 205012 kb
Host smart-d7623269-18a2-40b8-80e9-0d7e209dfbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336798482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2336798482
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3728604562
Short name T234
Test name
Test status
Simulation time 93900216 ps
CPU time 0.75 seconds
Started Jul 23 06:15:25 PM PDT 24
Finished Jul 23 06:15:27 PM PDT 24
Peak memory 204984 kb
Host smart-122b3d8a-7678-44f3-b7af-3f5222137ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728604562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3728604562
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1329629201
Short name T169
Test name
Test status
Simulation time 1695343570 ps
CPU time 2.59 seconds
Started Jul 23 06:15:26 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 205152 kb
Host smart-c269d87f-d13f-4444-b687-e19fcb82109d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329629201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1329629201
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3362505773
Short name T51
Test name
Test status
Simulation time 62748725 ps
CPU time 0.74 seconds
Started Jul 23 06:15:25 PM PDT 24
Finished Jul 23 06:15:26 PM PDT 24
Peak memory 204984 kb
Host smart-5dce00ea-a729-4ee9-bd79-5dc7008d7df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362505773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3362505773
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.525386102
Short name T221
Test name
Test status
Simulation time 183802798 ps
CPU time 1.13 seconds
Started Jul 23 06:14:42 PM PDT 24
Finished Jul 23 06:14:44 PM PDT 24
Peak memory 205032 kb
Host smart-361ddb21-aa26-433f-86f8-8222c6e0f784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525386102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.525386102
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3520788621
Short name T203
Test name
Test status
Simulation time 3863110346 ps
CPU time 10.64 seconds
Started Jul 23 06:14:36 PM PDT 24
Finished Jul 23 06:14:47 PM PDT 24
Peak memory 205300 kb
Host smart-669bb348-8de2-41c8-92ae-674d150f3f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520788621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3520788621
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2604018053
Short name T69
Test name
Test status
Simulation time 13289410708 ps
CPU time 14.49 seconds
Started Jul 23 06:14:38 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 213604 kb
Host smart-a08d6084-401d-49eb-abb8-d69f79985118
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604018053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2604018053
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.637095546
Short name T250
Test name
Test status
Simulation time 84485826 ps
CPU time 0.9 seconds
Started Jul 23 06:14:38 PM PDT 24
Finished Jul 23 06:14:39 PM PDT 24
Peak memory 204948 kb
Host smart-8357731b-f0c5-44e4-8a77-a4c2483496e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637095546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.637095546
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3125654978
Short name T57
Test name
Test status
Simulation time 2405930230 ps
CPU time 3 seconds
Started Jul 23 06:14:37 PM PDT 24
Finished Jul 23 06:14:41 PM PDT 24
Peak memory 205400 kb
Host smart-57a97ba9-3a6b-4f0c-9d9c-0de4adf2ecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125654978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3125654978
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.4070652470
Short name T53
Test name
Test status
Simulation time 383230370 ps
CPU time 1.79 seconds
Started Jul 23 06:14:42 PM PDT 24
Finished Jul 23 06:14:44 PM PDT 24
Peak memory 229244 kb
Host smart-9868e3e6-e3a0-40c8-9a59-418477aae5f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070652470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4070652470
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.154583699
Short name T5
Test name
Test status
Simulation time 3571148095 ps
CPU time 3.02 seconds
Started Jul 23 06:14:37 PM PDT 24
Finished Jul 23 06:14:41 PM PDT 24
Peak memory 205180 kb
Host smart-643f2f14-f85d-4dc6-acf7-2de38a23d59f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154583699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.154583699
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3458677561
Short name T291
Test name
Test status
Simulation time 71112987 ps
CPU time 0.72 seconds
Started Jul 23 06:15:22 PM PDT 24
Finished Jul 23 06:15:23 PM PDT 24
Peak memory 205008 kb
Host smart-ee24555e-d430-4229-89ab-2cdf363a6771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458677561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3458677561
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1114985995
Short name T296
Test name
Test status
Simulation time 62987760 ps
CPU time 0.72 seconds
Started Jul 23 06:15:28 PM PDT 24
Finished Jul 23 06:15:30 PM PDT 24
Peak memory 205012 kb
Host smart-93a3db22-6f2c-4ec7-aeff-8c11e6aa9e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114985995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1114985995
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.551869410
Short name T50
Test name
Test status
Simulation time 10389720187 ps
CPU time 18.67 seconds
Started Jul 23 06:15:23 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 213436 kb
Host smart-734dd354-24b4-429c-969e-7662a0256602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551869410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.551869410
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3701146694
Short name T217
Test name
Test status
Simulation time 148721564 ps
CPU time 0.83 seconds
Started Jul 23 06:15:26 PM PDT 24
Finished Jul 23 06:15:28 PM PDT 24
Peak memory 204976 kb
Host smart-2e29e53d-f286-42e8-a2f8-04cb22b5a67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701146694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3701146694
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.900679320
Short name T141
Test name
Test status
Simulation time 9384294835 ps
CPU time 13.12 seconds
Started Jul 23 06:15:29 PM PDT 24
Finished Jul 23 06:15:43 PM PDT 24
Peak memory 213252 kb
Host smart-a5c79137-2a45-4d03-b898-60ee9070c757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900679320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.900679320
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.955143260
Short name T190
Test name
Test status
Simulation time 112593230 ps
CPU time 0.82 seconds
Started Jul 23 06:15:29 PM PDT 24
Finished Jul 23 06:15:31 PM PDT 24
Peak memory 205024 kb
Host smart-8414b983-bb21-4bc4-ae0e-917a1f87fd61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955143260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.955143260
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.231408391
Short name T263
Test name
Test status
Simulation time 174305171 ps
CPU time 0.75 seconds
Started Jul 23 06:15:30 PM PDT 24
Finished Jul 23 06:15:31 PM PDT 24
Peak memory 205024 kb
Host smart-655d1c94-d0a6-4641-9aea-0053e03ac1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231408391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.231408391
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1354853338
Short name T18
Test name
Test status
Simulation time 6641443746 ps
CPU time 7.17 seconds
Started Jul 23 06:15:28 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 213388 kb
Host smart-14c19679-6711-441d-9d44-a2fcbfa6baba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354853338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1354853338
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2733234758
Short name T205
Test name
Test status
Simulation time 39949212 ps
CPU time 0.77 seconds
Started Jul 23 06:15:27 PM PDT 24
Finished Jul 23 06:15:29 PM PDT 24
Peak memory 205044 kb
Host smart-898a40cd-ac2b-487e-87d5-353f02b1ea61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733234758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2733234758
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.172095458
Short name T170
Test name
Test status
Simulation time 4222264355 ps
CPU time 4.06 seconds
Started Jul 23 06:15:26 PM PDT 24
Finished Jul 23 06:15:31 PM PDT 24
Peak memory 205152 kb
Host smart-a6f4ce37-a993-4830-9254-528d81e2b0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172095458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.172095458
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3098573048
Short name T266
Test name
Test status
Simulation time 75473654 ps
CPU time 0.8 seconds
Started Jul 23 06:15:29 PM PDT 24
Finished Jul 23 06:15:31 PM PDT 24
Peak memory 205036 kb
Host smart-bb44e790-7679-49b4-882b-1111be934189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098573048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3098573048
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.214849458
Short name T183
Test name
Test status
Simulation time 43939787 ps
CPU time 0.78 seconds
Started Jul 23 06:15:32 PM PDT 24
Finished Jul 23 06:15:33 PM PDT 24
Peak memory 204992 kb
Host smart-2d0ce19b-bcdb-4379-a388-47a5c2d557d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214849458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.214849458
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4150471026
Short name T208
Test name
Test status
Simulation time 41589909 ps
CPU time 0.82 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:35 PM PDT 24
Peak memory 205032 kb
Host smart-74878fff-6d17-44f5-b46a-812a7e69574e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150471026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4150471026
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3654924006
Short name T138
Test name
Test status
Simulation time 8044579462 ps
CPU time 11.22 seconds
Started Jul 23 06:15:37 PM PDT 24
Finished Jul 23 06:15:49 PM PDT 24
Peak memory 213328 kb
Host smart-98d940bd-62eb-4780-8be0-255309b54de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654924006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3654924006
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3847392456
Short name T48
Test name
Test status
Simulation time 60809230 ps
CPU time 0.74 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:35 PM PDT 24
Peak memory 205036 kb
Host smart-8e3ac4a2-370c-46e6-94e3-d76a38e9ca18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847392456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3847392456
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1304552501
Short name T133
Test name
Test status
Simulation time 10259096722 ps
CPU time 14.88 seconds
Started Jul 23 06:15:50 PM PDT 24
Finished Jul 23 06:16:07 PM PDT 24
Peak memory 219316 kb
Host smart-37c52466-8029-4377-9ebb-6383bad490ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304552501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1304552501
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2514566246
Short name T189
Test name
Test status
Simulation time 78068978 ps
CPU time 0.8 seconds
Started Jul 23 06:14:46 PM PDT 24
Finished Jul 23 06:14:48 PM PDT 24
Peak memory 205012 kb
Host smart-3f5f6424-e21c-433d-a391-6b078ba9ca34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514566246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2514566246
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2246586004
Short name T286
Test name
Test status
Simulation time 1023287215 ps
CPU time 2.18 seconds
Started Jul 23 06:14:39 PM PDT 24
Finished Jul 23 06:14:42 PM PDT 24
Peak memory 205320 kb
Host smart-e24885d4-054a-4272-9916-9d19902e5aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246586004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2246586004
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2045940190
Short name T271
Test name
Test status
Simulation time 5981134503 ps
CPU time 3.03 seconds
Started Jul 23 06:14:42 PM PDT 24
Finished Jul 23 06:14:46 PM PDT 24
Peak memory 205404 kb
Host smart-48940ac9-0cb5-4d84-83b2-85f7c057ecb6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045940190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2045940190
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2585324377
Short name T292
Test name
Test status
Simulation time 492619528 ps
CPU time 2.16 seconds
Started Jul 23 06:14:42 PM PDT 24
Finished Jul 23 06:14:44 PM PDT 24
Peak memory 204932 kb
Host smart-ab932044-24c8-4eed-9fc6-8d931c3eea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585324377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2585324377
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3129047167
Short name T225
Test name
Test status
Simulation time 4452672423 ps
CPU time 12.2 seconds
Started Jul 23 06:14:41 PM PDT 24
Finished Jul 23 06:14:54 PM PDT 24
Peak memory 205436 kb
Host smart-d9e85cf1-6e9a-4a7e-8393-4a3f2f1f7925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129047167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3129047167
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1599130057
Short name T63
Test name
Test status
Simulation time 735768953 ps
CPU time 1.1 seconds
Started Jul 23 06:14:47 PM PDT 24
Finished Jul 23 06:14:49 PM PDT 24
Peak memory 228880 kb
Host smart-a76a69b4-b8ce-401c-9d82-0a13aee941cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599130057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1599130057
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1239120166
Short name T171
Test name
Test status
Simulation time 1722628281 ps
CPU time 5.76 seconds
Started Jul 23 06:14:46 PM PDT 24
Finished Jul 23 06:14:52 PM PDT 24
Peak memory 205092 kb
Host smart-41ddf7b1-54de-4fe8-b757-151b097f5455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239120166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1239120166
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.325261221
Short name T181
Test name
Test status
Simulation time 154337073 ps
CPU time 0.75 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:34 PM PDT 24
Peak memory 205064 kb
Host smart-d9e0f7e1-53f4-4a21-93bc-1eb90909491f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325261221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.325261221
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2097543252
Short name T174
Test name
Test status
Simulation time 3027986440 ps
CPU time 5.64 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:40 PM PDT 24
Peak memory 205240 kb
Host smart-a8107243-68c1-4b90-8304-f99739726521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097543252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2097543252
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1752317115
Short name T245
Test name
Test status
Simulation time 116354504 ps
CPU time 0.91 seconds
Started Jul 23 06:15:35 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 205024 kb
Host smart-5da04420-93f8-40ea-ad02-d1d6d385d5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752317115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1752317115
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3477525906
Short name T252
Test name
Test status
Simulation time 132117676 ps
CPU time 0.86 seconds
Started Jul 23 06:15:32 PM PDT 24
Finished Jul 23 06:15:33 PM PDT 24
Peak memory 205020 kb
Host smart-607f7300-6ca1-45b9-9487-f68ba3f88860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477525906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3477525906
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3561051918
Short name T132
Test name
Test status
Simulation time 2673923556 ps
CPU time 3.21 seconds
Started Jul 23 06:15:33 PM PDT 24
Finished Jul 23 06:15:37 PM PDT 24
Peak memory 205252 kb
Host smart-31cae7e5-ab75-4076-9380-a59f63929d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561051918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3561051918
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2649219595
Short name T126
Test name
Test status
Simulation time 87010104 ps
CPU time 0.76 seconds
Started Jul 23 06:15:35 PM PDT 24
Finished Jul 23 06:15:36 PM PDT 24
Peak memory 205060 kb
Host smart-aa69520c-3647-4a0c-81ca-272987c3e2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649219595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2649219595
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1185679155
Short name T206
Test name
Test status
Simulation time 80955853 ps
CPU time 0.7 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:37 PM PDT 24
Peak memory 205008 kb
Host smart-9be96fba-87d0-41fe-993a-31648be84461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185679155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1185679155
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3184867225
Short name T232
Test name
Test status
Simulation time 108983583 ps
CPU time 0.72 seconds
Started Jul 23 06:15:38 PM PDT 24
Finished Jul 23 06:15:40 PM PDT 24
Peak memory 205060 kb
Host smart-5228734b-43fb-4e73-857e-c8f4fee3fd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184867225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3184867225
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.327256409
Short name T172
Test name
Test status
Simulation time 2229078106 ps
CPU time 2.64 seconds
Started Jul 23 06:15:36 PM PDT 24
Finished Jul 23 06:15:40 PM PDT 24
Peak memory 205376 kb
Host smart-ee53bbab-4709-4081-ab93-a463ab217d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327256409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.327256409
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.183442720
Short name T278
Test name
Test status
Simulation time 70304262 ps
CPU time 0.85 seconds
Started Jul 23 06:15:41 PM PDT 24
Finished Jul 23 06:15:43 PM PDT 24
Peak memory 205024 kb
Host smart-eb23ca8a-327d-40f8-970c-4f966d5a35bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183442720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.183442720
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2273494169
Short name T8
Test name
Test status
Simulation time 6565647494 ps
CPU time 3.62 seconds
Started Jul 23 06:15:38 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 205188 kb
Host smart-7930736e-c5af-4ceb-8328-4452cf361bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273494169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2273494169
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1892979839
Short name T214
Test name
Test status
Simulation time 204016742 ps
CPU time 0.75 seconds
Started Jul 23 06:15:39 PM PDT 24
Finished Jul 23 06:15:40 PM PDT 24
Peak memory 205064 kb
Host smart-b8340625-a0c6-46db-b281-fb639fa7f3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892979839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1892979839
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1286333456
Short name T247
Test name
Test status
Simulation time 134417921 ps
CPU time 0.98 seconds
Started Jul 23 06:15:40 PM PDT 24
Finished Jul 23 06:15:42 PM PDT 24
Peak memory 204988 kb
Host smart-aba9c510-3047-4524-99c3-c346915662b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286333456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1286333456
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1823757276
Short name T144
Test name
Test status
Simulation time 3627669333 ps
CPU time 5.32 seconds
Started Jul 23 06:15:35 PM PDT 24
Finished Jul 23 06:15:41 PM PDT 24
Peak memory 205148 kb
Host smart-0026ca43-8523-4634-a7ff-c63268fb7707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823757276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1823757276
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2704423319
Short name T279
Test name
Test status
Simulation time 55791689 ps
CPU time 0.82 seconds
Started Jul 23 06:15:37 PM PDT 24
Finished Jul 23 06:15:39 PM PDT 24
Peak memory 204992 kb
Host smart-a6561e19-87bc-488e-8b4b-f76664f9058d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704423319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2704423319
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.751723587
Short name T204
Test name
Test status
Simulation time 9482622087 ps
CPU time 7.27 seconds
Started Jul 23 06:15:38 PM PDT 24
Finished Jul 23 06:15:46 PM PDT 24
Peak memory 213308 kb
Host smart-65756b9f-4308-4bfa-8bac-c3171d9e8599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751723587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.751723587
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1247368395
Short name T269
Test name
Test status
Simulation time 147018585 ps
CPU time 0.96 seconds
Started Jul 23 06:14:52 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 204988 kb
Host smart-19648b29-db89-4811-ae2d-a6e49168f8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247368395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1247368395
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2196176629
Short name T261
Test name
Test status
Simulation time 9926084330 ps
CPU time 5.02 seconds
Started Jul 23 06:14:53 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 213752 kb
Host smart-e124961e-45b3-424b-b36e-195e9b33b5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196176629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2196176629
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.280044555
Short name T242
Test name
Test status
Simulation time 4188427215 ps
CPU time 6.43 seconds
Started Jul 23 06:14:45 PM PDT 24
Finished Jul 23 06:14:52 PM PDT 24
Peak memory 205340 kb
Host smart-f08fd011-5c69-446d-983b-a61ec1d91572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280044555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.280044555
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2510995324
Short name T215
Test name
Test status
Simulation time 3891787405 ps
CPU time 9.96 seconds
Started Jul 23 06:14:47 PM PDT 24
Finished Jul 23 06:14:58 PM PDT 24
Peak memory 205332 kb
Host smart-efa9c0c3-5d63-4f41-a957-defab283fdc5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510995324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2510995324
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3164600256
Short name T49
Test name
Test status
Simulation time 2710326540 ps
CPU time 5.81 seconds
Started Jul 23 06:14:46 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 205328 kb
Host smart-d8b69c77-b7d9-4dc3-9c92-6a73ff0a21da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164600256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3164600256
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.737763360
Short name T10
Test name
Test status
Simulation time 6748959651 ps
CPU time 6.18 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:03 PM PDT 24
Peak memory 213368 kb
Host smart-8d305151-19b3-4370-b10a-f8853f1bd4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737763360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.737763360
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2298382370
Short name T191
Test name
Test status
Simulation time 35731997 ps
CPU time 0.75 seconds
Started Jul 23 06:14:51 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 205024 kb
Host smart-6e2f1cf9-1614-49ec-9b71-e87e32e23ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298382370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2298382370
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.14961926
Short name T290
Test name
Test status
Simulation time 17042312517 ps
CPU time 13.23 seconds
Started Jul 23 06:14:48 PM PDT 24
Finished Jul 23 06:15:02 PM PDT 24
Peak memory 216772 kb
Host smart-0d16d125-aaf7-4fa1-a8e1-dae1eed36ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14961926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.14961926
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2930576340
Short name T142
Test name
Test status
Simulation time 1150816009 ps
CPU time 2.58 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:02 PM PDT 24
Peak memory 214380 kb
Host smart-2e760568-d76c-4490-8451-c3b1b0a3485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930576340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2930576340
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1598098636
Short name T58
Test name
Test status
Simulation time 6846171242 ps
CPU time 20.06 seconds
Started Jul 23 06:14:51 PM PDT 24
Finished Jul 23 06:15:12 PM PDT 24
Peak memory 205404 kb
Host smart-9b203511-ae54-49c8-8727-b48c5121febb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598098636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1598098636
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3378153171
Short name T260
Test name
Test status
Simulation time 1542672182 ps
CPU time 1.7 seconds
Started Jul 23 06:14:51 PM PDT 24
Finished Jul 23 06:14:53 PM PDT 24
Peak memory 205236 kb
Host smart-7dba0d40-b57c-4d91-bccf-471066e824ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378153171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3378153171
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3951487494
Short name T148
Test name
Test status
Simulation time 9591513969 ps
CPU time 13.09 seconds
Started Jul 23 06:14:52 PM PDT 24
Finished Jul 23 06:15:06 PM PDT 24
Peak memory 213376 kb
Host smart-9050e29d-cab2-4960-a6a5-d62759120393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951487494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3951487494
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1530450793
Short name T276
Test name
Test status
Simulation time 148550877 ps
CPU time 1.01 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 204912 kb
Host smart-4a9e0e8f-747f-4e0a-9af6-8d26aaea49ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530450793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1530450793
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3202007382
Short name T202
Test name
Test status
Simulation time 13622036656 ps
CPU time 8.04 seconds
Started Jul 23 06:14:49 PM PDT 24
Finished Jul 23 06:14:58 PM PDT 24
Peak memory 213644 kb
Host smart-8c972286-f8fa-47fe-ac61-6b3b6f17e46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202007382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3202007382
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2611597794
Short name T253
Test name
Test status
Simulation time 3031947953 ps
CPU time 7.97 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:05 PM PDT 24
Peak memory 213608 kb
Host smart-373f5d74-0fce-4bf7-988b-39c28438b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611597794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2611597794
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3067695814
Short name T272
Test name
Test status
Simulation time 3039974338 ps
CPU time 9.5 seconds
Started Jul 23 06:14:59 PM PDT 24
Finished Jul 23 06:15:10 PM PDT 24
Peak memory 205220 kb
Host smart-0936ef6d-4453-4583-a9ea-2d6b3e153a02
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067695814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3067695814
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.4031441439
Short name T7
Test name
Test status
Simulation time 2196102289 ps
CPU time 2.68 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 205520 kb
Host smart-c86479eb-fabb-4f89-99ae-10de2f62d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031441439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4031441439
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2519341873
Short name T175
Test name
Test status
Simulation time 9209194092 ps
CPU time 7.6 seconds
Started Jul 23 06:14:55 PM PDT 24
Finished Jul 23 06:15:03 PM PDT 24
Peak memory 213444 kb
Host smart-f6f1232a-05ba-4fda-b044-547fe9a73db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519341873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2519341873
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2414660515
Short name T194
Test name
Test status
Simulation time 82012211 ps
CPU time 0.75 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 204912 kb
Host smart-3b4777ef-ae0f-4bd4-95e4-bc77dbba45d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414660515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2414660515
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.612832851
Short name T241
Test name
Test status
Simulation time 9458364819 ps
CPU time 26.36 seconds
Started Jul 23 06:14:58 PM PDT 24
Finished Jul 23 06:15:26 PM PDT 24
Peak memory 213376 kb
Host smart-84d50807-ef91-40ea-a4b3-f4b1df3b1cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612832851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.612832851
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1131271032
Short name T199
Test name
Test status
Simulation time 2676747682 ps
CPU time 4.76 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 213436 kb
Host smart-7978e940-eb5d-40c5-aace-8f7025290132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131271032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1131271032
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1705392817
Short name T222
Test name
Test status
Simulation time 10700210887 ps
CPU time 28.94 seconds
Started Jul 23 06:14:58 PM PDT 24
Finished Jul 23 06:15:28 PM PDT 24
Peak memory 213416 kb
Host smart-d1641554-4095-44cc-93e9-568466abcb4a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705392817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1705392817
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2312405671
Short name T295
Test name
Test status
Simulation time 5510731478 ps
CPU time 6.68 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 205348 kb
Host smart-4861eb66-b5d3-481e-9cf3-fcb84e8eead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312405671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2312405671
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.1278190002
Short name T29
Test name
Test status
Simulation time 2817384005 ps
CPU time 5.31 seconds
Started Jul 23 06:14:59 PM PDT 24
Finished Jul 23 06:15:05 PM PDT 24
Peak memory 205000 kb
Host smart-e37ffec8-5f3c-4717-a2d6-7295888b61fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278190002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1278190002
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2667149382
Short name T230
Test name
Test status
Simulation time 79011010 ps
CPU time 0.72 seconds
Started Jul 23 06:14:57 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 204992 kb
Host smart-febee715-6c21-4de1-bd46-0d8088f459be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667149382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2667149382
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1473102856
Short name T192
Test name
Test status
Simulation time 7359865139 ps
CPU time 21.22 seconds
Started Jul 23 06:14:53 PM PDT 24
Finished Jul 23 06:15:15 PM PDT 24
Peak memory 213636 kb
Host smart-eb2b652e-c633-459b-bfed-f2a1743e26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473102856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1473102856
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.343793684
Short name T218
Test name
Test status
Simulation time 3058909853 ps
CPU time 7.05 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:15:04 PM PDT 24
Peak memory 213628 kb
Host smart-6f7eeeff-4e6e-4a12-b07d-e41c8189dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343793684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.343793684
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2227699838
Short name T226
Test name
Test status
Simulation time 2208409825 ps
CPU time 7.03 seconds
Started Jul 23 06:14:52 PM PDT 24
Finished Jul 23 06:15:00 PM PDT 24
Peak memory 205348 kb
Host smart-0032ecd8-5f55-4f99-bf83-9997aa5d032d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227699838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2227699838
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.4100736277
Short name T275
Test name
Test status
Simulation time 1647785672 ps
CPU time 1.85 seconds
Started Jul 23 06:14:56 PM PDT 24
Finished Jul 23 06:14:59 PM PDT 24
Peak memory 205220 kb
Host smart-9f1cc6e1-37dd-4bca-bce7-5ed8e140a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100736277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.4100736277
Directory /workspace/9.rv_dm_sba_tl_access/latest
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