Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.18 95.77 81.52 89.91 75.00 86.50 98.42 55.12


Total tests in report: 444
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
56.69 56.69 87.12 87.12 56.83 56.83 32.24 32.24 53.75 53.75 68.00 68.00 93.48 93.48 5.43 5.43 /workspace/coverage/default/41.rv_dm_stress_all.238559152
64.51 7.82 89.84 2.72 64.41 7.59 62.18 29.94 61.25 7.50 72.67 4.67 94.95 1.47 6.29 0.86 /workspace/coverage/default/1.rv_dm_sba_tl_access.2912944501
70.94 6.43 89.99 0.15 68.83 4.41 65.75 3.57 68.75 7.50 74.00 1.33 96.00 1.05 33.29 27.00 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4057905937
74.23 3.28 91.15 1.16 72.14 3.31 78.84 13.08 71.25 2.50 76.67 2.67 96.00 0.00 33.54 0.25 /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3366372720
75.76 1.54 92.15 1.01 73.66 1.52 81.79 2.95 73.75 2.50 78.83 2.17 96.00 0.00 34.16 0.62 /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.896092407
77.15 1.39 92.15 0.00 73.66 0.00 81.79 0.00 73.75 0.00 78.83 0.00 96.00 0.00 43.90 9.74 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.748637159
78.09 0.93 92.25 0.10 75.17 1.52 82.12 0.33 73.75 0.00 79.33 0.50 96.00 0.00 47.97 4.07 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1951140520
78.89 0.81 92.71 0.45 76.55 1.38 84.82 2.71 73.75 0.00 79.83 0.50 96.00 0.00 48.58 0.62 /workspace/coverage/default/0.rv_dm_alert_test.2659381702
79.49 0.60 93.31 0.60 77.38 0.83 84.82 0.00 75.00 1.25 81.33 1.50 96.00 0.00 48.58 0.00 /workspace/coverage/default/1.rv_dm_cmderr_exception.4021203207
80.02 0.53 93.31 0.00 77.38 0.00 88.56 3.73 75.00 0.00 81.33 0.00 96.00 0.00 48.58 0.00 /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1868457830
80.50 0.48 93.91 0.60 78.07 0.69 88.64 0.08 75.00 0.00 82.67 1.33 96.00 0.00 49.20 0.62 /workspace/coverage/default/36.rv_dm_stress_all.209060261
80.75 0.26 93.91 0.00 78.48 0.41 89.66 1.03 75.00 0.00 82.67 0.00 96.11 0.11 49.45 0.25 /workspace/coverage/default/2.rv_dm_sec_cm.920464666
80.98 0.23 93.91 0.00 78.48 0.00 89.66 0.00 75.00 0.00 82.67 0.00 96.11 0.00 51.05 1.60 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2108781291
81.18 0.19 94.22 0.30 79.03 0.55 89.66 0.00 75.00 0.00 83.17 0.50 96.11 0.00 51.05 0.00 /workspace/coverage/default/0.rv_dm_debug_disabled.3036174875
81.37 0.19 94.52 0.30 79.45 0.41 89.66 0.00 75.00 0.00 83.67 0.50 96.11 0.00 51.17 0.12 /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2324942801
81.53 0.16 94.82 0.30 79.72 0.28 89.75 0.08 75.00 0.00 84.00 0.33 96.11 0.00 51.29 0.12 /workspace/coverage/default/27.rv_dm_stress_all.3920664651
81.67 0.14 94.87 0.05 80.14 0.41 89.75 0.00 75.00 0.00 84.17 0.17 96.11 0.00 51.66 0.37 /workspace/coverage/default/26.rv_dm_stress_all.1914472913
81.81 0.14 94.87 0.00 80.14 0.00 89.75 0.00 75.00 0.00 84.17 0.00 96.32 0.21 52.40 0.74 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1022824876
81.94 0.14 94.87 0.00 80.14 0.00 89.75 0.00 75.00 0.00 84.17 0.00 97.27 0.95 52.40 0.00 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2212514256
82.08 0.13 94.97 0.10 80.28 0.14 89.83 0.08 75.00 0.00 84.67 0.50 97.27 0.00 52.53 0.12 /workspace/coverage/default/0.rv_dm_rom_read_access.2993495391
82.20 0.12 95.17 0.20 80.41 0.14 89.91 0.08 75.00 0.00 84.83 0.17 97.27 0.00 52.77 0.25 /workspace/coverage/default/43.rv_dm_stress_all.3814332912
82.31 0.11 95.47 0.30 80.41 0.00 89.91 0.00 75.00 0.00 85.33 0.50 97.27 0.00 52.77 0.00 /workspace/coverage/default/0.rv_dm_abstractcmd_status.1723766981
82.40 0.09 95.47 0.00 80.41 0.00 89.91 0.00 75.00 0.00 85.33 0.00 97.90 0.63 52.77 0.00 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1294127653
82.49 0.09 95.52 0.05 80.83 0.41 89.91 0.00 75.00 0.00 85.50 0.17 97.90 0.00 52.77 0.00 /workspace/coverage/default/0.rv_dm_dmi_failed_op.807581943
82.58 0.09 95.52 0.00 80.83 0.00 89.91 0.00 75.00 0.00 85.50 0.00 97.90 0.00 53.39 0.62 /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1953200218
82.65 0.07 95.57 0.05 80.97 0.14 89.91 0.00 75.00 0.00 85.67 0.17 97.90 0.00 53.51 0.12 /workspace/coverage/default/12.rv_dm_stress_all.3158315157
82.71 0.06 95.57 0.00 81.24 0.28 89.91 0.00 75.00 0.00 85.83 0.17 97.90 0.00 53.51 0.00 /workspace/coverage/default/1.rv_dm_progbuf_busy.1491090278
82.77 0.06 95.67 0.10 81.24 0.00 89.91 0.00 75.00 0.00 86.17 0.33 97.90 0.00 53.51 0.00 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1947677623
82.82 0.05 95.72 0.05 81.38 0.14 89.91 0.00 75.00 0.00 86.33 0.17 97.90 0.00 53.51 0.00 /workspace/coverage/default/0.rv_dm_hartsel_warl.923315410
82.87 0.05 95.72 0.00 81.38 0.00 89.91 0.00 75.00 0.00 86.33 0.00 98.21 0.32 53.51 0.00 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2215230724
82.90 0.04 95.72 0.00 81.52 0.14 89.91 0.00 75.00 0.00 86.33 0.00 98.21 0.00 53.64 0.12 /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.811661870
82.94 0.04 95.72 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.33 0.00 98.21 0.00 53.88 0.25 /workspace/coverage/default/1.rv_dm_stress_all.508737586
82.98 0.04 95.72 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.33 0.00 98.21 0.00 54.13 0.25 /workspace/coverage/default/10.rv_dm_stress_all.3454335528
83.01 0.03 95.77 0.05 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.17 98.21 0.00 54.13 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.730866439
83.04 0.03 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.21 54.13 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1026653477
83.05 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.25 0.12 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2002371185
83.07 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.38 0.12 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1485492789
83.09 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.50 0.12 /workspace/coverage/default/0.rv_dm_progbuf_busy.1500152471
83.11 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.62 0.12 /workspace/coverage/default/0.rv_dm_stress_all.1848388102
83.12 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.75 0.12 /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2898827063
83.14 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.87 0.12 /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4002176678
83.16 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 54.99 0.12 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3098528993
83.18 0.02 95.77 0.00 81.52 0.00 89.91 0.00 75.00 0.00 86.50 0.00 98.42 0.00 55.12 0.12 /workspace/coverage/default/21.rv_dm_stress_all.2988971271

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1917656766
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.753842147
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1547858128
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2603883736
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3912307943
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3194379908
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1538966507
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3162687987
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1206259403
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1897529744
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2523008833
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4210947042
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.986087007
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.560869559
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2947041299
/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3687766202
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3298219360
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2715048387
/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.459579756
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3775727589
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2111911045
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3327465974
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3272500145
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3592361007
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1990596159
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2026022453
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1100752515
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2327039513
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3256914906
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1794428443
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.655497663
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.362901243
/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2831285587
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1115307654
/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1641199843
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3361953928
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3485006470
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3751375148
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.254449578
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3609114085
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.899532480
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4156442223
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4039052384
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.636044782
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2667523203
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3299561077
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1178032972
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.827178453
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2481628535
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.339311634
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.143618565
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1573272961
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2712783063
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3100236788
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1823345415
/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1062065447
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4119873222
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4220499772
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3398680615
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1448336413
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2781525854
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1622350711
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1895188640
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.421349708
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2164171446
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1282075147
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2579458107
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1145459415
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2410674121
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2274522121
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3231715410
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1972560774
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.242251140
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2044446826
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.380570004
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.861050773
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3248913098
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1639692588
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.607349148
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2035548064
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1982095485
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2080774191
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2823617222
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3164959156
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3644296698
/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2408106008
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2767860931
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2290994508
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.713057392
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.601303632
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2829705305
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2835862316
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2573154621
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.403058789
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2127114616
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3557634675
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.744948025
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.261089064
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2571653002
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.405215025
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.990151980
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3940241096
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.389232803
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3220735918
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.201052213
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.756221643
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2833845698
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.787759785
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.549955245
/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3621179518
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4154484098
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.841631266
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1791636561
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3181347002
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.530842445
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1774679604
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4018296877
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1998483465
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.252446161
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3630876425
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3143646807
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3300410716
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.774017137
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1140821878
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.516382101
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.264517674
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2472350325
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2792335276
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2732198318
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.344571443
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3323030716
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4196761262
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3191334981
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3862609517
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3849982596
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2987055859
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4033389502
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Total test records in report: 444
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.rv_dm_alert_test.2659381702 Jul 23 06:14:14 PM PDT 24 Jul 23 06:14:17 PM PDT 24 67221238 ps
T2 /workspace/coverage/default/1.rv_dm_sba_tl_access.2912944501 Jul 23 06:14:13 PM PDT 24 Jul 23 06:14:21 PM PDT 24 6656278245 ps
T3 /workspace/coverage/default/17.rv_dm_stress_all.1034512009 Jul 23 06:15:15 PM PDT 24 Jul 23 06:15:28 PM PDT 24 4492903634 ps
T7 /workspace/coverage/default/7.rv_dm_sba_tl_access.4031441439 Jul 23 06:14:56 PM PDT 24 Jul 23 06:14:59 PM PDT 24 2196102289 ps
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T238 /workspace/coverage/default/16.rv_dm_sba_tl_access.2119853380 Jul 23 06:15:03 PM PDT 24 Jul 23 06:15:13 PM PDT 24 6689522561 ps
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T265 /workspace/coverage/default/2.rv_dm_sba_tl_access.2138814218 Jul 23 06:14:31 PM PDT 24 Jul 23 06:14:35 PM PDT 24 1038242788 ps
T130 /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3098528993 Jul 23 06:14:58 PM PDT 24 Jul 23 06:15:03 PM PDT 24 4259222667 ps
T170 /workspace/coverage/default/35.rv_dm_stress_all.172095458 Jul 23 06:15:26 PM PDT 24 Jul 23 06:15:31 PM PDT 24 4222264355 ps
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T182 /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2468805975 Jul 23 06:14:14 PM PDT 24 Jul 23 06:14:22 PM PDT 24 11610853460 ps
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T191 /workspace/coverage/default/6.rv_dm_alert_test.2298382370 Jul 23 06:14:51 PM PDT 24 Jul 23 06:14:53 PM PDT 24 35731997 ps
T192 /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1473102856 Jul 23 06:14:53 PM PDT 24 Jul 23 06:15:15 PM PDT 24 7359865139 ps
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T216 /workspace/coverage/default/2.rv_dm_hart_unavail.1904360890 Jul 23 06:14:31 PM PDT 24 Jul 23 06:14:32 PM PDT 24 172876762 ps
T269 /workspace/coverage/default/5.rv_dm_alert_test.1247368395 Jul 23 06:14:52 PM PDT 24 Jul 23 06:14:53 PM PDT 24 147018585 ps
T270 /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3518220174 Jul 23 06:15:02 PM PDT 24 Jul 23 06:15:06 PM PDT 24 2433508892 ps
T231 /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2427894944 Jul 23 06:15:02 PM PDT 24 Jul 23 06:15:06 PM PDT 24 3790696419 ps
T201 /workspace/coverage/default/0.rv_dm_sba_tl_access.1587977643 Jul 23 06:14:13 PM PDT 24 Jul 23 06:14:17 PM PDT 24 1126532272 ps
T220 /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2249734203 Jul 23 06:15:12 PM PDT 24 Jul 23 06:15:14 PM PDT 24 1662011045 ps
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T180 /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1139786967 Jul 23 06:14:21 PM PDT 24 Jul 23 06:14:23 PM PDT 24 759535232 ps
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T276 /workspace/coverage/default/7.rv_dm_alert_test.1530450793 Jul 23 06:14:57 PM PDT 24 Jul 23 06:14:59 PM PDT 24 148550877 ps
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T175 /workspace/coverage/default/7.rv_dm_stress_all.2519341873 Jul 23 06:14:55 PM PDT 24 Jul 23 06:15:03 PM PDT 24 9209194092 ps
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T280 /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1455111104 Jul 23 06:14:23 PM PDT 24 Jul 23 06:14:24 PM PDT 24 212922106 ps
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T281 /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.462660289 Jul 23 06:14:12 PM PDT 24 Jul 23 06:14:14 PM PDT 24 1226371578 ps
T133 /workspace/coverage/default/39.rv_dm_stress_all.1304552501 Jul 23 06:15:50 PM PDT 24 Jul 23 06:16:07 PM PDT 24 10259096722 ps
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T284 /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1868457830 Jul 23 06:14:41 PM PDT 24 Jul 23 06:16:04 PM PDT 24 27625588703 ps
T285 /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2765144922 Jul 23 06:15:12 PM PDT 24 Jul 23 06:15:19 PM PDT 24 6013156547 ps
T242 /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.280044555 Jul 23 06:14:45 PM PDT 24 Jul 23 06:14:52 PM PDT 24 4188427215 ps
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T199 /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1131271032 Jul 23 06:14:57 PM PDT 24 Jul 23 06:15:04 PM PDT 24 2676747682 ps
T289 /workspace/coverage/default/13.rv_dm_sba_tl_access.3189094674 Jul 23 06:14:57 PM PDT 24 Jul 23 06:15:04 PM PDT 24 1893777193 ps
T32 /workspace/coverage/default/0.rv_dm_hartsel_warl.923315410 Jul 23 06:14:14 PM PDT 24 Jul 23 06:14:17 PM PDT 24 318278934 ps
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T230 /workspace/coverage/default/9.rv_dm_alert_test.2667149382 Jul 23 06:14:57 PM PDT 24 Jul 23 06:14:59 PM PDT 24 79011010 ps
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T294 /workspace/coverage/default/12.rv_dm_sba_tl_access.2358275657 Jul 23 06:14:56 PM PDT 24 Jul 23 06:15:02 PM PDT 24 2313755562 ps
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T64 /workspace/coverage/default/1.rv_dm_sec_cm.2792982866 Jul 23 06:14:31 PM PDT 24 Jul 23 06:14:35 PM PDT 24 1711267636 ps
T295 /workspace/coverage/default/8.rv_dm_sba_tl_access.2312405671 Jul 23 06:14:56 PM PDT 24 Jul 23 06:15:04 PM PDT 24 5510731478 ps
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T190 /workspace/coverage/default/33.rv_dm_alert_test.955143260 Jul 23 06:15:29 PM PDT 24 Jul 23 06:15:31 PM PDT 24 112593230 ps
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T297 /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3403692191 Jul 23 06:14:33 PM PDT 24 Jul 23 06:14:36 PM PDT 24 1312902932 ps
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T303 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.756221643 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:28 PM PDT 24 14825929185 ps
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T305 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1573272961 Jul 23 06:10:22 PM PDT 24 Jul 23 06:10:30 PM PDT 24 2093304863 ps
T306 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.744948025 Jul 23 06:10:06 PM PDT 24 Jul 23 06:10:28 PM PDT 24 22192820904 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3991708571 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:53 PM PDT 24 6291247561 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.252446161 Jul 23 06:09:43 PM PDT 24 Jul 23 06:09:48 PM PDT 24 2706667729 ps
T88 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.636044782 Jul 23 06:10:19 PM PDT 24 Jul 23 06:10:27 PM PDT 24 188589783 ps
T308 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1834893356 Jul 23 06:10:02 PM PDT 24 Jul 23 06:10:32 PM PDT 24 16350162091 ps
T309 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2712783063 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:23 PM PDT 24 608263071 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.939608222 Jul 23 06:10:17 PM PDT 24 Jul 23 06:10:41 PM PDT 24 19506816087 ps
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