Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	225691	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	574329	1		T2	2		T3	1		T6	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	510919	1		T6	6		T8	1		T4	3
values[0x0]	138769	1		T2	1		T3	3		T6	4
values[0x1]	150332	1		T2	1		T3	2		T6	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167701	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	632319	1		T2	2		T3	2		T6	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3278	1		T61	23		T62	21		T64	6
valid_sources[0x01]	2905	1		T58	1		T21	1		T61	11
valid_sources[0x02]	2937	1		T24	4		T163	1		T61	18
valid_sources[0x03]	2859	1		T164	1		T61	16		T62	24
valid_sources[0x04]	2483	1		T142	4		T165	4		T61	13
valid_sources[0x05]	2549	1		T61	14		T62	15		T64	7
valid_sources[0x06]	2765	1		T25	1		T61	16		T62	28
valid_sources[0x07]	2787	1		T24	1		T139	2		T61	27
valid_sources[0x08]	3148	1		T14	6		T61	23		T62	24
valid_sources[0x09]	2869	1		T61	23		T62	26		T64	3
valid_sources[0x0a]	3165	1		T27	1		T61	24		T62	26
valid_sources[0x0b]	2952	1		T17	3		T61	23		T62	26
valid_sources[0x0c]	3269	1		T22	2		T61	39		T62	20
valid_sources[0x0d]	3267	1		T60	3		T61	31		T62	23
valid_sources[0x0e]	3600	1		T166	1		T23	1		T61	28
valid_sources[0x0f]	3524	1		T58	1		T61	26		T62	27
valid_sources[0x10]	2896	1		T61	35		T62	18		T64	3
valid_sources[0x11]	3522	1		T24	1		T61	23		T62	26
valid_sources[0x12]	3165	1		T167	1		T61	11		T62	20
valid_sources[0x13]	2857	1		T18	5		T23	1		T61	34
valid_sources[0x14]	3224	1		T61	8		T62	18		T64	3
valid_sources[0x15]	3447	1		T25	1		T61	16		T62	23
valid_sources[0x16]	2808	1		T58	1		T167	1		T164	1
valid_sources[0x17]	3324	1		T166	1		T167	1		T139	1
valid_sources[0x18]	3242	1		T21	1		T61	13		T62	22
valid_sources[0x19]	2372	1		T32	3		T167	1		T61	25
valid_sources[0x1a]	2603	1		T61	19		T62	23		T64	4
valid_sources[0x1b]	2879	1		T61	17		T62	19		T64	2
valid_sources[0x1c]	3274	1		T38	3		T61	30		T62	23
valid_sources[0x1d]	3297	1		T14	1		T61	17		T62	16
valid_sources[0x1e]	2475	1		T24	3		T61	22		T62	31
valid_sources[0x1f]	3269	1		T15	1		T61	16		T62	25
valid_sources[0x20]	3018	1		T136	1		T61	32		T62	25
valid_sources[0x21]	2803	1		T25	1		T61	9		T62	23
valid_sources[0x22]	3351	1		T136	1		T61	14		T62	22
valid_sources[0x23]	5481	1		T61	18		T62	22		T64	2
valid_sources[0x24]	2684	1		T61	22		T62	14		T64	2
valid_sources[0x25]	2746	1		T61	34		T62	17		T64	3
valid_sources[0x26]	3410	1		T24	3		T61	22		T62	13
valid_sources[0x27]	2375	1		T20	1		T148	2		T16	1
valid_sources[0x28]	2777	1		T61	18		T62	23		T64	2
valid_sources[0x29]	3387	1		T61	18		T62	24		T64	6
valid_sources[0x2a]	2427	1		T18	1		T61	12		T62	18
valid_sources[0x2b]	2978	1		T163	2		T61	21		T62	21
valid_sources[0x2c]	2815	1		T61	12		T62	22		T64	2
valid_sources[0x2d]	3114	1		T3	5		T168	2		T61	20
valid_sources[0x2e]	2807	1		T4	1		T33	1		T21	1
valid_sources[0x2f]	3147	1		T61	20		T62	23		T64	1
valid_sources[0x30]	3073	1		T20	1		T61	13		T62	23
valid_sources[0x31]	2914	1		T164	1		T61	13		T62	26
valid_sources[0x32]	2869	1		T61	28		T62	22		T64	5
valid_sources[0x33]	2857	1		T61	8		T62	23		T64	3
valid_sources[0x34]	2863	1		T61	17		T62	18		T64	3
valid_sources[0x35]	2809	1		T25	1		T167	1		T61	37
valid_sources[0x36]	2804	1		T59	1		T22	1		T165	3
valid_sources[0x37]	2716	1		T25	1		T19	1		T61	31
valid_sources[0x38]	3186	1		T40	1		T66	1		T61	16
valid_sources[0x39]	2672	1		T167	1		T61	11		T62	23
valid_sources[0x3a]	2975	1		T61	21		T62	30		T64	1
valid_sources[0x3b]	3994	1		T58	2		T15	1		T148	2
valid_sources[0x3c]	2575	1		T34	10		T21	1		T10	1
valid_sources[0x3d]	3561	1		T22	1		T11	26		T61	24
valid_sources[0x3e]	2436	1		T136	1		T61	20		T62	17
valid_sources[0x3f]	3395	1		T38	14		T61	26		T62	27
valid_sources[0x40]	2695	1		T61	16		T62	25		T64	7
valid_sources[0x41]	3645	1		T32	1		T61	22		T62	26
valid_sources[0x42]	3140	1		T5	5		T61	16		T62	17
valid_sources[0x43]	3059	1		T166	1		T61	14		T62	25
valid_sources[0x44]	3220	1		T61	12		T62	16		T64	5
valid_sources[0x45]	2652	1		T61	32		T62	19		T65	3
valid_sources[0x46]	2750	1		T60	3		T61	28		T62	11
valid_sources[0x47]	3224	1		T10	2		T61	25		T62	23
valid_sources[0x48]	5961	1		T25	1		T168	2		T61	18
valid_sources[0x49]	3509	1		T59	1		T22	1		T168	1
valid_sources[0x4a]	2522	1		T33	1		T60	2		T38	14
valid_sources[0x4b]	2643	1		T61	15		T62	21		T64	2
valid_sources[0x4c]	3037	1		T61	19		T62	21		T64	1
valid_sources[0x4d]	2363	1		T139	1		T61	18		T62	24
valid_sources[0x4e]	2985	1		T23	1		T136	1		T61	27
valid_sources[0x4f]	2602	1		T21	1		T61	17		T62	17
valid_sources[0x50]	2674	1		T165	1		T61	20		T62	16
valid_sources[0x51]	3139	1		T21	2		T166	1		T61	37
valid_sources[0x52]	3159	1		T58	1		T14	8		T61	27
valid_sources[0x53]	2303	1		T25	1		T61	23		T62	25
valid_sources[0x54]	2956	1		T22	1		T167	1		T61	9
valid_sources[0x55]	3783	1		T25	1		T33	1		T22	3
valid_sources[0x56]	2715	1		T21	1		T24	4		T61	17
valid_sources[0x57]	2785	1		T61	29		T62	25		T64	3
valid_sources[0x58]	2932	1		T8	2		T33	1		T61	13
valid_sources[0x59]	9821	1		T22	1		T19	1		T61	12
valid_sources[0x5a]	2591	1		T33	1		T21	1		T61	22
valid_sources[0x5b]	3356	1		T19	2		T165	1		T61	25
valid_sources[0x5c]	3070	1		T19	1		T61	20		T62	28
valid_sources[0x5d]	2937	1		T40	1		T32	1		T22	1
valid_sources[0x5e]	3344	1		T61	38		T62	21		T64	4
valid_sources[0x5f]	2953	1		T167	1		T61	14		T62	19
valid_sources[0x60]	2944	1		T4	7		T60	1		T61	35
valid_sources[0x61]	3689	1		T61	20		T62	27		T64	2
valid_sources[0x62]	2673	1		T168	1		T61	20		T62	12
valid_sources[0x63]	2955	1		T20	1		T22	2		T61	29
valid_sources[0x64]	2661	1		T40	8		T58	3		T14	1
valid_sources[0x65]	3848	1		T61	23		T62	19		T64	2
valid_sources[0x66]	4307	1		T168	1		T61	21		T62	19
valid_sources[0x67]	3161	1		T148	2		T165	1		T61	9
valid_sources[0x68]	2835	1		T61	18		T62	22		T64	6
valid_sources[0x69]	3109	1		T60	1		T167	1		T61	20
valid_sources[0x6a]	2836	1		T23	3		T61	14		T62	16
valid_sources[0x6b]	2892	1		T25	1		T38	1		T61	29
valid_sources[0x6c]	3379	1		T142	4		T61	26		T62	17
valid_sources[0x6d]	3085	1		T61	8		T62	27		T64	2
valid_sources[0x6e]	3231	1		T17	3		T27	1		T59	1
valid_sources[0x6f]	3120	1		T168	1		T16	1		T61	9
valid_sources[0x70]	2371	1		T18	1		T61	17		T62	28
valid_sources[0x71]	3058	1		T61	30		T62	18		T64	4
valid_sources[0x72]	3119	1		T148	2		T61	27		T62	25
valid_sources[0x73]	4892	1		T14	4		T168	1		T61	21
valid_sources[0x74]	2760	1		T27	4		T61	29		T62	25
valid_sources[0x75]	3181	1		T61	23		T62	14		T64	9
valid_sources[0x76]	2724	1		T61	17		T62	23		T64	3
valid_sources[0x77]	2791	1		T22	3		T167	1		T61	22
valid_sources[0x78]	2625	1		T6	14		T25	1		T22	2
valid_sources[0x79]	3086	1		T21	1		T148	1		T61	7
valid_sources[0x7a]	2871	1		T167	1		T168	2		T61	31
valid_sources[0x7b]	2936	1		T61	23		T62	25		T64	3
valid_sources[0x7c]	3519	1		T61	15		T62	28		T64	3
valid_sources[0x7d]	2673	1		T45	1		T61	15		T62	24
valid_sources[0x7e]	2806	1		T61	22		T62	18		T64	3
valid_sources[0x7f]	2794	1		T61	22		T62	17		T64	3
valid_sources[0x80]	2954	1		T18	2		T44	8		T61	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

301438

1

T6

3

T8

1

T4

3

values[0x0]

all_enables

biggest_size

136358

1

T2

1

T3

1

T6

1

values[0x1]

all_enables

biggest_size

136533

1

T2

1

T6

1

T8

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5141	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	30341	1		T1	5		T2	1		T7	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12050	1		T61	34		T62	36		T64	118
values[0x0]	11469	1		T1	1		T7	1		T3	4
values[0x1]	11963	1		T1	4		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3786	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	31696	1		T1	5		T2	1		T7	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	81	1		T63	1		T88	7		T90	2
valid_sources[0x01]	155	1		T136	1		T169	4		T61	1
valid_sources[0x02]	126	1		T170	2		T22	3		T171	1
valid_sources[0x03]	131	1		T169	1		T63	9		T88	18
valid_sources[0x04]	138	1		T138	1		T172	1		T173	2
valid_sources[0x05]	142	1		T18	1		T65	2		T88	5
valid_sources[0x06]	414	1		T174	1		T169	1		T61	1
valid_sources[0x07]	159	1		T59	4		T175	1		T63	3
valid_sources[0x08]	145	1		T176	1		T177	3		T64	39
valid_sources[0x09]	130	1		T61	1		T63	12		T90	2
valid_sources[0x0a]	129	1		T178	1		T61	1		T64	4
valid_sources[0x0b]	264	1		T65	1		T88	15		T90	2
valid_sources[0x0c]	182	1		T63	18		T88	28		T90	6
valid_sources[0x0d]	136	1		T172	2		T75	1		T63	5
valid_sources[0x0e]	126	1		T63	2		T78	2		T71	1
valid_sources[0x0f]	194	1		T30	1		T179	13		T63	3
valid_sources[0x10]	123	1		T79	2		T180	3		T181	1
valid_sources[0x11]	139	1		T65	5		T63	22		T90	14
valid_sources[0x12]	109	1		T182	1		T183	1		T63	5
valid_sources[0x13]	141	1		T134	1		T184	1		T65	1
valid_sources[0x14]	152	1		T184	1		T61	1		T64	16
valid_sources[0x15]	142	1		T64	6		T63	8		T88	9
valid_sources[0x16]	101	1		T1	2		T185	1		T90	4
valid_sources[0x17]	184	1		T171	1		T186	1		T63	12
valid_sources[0x18]	100	1		T129	2		T134	1		T90	2
valid_sources[0x19]	136	1		T182	1		T63	16		T90	6
valid_sources[0x1a]	148	1		T163	2		T145	5		T64	14
valid_sources[0x1b]	140	1		T129	1		T187	1		T63	14
valid_sources[0x1c]	96	1		T138	1		T188	1		T61	2
valid_sources[0x1d]	127	1		T189	1		T61	1		T63	12
valid_sources[0x1e]	183	1		T173	1		T61	1		T62	2
valid_sources[0x1f]	288	1		T33	6		T61	1		T64	2
valid_sources[0x20]	130	1		T190	2		T170	1		T64	12
valid_sources[0x21]	87	1		T170	1		T191	1		T187	1
valid_sources[0x22]	99	1		T129	1		T192	1		T165	1
valid_sources[0x23]	122	1		T32	2		T193	3		T184	1
valid_sources[0x24]	108	1		T170	9		T194	1		T64	8
valid_sources[0x25]	110	1		T9	1		T191	1		T195	1
valid_sources[0x26]	143	1		T25	1		T61	2		T63	3
valid_sources[0x27]	156	1		T189	1		T63	12		T90	2
valid_sources[0x28]	87	1		T63	2		T88	1		T90	4
valid_sources[0x29]	97	1		T170	2		T187	1		T62	1
valid_sources[0x2a]	117	1		T61	1		T63	9		T90	2
valid_sources[0x2b]	154	1		T64	12		T63	14		T82	1
valid_sources[0x2c]	107	1		T31	2		T196	1		T172	1
valid_sources[0x2d]	160	1		T197	8		T61	2		T63	9
valid_sources[0x2e]	139	1		T195	1		T198	1		T62	7
valid_sources[0x2f]	114	1		T199	1		T65	1		T63	16
valid_sources[0x30]	130	1		T43	1		T63	12		T90	4
valid_sources[0x31]	89	1		T187	1		T200	1		T61	1
valid_sources[0x32]	89	1		T68	1		T189	1		T88	1
valid_sources[0x33]	105	1		T3	6		T181	3		T184	1
valid_sources[0x34]	115	1		T31	1		T134	1		T65	1
valid_sources[0x35]	203	1		T67	21		T200	2		T61	2
valid_sources[0x36]	122	1		T201	1		T202	2		T203	1
valid_sources[0x37]	87	1		T173	1		T184	1		T63	16
valid_sources[0x38]	176	1		T137	5		T204	1		T136	1
valid_sources[0x39]	94	1		T182	1		T61	1		T62	1
valid_sources[0x3a]	105	1		T56	1		T64	12		T63	16
valid_sources[0x3b]	115	1		T182	1		T205	1		T169	1
valid_sources[0x3c]	113	1		T206	1		T61	1		T63	1
valid_sources[0x3d]	106	1		T207	1		T136	1		T63	1
valid_sources[0x3e]	230	1		T129	2		T200	3		T63	9
valid_sources[0x3f]	118	1		T195	1		T61	1		T65	3
valid_sources[0x40]	150	1		T208	11		T61	1		T64	3
valid_sources[0x41]	154	1		T185	1		T206	1		T42	1
valid_sources[0x42]	283	1		T209	3		T174	1		T63	11
valid_sources[0x43]	103	1		T165	1		T184	1		T63	1
valid_sources[0x44]	160	1		T199	1		T144	1		T210	1
valid_sources[0x45]	95	1		T211	1		T212	1		T82	2
valid_sources[0x46]	98	1		T213	1		T63	1		T90	4
valid_sources[0x47]	158	1		T56	1		T189	1		T62	6
valid_sources[0x48]	84	1		T214	1		T63	4		T90	2
valid_sources[0x49]	256	1		T215	3		T164	1		T11	10
valid_sources[0x4a]	117	1		T25	4		T194	5		T63	9
valid_sources[0x4b]	121	1		T25	1		T31	1		T64	1
valid_sources[0x4c]	130	1		T216	1		T169	1		T63	2
valid_sources[0x4d]	163	1		T63	5		T88	48		T90	9
valid_sources[0x4e]	129	1		T199	1		T210	2		T217	1
valid_sources[0x4f]	170	1		T136	1		T63	17		T88	24
valid_sources[0x50]	93	1		T49	1		T134	1		T82	1
valid_sources[0x51]	111	1		T4	8		T181	1		T78	1
valid_sources[0x52]	86	1		T31	1		T209	2		T217	1
valid_sources[0x53]	128	1		T63	9		T81	2		T78	1
valid_sources[0x54]	109	1		T90	2		T84	1		T85	7
valid_sources[0x55]	70	1		T218	1		T61	1		T63	3
valid_sources[0x56]	132	1		T61	2		T65	2		T63	13
valid_sources[0x57]	177	1		T219	1		T59	3		T220	1
valid_sources[0x58]	90	1		T80	1		T35	1		T221	1
valid_sources[0x59]	137	1		T25	1		T181	1		T202	1
valid_sources[0x5a]	93	1		T22	1		T65	1		T63	2
valid_sources[0x5b]	136	1		T30	1		T14	6		T222	1
valid_sources[0x5c]	93	1		T10	6		T200	1		T61	1
valid_sources[0x5d]	131	1		T223	8		T163	1		T184	1
valid_sources[0x5e]	149	1		T65	2		T63	9		T88	29
valid_sources[0x5f]	137	1		T21	1		T224	2		T195	1
valid_sources[0x60]	103	1		T44	1		T195	1		T63	20
valid_sources[0x61]	124	1		T148	7		T225	1		T63	1
valid_sources[0x62]	142	1		T31	1		T195	1		T65	1
valid_sources[0x63]	118	1		T190	1		T226	17		T184	1
valid_sources[0x64]	313	1		T17	1		T227	2		T65	1
valid_sources[0x65]	109	1		T49	3		T163	1		T61	1
valid_sources[0x66]	142	1		T63	2		T90	2		T71	1
valid_sources[0x67]	155	1		T207	1		T22	3		T61	1
valid_sources[0x68]	94	1		T129	1		T31	2		T189	1
valid_sources[0x69]	133	1		T181	1		T184	1		T62	2
valid_sources[0x6a]	155	1		T190	7		T171	1		T228	1
valid_sources[0x6b]	132	1		T87	1		T63	5		T88	32
valid_sources[0x6c]	122	1		T189	1		T63	8		T90	6
valid_sources[0x6d]	126	1		T204	1		T147	1		T63	5
valid_sources[0x6e]	123	1		T56	1		T172	1		T63	7
valid_sources[0x6f]	127	1		T216	2		T229	3		T184	1
valid_sources[0x70]	105	1		T34	1		T65	1		T78	1
valid_sources[0x71]	119	1		T230	15		T71	2		T84	1
valid_sources[0x72]	130	1		T207	1		T231	12		T232	5
valid_sources[0x73]	150	1		T30	1		T185	1		T191	1
valid_sources[0x74]	129	1		T217	1		T171	1		T64	3
valid_sources[0x75]	113	1		T49	1		T233	1		T64	13
valid_sources[0x76]	100	1		T234	1		T195	1		T235	1
valid_sources[0x77]	170	1		T43	1		T174	1		T171	1
valid_sources[0x78]	96	1		T63	18		T78	1		T82	1
valid_sources[0x79]	173	1		T236	10		T171	1		T63	9
valid_sources[0x7a]	94	1		T28	1		T90	12		T71	2
valid_sources[0x7b]	149	1		T128	3		T237	1		T195	1
valid_sources[0x7c]	99	1		T213	1		T238	1		T43	1
valid_sources[0x7d]	139	1		T58	7		T62	7		T65	3
valid_sources[0x7e]	129	1		T129	1		T239	1		T63	26
valid_sources[0x7f]	128	1		T199	1		T174	1		T184	1
valid_sources[0x80]	143	1		T170	3		T134	1		T43	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9192

1

T61

11

T62

13

T64

114

values[0x0]

all_enables

biggest_size

10680

1

T1

1

T7

1

T3

4

values[0x1]

all_enables

biggest_size

10469

1

T1

4

T2

1

T3

2