SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 853631 | 1 | T2 | 2 | T3 | 5 | T6 | 14 | |||
auto[1] | 42985 | 1 | T38 | 80 | T39 | 80 | T61 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 896439 | 1 | T2 | 2 | T3 | 5 | T6 | 14 | |||
values[1] | 18 | 1 | T62 | 1 | T81 | 1 | T85 | 1 | |||
values[2] | 3 | 1 | T150 | 1 | T151 | 2 | - | - | |||
values[3] | 95 | 1 | T61 | 1 | T62 | 1 | T81 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 896421 | 1 | T2 | 2 | T3 | 5 | T6 | 14 | |||
values[1] | 23 | 1 | T85 | 1 | T152 | 1 | T130 | 2 | |||
values[2] | 8 | 1 | T62 | 2 | T150 | 1 | T153 | 1 | |||
values[3] | 93 | 1 | T61 | 3 | T62 | 5 | T81 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 896346 | 1 | T2 | 2 | T3 | 5 | T6 | 14 | |||
auto[TlIntgErrCmd] | 75 | 1 | T61 | 4 | T81 | 3 | T85 | 3 | |||
auto[TlIntgErrData] | 93 | 1 | T61 | 2 | T62 | 8 | T81 | 5 | |||
auto[TlIntgErrBoth] | 102 | 1 | T61 | 4 | T62 | 2 | T81 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 77510 | 0 | T1 | 5 | T2 | 1 | T7 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 77331 | 1 | T1 | 5 | T2 | 1 | T7 | 1 | |||
values[1] | 15 | 1 | T152 | 1 | T130 | 1 | T150 | 2 | |||
values[2] | 3 | 1 | T150 | 1 | T154 | 1 | T155 | 1 | |||
values[3] | 98 | 1 | T61 | 8 | T62 | 2 | T81 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 77339 | 1 | T1 | 5 | T2 | 1 | T7 | 1 | |||
values[1] | 13 | 1 | T85 | 1 | T150 | 1 | T156 | 2 | |||
values[2] | 4 | 1 | T152 | 1 | T154 | 1 | T157 | 1 | |||
values[3] | 75 | 1 | T61 | 4 | T62 | 5 | T81 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 77240 | 1 | T1 | 5 | T2 | 1 | T7 | 1 | |||
auto[TlIntgErrCmd] | 99 | 1 | T61 | 3 | T62 | 4 | T81 | 4 | |||
auto[TlIntgErrData] | 91 | 1 | T61 | 1 | T62 | 5 | T81 | 3 | |||
auto[TlIntgErrBoth] | 80 | 1 | T61 | 6 | T62 | 1 | T81 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |