Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	318549	1		T3	4		T6	9		T4	4
full_word	578067	1		T2	2		T3	1		T6	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	896346	1		T2	2		T3	5		T6	14
auto[TlIntgErrCmd]	75	1		T61	4		T81	3		T85	3
auto[TlIntgErrData]	93	1		T61	2		T62	8		T81	5
auto[TlIntgErrBoth]	102	1		T61	4		T62	2		T81	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	515343	1		T6	6		T8	1		T4	3
auto[1]	381273	1		T2	2		T3	5		T6	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	213309	1		T6	3		T40	4		T5	3
auto[TlIntgErrNone]	partial	auto[1]	104993	1		T3	4		T6	6		T4	4
auto[TlIntgErrNone]	full_word	auto[0]	301904	1		T6	3		T8	1		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	276140	1		T2	2		T3	1		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T61	2		T81	3		T85	2
auto[TlIntgErrCmd]	partial	auto[1]	39	1		T61	2		T85	1		T152	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T152	1		T130	1		T150	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T152	1		T155	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T62	4		T81	3		T85	1
auto[TlIntgErrData]	partial	auto[1]	35	1		T61	2		T62	3		T81	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T85	1		T130	1		T159	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T62	1		T81	1		T160	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T61	1		T62	2		T85	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T61	3		T81	2		T85	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T150	1		T160	1		T151	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T161	1		T156	1		T154	1