Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9790935	9789627	0	0
selKnown1	64009134	64007826	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	9790935	9789627	0	0
T1	22091	22087	0	0
T2	1067	1063	0	0
T3	38115	38111	0	0
T4	0	10	0	0
T5	0	14	0	0
T6	5156	5152	0	0
T7	1873	1869	0	0
T8	1761	1757	0	0
T12	481012	481008	0	0
T13	31171	31167	0	0
T25	0	8	0	0
T26	0	8	0	0
T27	0	6	0	0
T29	5536	5532	0	0
T30	0	10	0	0
T46	271	267	0	0
T47	0	40	0	0
T56	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	64009134	64007826	0	0
T1	340224	340220	0	0
T2	10547	10543	0	0
T3	208727	208723	0	0
T4	0	6	0	0
T5	0	8	0	0
T6	79946	79942	0	0
T7	37719	37715	0	0
T8	18686	18682	0	0
T12	355358	355355	0	0
T13	90274	90270	0	0
T25	0	8	0	0
T26	0	8	0	0
T27	0	2	0	0
T29	11137	11133	0	0
T30	0	10	0	0
T46	7467	7463	0	0
T47	0	40	0	0
T56	0	8	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2704511	2704294	0	0
selKnown1	56923134	56922917	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2704511	2704294	0	0
T1	11040	11039	0	0
T2	532	531	0	0
T3	19049	19048	0	0
T6	2577	2576	0	0
T7	935	934	0	0
T8	879	878	0	0
T12	240505	240504	0	0
T13	15584	15583	0	0
T29	2767	2766	0	0
T46	134	133	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	56923134	56922917	0	0
T1	329174	329173	0	0
T2	10013	10012	0	0
T3	189674	189673	0	0
T6	77367	77366	0	0
T7	36782	36781	0	0
T8	17805	17804	0	0
T12	114851	114851	0	0
T13	74688	74687	0	0
T29	8368	8367	0	0
T46	7331	7330	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	601	384	0	0
selKnown1	583	366	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	601	384	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	2	1	0	0
T4	0	4	0	0
T5	0	4	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	1	0	0	0
T12	1	0	0	0
T13	1	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	1	0	0
T29	1	0	0	0
T30	0	5	0	0
T46	1	0	0	0
T47	0	20	0	0
T56	0	4	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	583	366	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	2	1	0	0
T4	0	3	0	0
T5	0	4	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	1	0	0	0
T12	1	0	0	0
T13	1	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	1	0	0
T29	1	0	0	0
T30	0	5	0	0
T46	1	0	0	0
T47	0	20	0	0
T56	0	4	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7083980	7083543	0	0
selKnown1	7083772	7083335	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7083980	7083543	0	0
T1	11041	11040	0	0
T2	533	532	0	0
T3	19050	19049	0	0
T6	2577	2576	0	0
T7	935	934	0	0
T8	880	879	0	0
T12	240505	240504	0	0
T13	15585	15584	0	0
T29	2767	2766	0	0
T46	135	134	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	7083772	7083335	0	0
T1	11040	11039	0	0
T2	532	531	0	0
T3	19049	19048	0	0
T6	2577	2576	0	0
T7	935	934	0	0
T8	879	878	0	0
T12	240505	240504	0	0
T13	15584	15583	0	0
T29	2767	2766	0	0
T46	134	133	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1843	1406	0	0
selKnown1	1645	1208	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1843	1406	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	14	13	0	0
T4	0	6	0	0
T5	0	10	0	0
T6	1	0	0	0
T7	2	1	0	0
T8	1	0	0	0
T12	1	0	0	0
T13	1	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	5	0	0
T29	1	0	0	0
T30	0	5	0	0
T46	1	0	0	0
T47	0	20	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1645	1208	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	2	1	0	0
T4	0	3	0	0
T5	0	4	0	0
T6	1	0	0	0
T7	1	0	0	0
T8	1	0	0	0
T12	1	0	0	0
T13	1	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	1	0	0
T29	1	0	0	0
T30	0	5	0	0
T46	1	0	0	0
T47	0	20	0	0
T56	0	4	0	0