SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
79.81 | 98.04 | 77.78 | 85.71 | 87.50 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1302 | 1302 | 0 | 0 |
OutputsKnown_A | 341538804 | 341307228 | 0 | 0 |
gen_flops.OutputDelay_A | 170769402 | 170648367 | 0 | 1953 |
gen_no_flops.OutputDelay_A | 170769402 | 170653614 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1302 | 1302 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
T46 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 341538804 | 341307228 | 0 | 0 |
T1 | 1975044 | 1972950 | 0 | 0 |
T2 | 60078 | 59682 | 0 | 0 |
T3 | 1138044 | 1137318 | 0 | 0 |
T6 | 464202 | 463788 | 0 | 0 |
T7 | 220692 | 220392 | 0 | 0 |
T8 | 106830 | 106518 | 0 | 0 |
T12 | 689106 | 689064 | 0 | 0 |
T13 | 448128 | 447708 | 0 | 0 |
T29 | 50208 | 49782 | 0 | 0 |
T46 | 43986 | 43596 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 170769402 | 170648367 | 0 | 1953 |
T1 | 987522 | 986430 | 0 | 9 |
T2 | 30039 | 29832 | 0 | 9 |
T3 | 569022 | 568641 | 0 | 9 |
T6 | 232101 | 231885 | 0 | 9 |
T7 | 110346 | 110187 | 0 | 9 |
T8 | 53415 | 53250 | 0 | 9 |
T12 | 344553 | 344532 | 0 | 9 |
T13 | 224064 | 223845 | 0 | 9 |
T29 | 25104 | 24882 | 0 | 9 |
T46 | 21993 | 21789 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 170769402 | 170653614 | 0 | 0 |
T1 | 987522 | 986475 | 0 | 0 |
T2 | 30039 | 29841 | 0 | 0 |
T3 | 569022 | 568659 | 0 | 0 |
T6 | 232101 | 231894 | 0 | 0 |
T7 | 110346 | 110196 | 0 | 0 |
T8 | 53415 | 53259 | 0 | 0 |
T12 | 344553 | 344532 | 0 | 0 |
T13 | 224064 | 223854 | 0 | 0 |
T29 | 25104 | 24891 | 0 | 0 |
T46 | 21993 | 21798 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_flops.OutputDelay_A | 56923134 | 56882789 | 0 | 651 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56882789 | 0 | 651 |
T1 | 329174 | 328810 | 0 | 3 |
T2 | 10013 | 9944 | 0 | 3 |
T3 | 189674 | 189547 | 0 | 3 |
T6 | 77367 | 77295 | 0 | 3 |
T7 | 36782 | 36729 | 0 | 3 |
T8 | 17805 | 17750 | 0 | 3 |
T12 | 114851 | 114844 | 0 | 3 |
T13 | 74688 | 74615 | 0 | 3 |
T29 | 8368 | 8294 | 0 | 3 |
T46 | 7331 | 7263 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_flops.OutputDelay_A | 56923134 | 56882789 | 0 | 651 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56882789 | 0 | 651 |
T1 | 329174 | 328810 | 0 | 3 |
T2 | 10013 | 9944 | 0 | 3 |
T3 | 189674 | 189547 | 0 | 3 |
T6 | 77367 | 77295 | 0 | 3 |
T7 | 36782 | 36729 | 0 | 3 |
T8 | 17805 | 17750 | 0 | 3 |
T12 | 114851 | 114844 | 0 | 3 |
T13 | 74688 | 74615 | 0 | 3 |
T29 | 8368 | 8294 | 0 | 3 |
T46 | 7331 | 7263 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56923134 | 56884538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_flops.OutputDelay_A | 56923134 | 56882789 | 0 | 651 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56882789 | 0 | 651 |
T1 | 329174 | 328810 | 0 | 3 |
T2 | 10013 | 9944 | 0 | 3 |
T3 | 189674 | 189547 | 0 | 3 |
T6 | 77367 | 77295 | 0 | 3 |
T7 | 36782 | 36729 | 0 | 3 |
T8 | 17805 | 17750 | 0 | 3 |
T12 | 114851 | 114844 | 0 | 3 |
T13 | 74688 | 74615 | 0 | 3 |
T29 | 8368 | 8294 | 0 | 3 |
T46 | 7331 | 7263 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56923134 | 56884538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 217 | 217 | 0 | 0 |
OutputsKnown_A | 56923134 | 56884538 | 0 | 0 |
gen_no_flops.OutputDelay_A | 56923134 | 56884538 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 217 | 217 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T46 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 56923134 | 56884538 | 0 | 0 |
T1 | 329174 | 328825 | 0 | 0 |
T2 | 10013 | 9947 | 0 | 0 |
T3 | 189674 | 189553 | 0 | 0 |
T6 | 77367 | 77298 | 0 | 0 |
T7 | 36782 | 36732 | 0 | 0 |
T8 | 17805 | 17753 | 0 | 0 |
T12 | 114851 | 114844 | 0 | 0 |
T13 | 74688 | 74618 | 0 | 0 |
T29 | 8368 | 8297 | 0 | 0 |
T46 | 7331 | 7266 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |