Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	2911607	1		T3	21		T6	9		T7	42
full_word	994621	1		T3	9		T6	5		T7	15

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3905948	1		T3	30		T6	14		T7	57
auto[TlIntgErrCmd]	104	1		T71	5		T89	9		T125	4
auto[TlIntgErrData]	84	1		T71	3		T89	8		T125	2
auto[TlIntgErrBoth]	92	1		T71	2		T89	3		T125	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	669533	1		T3	7		T6	6		T7	12
auto[1]	3236695	1		T3	23		T6	8		T7	45

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	286992	1		T3	5		T6	3		T7	5
auto[TlIntgErrNone]	partial	auto[1]	2624353	1		T3	16		T6	6		T7	37
auto[TlIntgErrNone]	full_word	auto[0]	382412	1		T3	2		T6	3		T7	7
auto[TlIntgErrNone]	full_word	auto[1]	612191	1		T3	7		T6	2		T7	8
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T71	2		T89	2		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T71	3		T89	7		T125	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T163	1		T164	1		T165	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T160	1		T164	1		T165	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T71	1		T89	3		T125	2
auto[TlIntgErrData]	partial	auto[1]	36	1		T71	1		T89	5		T159	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T153	2		T154	1		T161	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T71	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T89	1		T159	1		T158	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T71	2		T89	2		T125	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T125	1		T164	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T159	1		T156	2		-	-