Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	133993996	709901	0	0
late_debug_enable_rd_A	133993996	33699	0	0
late_debug_enable_regwen_rd_A	133993996	29739	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133993996	709901	0	0
T4	889386	18170	0	0
T5	179539	0	0	0
T10	0	49797	0	0
T11	0	190834	0	0
T14	0	166915	0	0
T16	252266	0	0	0
T17	235372	44326	0	0
T20	0	45629	0	0
T40	2752	0	0	0
T47	63132	0	0	0
T48	255309	0	0	0
T69	0	15336	0	0
T70	0	44670	0	0
T71	0	4	0	0
T73	191573	0	0	0
T74	975241	0	0	0
T75	31570	0	0	0
T89	0	4	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133993996	33699	0	0
T17	235372	15944	0	0
T20	0	15253	0	0
T41	4509	0	0	0
T49	267982	0	0	0
T50	95192	0	0	0
T64	0	188	0	0
T75	31570	0	0	0
T79	0	58	0	0
T84	0	68	0	0
T87	0	5	0	0
T88	0	35	0	0
T89	0	80	0	0
T115	4322	0	0	0
T119	0	39	0	0
T120	0	27	0	0
T121	21029	0	0	0
T122	23987	0	0	0
T123	2457	0	0	0
T124	329651	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133993996	29739	0	0
T17	235372	13661	0	0
T20	0	13556	0	0
T41	4509	0	0	0
T49	267982	0	0	0
T50	95192	0	0	0
T64	0	183	0	0
T75	31570	0	0	0
T79	0	108	0	0
T84	0	41	0	0
T87	0	6	0	0
T88	0	24	0	0
T89	0	75	0	0
T115	4322	0	0	0
T119	0	12	0	0
T120	0	52	0	0
T121	21029	0	0	0
T122	23987	0	0	0
T123	2457	0	0	0
T124	329651	0	0	0