Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
709901 |
0 |
0 |
T4 |
889386 |
18170 |
0 |
0 |
T5 |
179539 |
0 |
0 |
0 |
T10 |
0 |
49797 |
0 |
0 |
T11 |
0 |
190834 |
0 |
0 |
T14 |
0 |
166915 |
0 |
0 |
T16 |
252266 |
0 |
0 |
0 |
T17 |
235372 |
44326 |
0 |
0 |
T20 |
0 |
45629 |
0 |
0 |
T40 |
2752 |
0 |
0 |
0 |
T47 |
63132 |
0 |
0 |
0 |
T48 |
255309 |
0 |
0 |
0 |
T69 |
0 |
15336 |
0 |
0 |
T70 |
0 |
44670 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T73 |
191573 |
0 |
0 |
0 |
T74 |
975241 |
0 |
0 |
0 |
T75 |
31570 |
0 |
0 |
0 |
T89 |
0 |
4 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
33699 |
0 |
0 |
T17 |
235372 |
15944 |
0 |
0 |
T20 |
0 |
15253 |
0 |
0 |
T41 |
4509 |
0 |
0 |
0 |
T49 |
267982 |
0 |
0 |
0 |
T50 |
95192 |
0 |
0 |
0 |
T64 |
0 |
188 |
0 |
0 |
T75 |
31570 |
0 |
0 |
0 |
T79 |
0 |
58 |
0 |
0 |
T84 |
0 |
68 |
0 |
0 |
T87 |
0 |
5 |
0 |
0 |
T88 |
0 |
35 |
0 |
0 |
T89 |
0 |
80 |
0 |
0 |
T115 |
4322 |
0 |
0 |
0 |
T119 |
0 |
39 |
0 |
0 |
T120 |
0 |
27 |
0 |
0 |
T121 |
21029 |
0 |
0 |
0 |
T122 |
23987 |
0 |
0 |
0 |
T123 |
2457 |
0 |
0 |
0 |
T124 |
329651 |
0 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
29739 |
0 |
0 |
T17 |
235372 |
13661 |
0 |
0 |
T20 |
0 |
13556 |
0 |
0 |
T41 |
4509 |
0 |
0 |
0 |
T49 |
267982 |
0 |
0 |
0 |
T50 |
95192 |
0 |
0 |
0 |
T64 |
0 |
183 |
0 |
0 |
T75 |
31570 |
0 |
0 |
0 |
T79 |
0 |
108 |
0 |
0 |
T84 |
0 |
41 |
0 |
0 |
T87 |
0 |
6 |
0 |
0 |
T88 |
0 |
24 |
0 |
0 |
T89 |
0 |
75 |
0 |
0 |
T115 |
4322 |
0 |
0 |
0 |
T119 |
0 |
12 |
0 |
0 |
T120 |
0 |
52 |
0 |
0 |
T121 |
21029 |
0 |
0 |
0 |
T122 |
23987 |
0 |
0 |
0 |
T123 |
2457 |
0 |
0 |
0 |
T124 |
329651 |
0 |
0 |
0 |