Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
15339320 |
15337986 |
0 |
0 |
selKnown1 |
72203035 |
72201701 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
15339320 |
15337986 |
0 |
0 |
T1 |
22869 |
22867 |
0 |
0 |
T2 |
13432 |
13430 |
0 |
0 |
T3 |
20266 |
20262 |
0 |
0 |
T4 |
0 |
19 |
0 |
0 |
T7 |
0 |
10 |
0 |
0 |
T8 |
8 |
6 |
0 |
0 |
T15 |
12877 |
12873 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T17 |
0 |
30 |
0 |
0 |
T23 |
12571 |
12567 |
0 |
0 |
T24 |
11495 |
11491 |
0 |
0 |
T33 |
18652 |
18648 |
0 |
0 |
T34 |
31320 |
31316 |
0 |
0 |
T38 |
841 |
837 |
0 |
0 |
T39 |
17301 |
17297 |
0 |
0 |
T47 |
0 |
8 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
T49 |
0 |
10 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72203035 |
72201701 |
0 |
0 |
T1 |
807698 |
807696 |
0 |
0 |
T2 |
284847 |
284845 |
0 |
0 |
T3 |
332460 |
332456 |
0 |
0 |
T4 |
0 |
10 |
0 |
0 |
T7 |
0 |
8 |
0 |
0 |
T8 |
2 |
0 |
0 |
0 |
T15 |
10936 |
10932 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T17 |
0 |
10 |
0 |
0 |
T23 |
51347 |
51343 |
0 |
0 |
T24 |
86594 |
86590 |
0 |
0 |
T33 |
72578 |
72574 |
0 |
0 |
T34 |
501709 |
501705 |
0 |
0 |
T38 |
1995 |
1991 |
0 |
0 |
T39 |
105062 |
105058 |
0 |
0 |
T47 |
0 |
8 |
0 |
0 |
T48 |
0 |
6 |
0 |
0 |
T49 |
0 |
10 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5434403 |
5434179 |
0 |
0 |
selKnown1 |
62298652 |
62298428 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5434403 |
5434179 |
0 |
0 |
T1 |
11434 |
11433 |
0 |
0 |
T2 |
6716 |
6715 |
0 |
0 |
T3 |
10128 |
10127 |
0 |
0 |
T15 |
6437 |
6436 |
0 |
0 |
T23 |
6284 |
6283 |
0 |
0 |
T24 |
5746 |
5745 |
0 |
0 |
T33 |
9320 |
9319 |
0 |
0 |
T34 |
15659 |
15658 |
0 |
0 |
T38 |
419 |
418 |
0 |
0 |
T39 |
8649 |
8648 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
62298652 |
62298428 |
0 |
0 |
T1 |
796264 |
796263 |
0 |
0 |
T2 |
278131 |
278130 |
0 |
0 |
T3 |
322326 |
322325 |
0 |
0 |
T15 |
4497 |
4496 |
0 |
0 |
T23 |
45061 |
45060 |
0 |
0 |
T24 |
80846 |
80845 |
0 |
0 |
T33 |
63246 |
63245 |
0 |
0 |
T34 |
486048 |
486047 |
0 |
0 |
T38 |
1574 |
1573 |
0 |
0 |
T39 |
96411 |
96410 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
574 |
350 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
0 |
9 |
0 |
0 |
T7 |
0 |
5 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
8 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T33 |
6 |
5 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
533 |
309 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
0 |
5 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
5 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T33 |
6 |
5 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9902412 |
9901969 |
0 |
0 |
selKnown1 |
9902208 |
9901765 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9902412 |
9901969 |
0 |
0 |
T1 |
11435 |
11434 |
0 |
0 |
T2 |
6716 |
6715 |
0 |
0 |
T3 |
10129 |
10128 |
0 |
0 |
T15 |
6438 |
6437 |
0 |
0 |
T23 |
6285 |
6284 |
0 |
0 |
T24 |
5747 |
5746 |
0 |
0 |
T33 |
9320 |
9319 |
0 |
0 |
T34 |
15659 |
15658 |
0 |
0 |
T38 |
420 |
419 |
0 |
0 |
T39 |
8650 |
8649 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9902208 |
9901765 |
0 |
0 |
T1 |
11434 |
11433 |
0 |
0 |
T2 |
6716 |
6715 |
0 |
0 |
T3 |
10128 |
10127 |
0 |
0 |
T15 |
6437 |
6436 |
0 |
0 |
T23 |
6284 |
6283 |
0 |
0 |
T24 |
5746 |
5745 |
0 |
0 |
T33 |
9320 |
9319 |
0 |
0 |
T34 |
15659 |
15658 |
0 |
0 |
T38 |
419 |
418 |
0 |
0 |
T39 |
8649 |
8648 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1931 |
1488 |
0 |
0 |
selKnown1 |
1642 |
1199 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1931 |
1488 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
0 |
10 |
0 |
0 |
T7 |
0 |
5 |
0 |
0 |
T8 |
7 |
6 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
22 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T33 |
6 |
5 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1642 |
1199 |
0 |
0 |
T3 |
3 |
2 |
0 |
0 |
T4 |
0 |
5 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T15 |
1 |
0 |
0 |
0 |
T16 |
0 |
4 |
0 |
0 |
T17 |
0 |
5 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T33 |
6 |
5 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T39 |
1 |
0 |
0 |
0 |
T47 |
0 |
4 |
0 |
0 |
T48 |
0 |
3 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
1 |
0 |
0 |
0 |