Line Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 35 | 35 | 100.00 |
ALWAYS | 67 | 4 | 4 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 215 | 4 | 4 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
ALWAYS | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
ALWAYS | 244 | 4 | 4 | 100.00 |
ALWAYS | 252 | 5 | 5 | 100.00 |
CONT_ASSIGN | 277 | 0 | 0 | |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
|
|
|
MISSING_ELSE |
76 |
1 |
1 |
88 |
1 |
1 |
89 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
136 |
1 |
1 |
150 |
1 |
1 |
184 |
1 |
1 |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
221 |
1 |
1 |
225 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
244 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
247 |
1 |
1 |
252 |
1 |
1 |
253 |
1 |
1 |
255 |
1 |
1 |
259 |
1 |
1 |
263 |
1 |
1 |
277 |
|
unreachable |
285 |
1 |
1 |
286 |
1 |
1 |
Cond Coverage for Module :
rv_dm_regs_reg_top
| Total | Covered | Percent |
Conditions | 56 | 56 | 100.00 |
Logical | 56 | 56 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 57
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T17,T14 |
1 | 1 | Covered | T1,T2,T3 |
LINE 69
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T42,T43,T44 |
1 | 0 | Covered | T71,T89,T125 |
LINE 76
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T42,T43,T44 |
0 | 1 | 0 | Covered | T71,T89,T125 |
1 | 0 | 0 | Covered | T42,T43,T44 |
LINE 118
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T71,T89,T125 |
0 | 1 | 0 | Covered | T4,T17,T14 |
1 | 0 | 0 | Covered | T4,T17,T14 |
LINE 184
EXPRESSION (late_debug_enable_we & late_debug_enable_regwen_qs)
----------1--------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T71,T89,T79 |
1 | 1 | Covered | T1,T2,T3 |
LINE 216
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T38,T52 |
LINE 217
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET)
---------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T38,T23,T39 |
LINE 218
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T17,T14 |
LINE 225
EXPRESSION (reg_we & ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))))
---1-- ----------------------------------------------------------------2---------------------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T38,T23 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T17,T14 |
LINE 225
SUB-EXPRESSION ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))))
-------------------1------------------- -------------------2------------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T38,T23 |
0 | 1 | 0 | Covered | T23,T4,T5 |
1 | 0 | 0 | Covered | T1,T38,T4 |
LINE 225
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T38,T23 |
1 | 0 | Covered | T38,T52,T4 |
1 | 1 | Covered | T1,T38,T4 |
LINE 225
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T38,T23 |
1 | 0 | Covered | T38,T39,T52 |
1 | 1 | Covered | T23,T4,T5 |
LINE 225
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T38,T23 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T38,T23 |
LINE 232
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T38,T39 |
1 | 1 | 0 | Covered | T4,T17,T14 |
1 | 1 | 1 | Covered | T38,T52,T40 |
LINE 235
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T38,T23,T39 |
1 | 1 | 0 | Covered | T4,T17,T14 |
1 | 1 | 1 | Covered | T71,T89,T79 |
LINE 238
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T38,T52,T40 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T4,T17,T14 |
1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
221 |
2 |
2 |
100.00 |
IF |
67 |
3 |
3 |
100.00 |
CASE |
253 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm_regs_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 221 ((reg_re || reg_we)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 67 if ((!rst_ni))
-2-: 69 if ((intg_err || reg_we_err))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T42,T43,T44 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 253 case (1'b1)
Branches:
-1- | Status | Tests |
addr_hit[0] |
Covered |
T1,T2,T3 |
addr_hit[1] |
Covered |
T2,T3,T15 |
addr_hit[2] |
Covered |
T1,T2,T3 |
default |
Covered |
T2,T3,T15 |
Assert Coverage for Module :
rv_dm_regs_reg_top
Assertion Details
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
27309 |
0 |
0 |
T1 |
796264 |
1 |
0 |
0 |
T2 |
278131 |
1 |
0 |
0 |
T3 |
322326 |
6 |
0 |
0 |
T15 |
4497 |
1 |
0 |
0 |
T23 |
45061 |
1 |
0 |
0 |
T24 |
80846 |
1 |
0 |
0 |
T33 |
63246 |
6 |
0 |
0 |
T34 |
486048 |
1 |
0 |
0 |
T38 |
1574 |
8 |
0 |
0 |
T39 |
96411 |
1 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
27309 |
0 |
0 |
T1 |
796264 |
1 |
0 |
0 |
T2 |
278131 |
1 |
0 |
0 |
T3 |
322326 |
6 |
0 |
0 |
T15 |
4497 |
1 |
0 |
0 |
T23 |
45061 |
1 |
0 |
0 |
T24 |
80846 |
1 |
0 |
0 |
T33 |
63246 |
6 |
0 |
0 |
T34 |
486048 |
1 |
0 |
0 |
T38 |
1574 |
8 |
0 |
0 |
T39 |
96411 |
1 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
12295 |
0 |
0 |
T4 |
889386 |
216 |
0 |
0 |
T5 |
179539 |
0 |
0 |
0 |
T10 |
0 |
523 |
0 |
0 |
T11 |
0 |
2032 |
0 |
0 |
T14 |
0 |
1778 |
0 |
0 |
T16 |
252266 |
0 |
0 |
0 |
T17 |
235372 |
439 |
0 |
0 |
T20 |
0 |
446 |
0 |
0 |
T40 |
2752 |
0 |
0 |
0 |
T47 |
63132 |
0 |
0 |
0 |
T48 |
255309 |
0 |
0 |
0 |
T69 |
0 |
159 |
0 |
0 |
T70 |
0 |
508 |
0 |
0 |
T71 |
0 |
36 |
0 |
0 |
T73 |
191573 |
0 |
0 |
0 |
T74 |
975241 |
0 |
0 |
0 |
T75 |
31570 |
0 |
0 |
0 |
T89 |
0 |
66 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
133993996 |
15014 |
0 |
0 |
T1 |
796264 |
1 |
0 |
0 |
T2 |
278131 |
1 |
0 |
0 |
T3 |
322326 |
6 |
0 |
0 |
T15 |
4497 |
1 |
0 |
0 |
T23 |
45061 |
1 |
0 |
0 |
T24 |
80846 |
1 |
0 |
0 |
T33 |
63246 |
6 |
0 |
0 |
T34 |
486048 |
1 |
0 |
0 |
T38 |
1574 |
8 |
0 |
0 |
T39 |
96411 |
1 |
0 |
0 |