SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 224 | 224 | 0 | 0 |
OutputsKnown_A | 62298652 | 62260807 | 0 | 0 |
gen_no_flops.OutputDelay_A | 62298652 | 62260807 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 224 | 224 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T38 | 1 | 1 | 0 | 0 |
T39 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 62298652 | 62260807 | 0 | 0 |
T1 | 796264 | 796206 | 0 | 0 |
T2 | 278131 | 278072 | 0 | 0 |
T3 | 322326 | 322147 | 0 | 0 |
T15 | 4497 | 4424 | 0 | 0 |
T23 | 45061 | 44991 | 0 | 0 |
T24 | 80846 | 80779 | 0 | 0 |
T33 | 63246 | 62846 | 0 | 0 |
T34 | 486048 | 485993 | 0 | 0 |
T38 | 1574 | 1514 | 0 | 0 |
T39 | 96411 | 96334 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 62298652 | 62260807 | 0 | 0 |
T1 | 796264 | 796206 | 0 | 0 |
T2 | 278131 | 278072 | 0 | 0 |
T3 | 322326 | 322147 | 0 | 0 |
T15 | 4497 | 4424 | 0 | 0 |
T23 | 45061 | 44991 | 0 | 0 |
T24 | 80846 | 80779 | 0 | 0 |
T33 | 63246 | 62846 | 0 | 0 |
T34 | 486048 | 485993 | 0 | 0 |
T38 | 1574 | 1514 | 0 | 0 |
T39 | 96411 | 96334 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |