SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.67 | 95.72 | 83.72 | 89.91 | 75.00 | 88.00 | 98.53 | 54.78 |
T304 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4006166727 | Jul 27 04:55:24 PM PDT 24 | Jul 27 04:55:25 PM PDT 24 | 972198956 ps | ||
T123 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.980929095 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:23 PM PDT 24 | 322546448 ps | ||
T305 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.69535703 | Jul 27 04:55:47 PM PDT 24 | Jul 27 04:56:01 PM PDT 24 | 5130670196 ps | ||
T306 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1535413437 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:37 PM PDT 24 | 250176320 ps | ||
T86 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.271825736 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:21 PM PDT 24 | 370624257 ps | ||
T307 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.961947336 | Jul 27 04:56:00 PM PDT 24 | Jul 27 04:56:00 PM PDT 24 | 25849607 ps | ||
T58 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3376023158 | Jul 27 04:55:12 PM PDT 24 | Jul 27 04:56:08 PM PDT 24 | 55656655734 ps | ||
T308 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2268086673 | Jul 27 04:55:29 PM PDT 24 | Jul 27 04:59:32 PM PDT 24 | 84195481407 ps | ||
T309 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2931472798 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:40 PM PDT 24 | 239942391 ps | ||
T87 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3190451995 | Jul 27 04:55:58 PM PDT 24 | Jul 27 04:56:10 PM PDT 24 | 576765623 ps | ||
T310 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.57635807 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:42 PM PDT 24 | 166078076 ps | ||
T59 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3648193427 | Jul 27 04:55:27 PM PDT 24 | Jul 27 04:56:44 PM PDT 24 | 31446607014 ps | ||
T311 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4208949681 | Jul 27 04:56:00 PM PDT 24 | Jul 27 04:56:01 PM PDT 24 | 223719725 ps | ||
T88 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2427875123 | Jul 27 04:55:15 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 3866918148 ps | ||
T312 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.258279068 | Jul 27 04:56:02 PM PDT 24 | Jul 27 04:56:08 PM PDT 24 | 242089755 ps | ||
T313 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1178927573 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:40 PM PDT 24 | 1804183365 ps | ||
T314 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1762878600 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:58:00 PM PDT 24 | 54064335245 ps | ||
T89 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1040889783 | Jul 27 04:55:55 PM PDT 24 | Jul 27 04:55:57 PM PDT 24 | 150703133 ps | ||
T315 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2133979886 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:56:28 PM PDT 24 | 5202888075 ps | ||
T316 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1422180572 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:57:04 PM PDT 24 | 33792574922 ps | ||
T160 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.334185046 | Jul 27 04:55:41 PM PDT 24 | Jul 27 04:56:00 PM PDT 24 | 2379828681 ps | ||
T317 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2586906173 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:36 PM PDT 24 | 174347309 ps | ||
T318 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1033356368 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:23 PM PDT 24 | 472243239 ps | ||
T319 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1512898973 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 321952109 ps | ||
T95 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2200797113 | Jul 27 04:55:44 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 672339316 ps | ||
T320 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2842287643 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 111483607 ps | ||
T124 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3784052447 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 5787473501 ps | ||
T125 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2293247480 | Jul 27 04:55:42 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 153556910 ps | ||
T167 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2098004607 | Jul 27 04:56:02 PM PDT 24 | Jul 27 04:56:11 PM PDT 24 | 596351246 ps | ||
T321 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3318070305 | Jul 27 04:55:35 PM PDT 24 | Jul 27 04:55:39 PM PDT 24 | 5074063555 ps | ||
T322 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.358206540 | Jul 27 04:55:47 PM PDT 24 | Jul 27 04:55:52 PM PDT 24 | 2311328567 ps | ||
T126 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2605479853 | Jul 27 04:55:41 PM PDT 24 | Jul 27 04:55:44 PM PDT 24 | 344304063 ps | ||
T323 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4085076061 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:04 PM PDT 24 | 2866930107 ps | ||
T324 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1916497433 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:39 PM PDT 24 | 166055276 ps | ||
T96 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1455700877 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:26 PM PDT 24 | 182811267 ps | ||
T127 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1328059460 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:40 PM PDT 24 | 227359917 ps | ||
T325 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2677086820 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:56:04 PM PDT 24 | 476353045 ps | ||
T170 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.539172200 | Jul 27 04:55:31 PM PDT 24 | Jul 27 04:56:18 PM PDT 24 | 13813648544 ps | ||
T326 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2745531115 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 169991803 ps | ||
T163 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1317252424 | Jul 27 04:55:35 PM PDT 24 | Jul 27 04:55:59 PM PDT 24 | 9916692525 ps | ||
T327 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2587413466 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:12 PM PDT 24 | 7381632660 ps | ||
T97 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2623466877 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 424614999 ps | ||
T328 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.660932512 | Jul 27 04:55:56 PM PDT 24 | Jul 27 04:55:58 PM PDT 24 | 68839723 ps | ||
T157 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2471678363 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:55:58 PM PDT 24 | 1710695725 ps | ||
T329 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2773155048 | Jul 27 04:55:08 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 13738101811 ps | ||
T330 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3729924620 | Jul 27 04:55:43 PM PDT 24 | Jul 27 04:55:47 PM PDT 24 | 4724913356 ps | ||
T91 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.368893379 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:50 PM PDT 24 | 7143493249 ps | ||
T112 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2755929894 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:55:59 PM PDT 24 | 692762500 ps | ||
T113 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3771324881 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:42 PM PDT 24 | 3315194669 ps | ||
T331 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1890260215 | Jul 27 04:55:25 PM PDT 24 | Jul 27 04:55:30 PM PDT 24 | 219720923 ps | ||
T114 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.476887688 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:42 PM PDT 24 | 526240875 ps | ||
T332 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2694093704 | Jul 27 04:55:29 PM PDT 24 | Jul 27 04:55:30 PM PDT 24 | 511830507 ps | ||
T333 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3315210842 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:39 PM PDT 24 | 561523929 ps | ||
T334 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2856188992 | Jul 27 04:55:27 PM PDT 24 | Jul 27 04:55:30 PM PDT 24 | 217158290 ps | ||
T335 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2881500437 | Jul 27 04:55:18 PM PDT 24 | Jul 27 04:55:19 PM PDT 24 | 121368107 ps | ||
T336 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4026548245 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 337701180 ps | ||
T337 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1161311484 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:44 PM PDT 24 | 28735785352 ps | ||
T338 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4044664137 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:55:47 PM PDT 24 | 698882384 ps | ||
T339 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3568476770 | Jul 27 04:55:22 PM PDT 24 | Jul 27 04:55:32 PM PDT 24 | 12048947307 ps | ||
T340 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.207209743 | Jul 27 04:55:58 PM PDT 24 | Jul 27 04:56:12 PM PDT 24 | 9450850928 ps | ||
T341 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3037854742 | Jul 27 04:55:28 PM PDT 24 | Jul 27 04:55:35 PM PDT 24 | 50283356 ps | ||
T161 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3548387022 | Jul 27 04:56:03 PM PDT 24 | Jul 27 04:56:16 PM PDT 24 | 1268093217 ps | ||
T342 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2761451154 | Jul 27 04:56:06 PM PDT 24 | Jul 27 04:56:29 PM PDT 24 | 2718875587 ps | ||
T115 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.798126329 | Jul 27 04:55:41 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 405981905 ps | ||
T343 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2306866231 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:26 PM PDT 24 | 6756025709 ps | ||
T344 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1479850925 | Jul 27 04:55:17 PM PDT 24 | Jul 27 04:55:18 PM PDT 24 | 74839768 ps | ||
T345 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1690742074 | Jul 27 04:56:18 PM PDT 24 | Jul 27 04:56:24 PM PDT 24 | 3242650738 ps | ||
T98 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.850282297 | Jul 27 04:55:35 PM PDT 24 | Jul 27 04:55:37 PM PDT 24 | 181939664 ps | ||
T346 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.548062577 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:55:55 PM PDT 24 | 289762697 ps | ||
T347 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2863411611 | Jul 27 04:55:12 PM PDT 24 | Jul 27 04:56:10 PM PDT 24 | 22290875225 ps | ||
T348 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1024856994 | Jul 27 04:55:35 PM PDT 24 | Jul 27 04:55:43 PM PDT 24 | 413728087 ps | ||
T349 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2247123744 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:55:48 PM PDT 24 | 2555555284 ps | ||
T350 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.815306560 | Jul 27 04:55:09 PM PDT 24 | Jul 27 04:55:10 PM PDT 24 | 420879185 ps | ||
T351 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2161461674 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:39 PM PDT 24 | 142077012 ps | ||
T352 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.757101907 | Jul 27 04:55:31 PM PDT 24 | Jul 27 04:55:34 PM PDT 24 | 330410943 ps | ||
T106 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1986712959 | Jul 27 04:55:48 PM PDT 24 | Jul 27 04:55:50 PM PDT 24 | 205103400 ps | ||
T116 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2242646435 | Jul 27 04:56:02 PM PDT 24 | Jul 27 04:56:06 PM PDT 24 | 278154016 ps | ||
T353 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3114482312 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:56:02 PM PDT 24 | 52273039323 ps | ||
T354 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.573549765 | Jul 27 04:55:55 PM PDT 24 | Jul 27 04:55:56 PM PDT 24 | 156035738 ps | ||
T355 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2592814699 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:35 PM PDT 24 | 279059411 ps | ||
T117 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3937775438 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:05 PM PDT 24 | 980704260 ps | ||
T158 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3255261737 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:22 PM PDT 24 | 3217234284 ps | ||
T165 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4176000487 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 2610595761 ps | ||
T356 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1923730964 | Jul 27 04:55:49 PM PDT 24 | Jul 27 04:55:50 PM PDT 24 | 441751649 ps | ||
T357 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3648041015 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 12178487144 ps | ||
T358 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2051511269 | Jul 27 04:55:24 PM PDT 24 | Jul 27 04:55:25 PM PDT 24 | 229773786 ps | ||
T359 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3630189403 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 7964264785 ps | ||
T107 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1549168612 | Jul 27 04:55:23 PM PDT 24 | Jul 27 04:56:39 PM PDT 24 | 3545780229 ps | ||
T360 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.121343034 | Jul 27 04:56:14 PM PDT 24 | Jul 27 04:56:21 PM PDT 24 | 4406192493 ps | ||
T159 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1300250579 | Jul 27 04:55:32 PM PDT 24 | Jul 27 04:55:43 PM PDT 24 | 2064046074 ps | ||
T162 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.794483920 | Jul 27 04:55:11 PM PDT 24 | Jul 27 04:55:22 PM PDT 24 | 3513246853 ps | ||
T361 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.711910712 | Jul 27 04:55:47 PM PDT 24 | Jul 27 04:55:52 PM PDT 24 | 2865715277 ps | ||
T362 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2701957912 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 239839474 ps | ||
T99 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2898764415 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:22 PM PDT 24 | 335423951 ps | ||
T363 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.549255355 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:55:50 PM PDT 24 | 582640406 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1180831145 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:56:27 PM PDT 24 | 7587153668 ps | ||
T364 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3490187947 | Jul 27 04:55:55 PM PDT 24 | Jul 27 04:56:21 PM PDT 24 | 37752704691 ps | ||
T365 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3024253476 | Jul 27 04:55:42 PM PDT 24 | Jul 27 04:55:43 PM PDT 24 | 258947767 ps | ||
T92 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2659807527 | Jul 27 04:56:00 PM PDT 24 | Jul 27 04:56:03 PM PDT 24 | 2692273856 ps | ||
T109 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2151117056 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:55:59 PM PDT 24 | 593050320 ps | ||
T366 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4246391873 | Jul 27 04:55:43 PM PDT 24 | Jul 27 04:56:01 PM PDT 24 | 11161799000 ps | ||
T367 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1258229422 | Jul 27 04:55:15 PM PDT 24 | Jul 27 04:55:18 PM PDT 24 | 126288361 ps | ||
T164 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.100632256 | Jul 27 04:55:30 PM PDT 24 | Jul 27 04:55:53 PM PDT 24 | 6488466392 ps | ||
T368 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2438657367 | Jul 27 04:56:03 PM PDT 24 | Jul 27 04:56:08 PM PDT 24 | 556652833 ps | ||
T118 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1715807481 | Jul 27 04:55:59 PM PDT 24 | Jul 27 04:56:07 PM PDT 24 | 2277645605 ps | ||
T101 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2345759657 | Jul 27 04:55:27 PM PDT 24 | Jul 27 04:55:29 PM PDT 24 | 82233624 ps | ||
T369 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2856462922 | Jul 27 04:55:27 PM PDT 24 | Jul 27 04:55:27 PM PDT 24 | 93492526 ps | ||
T370 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1171078122 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 240444444 ps | ||
T371 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2127138103 | Jul 27 04:55:31 PM PDT 24 | Jul 27 04:55:35 PM PDT 24 | 107156043 ps | ||
T372 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2841972325 | Jul 27 04:55:08 PM PDT 24 | Jul 27 04:55:59 PM PDT 24 | 37676874641 ps | ||
T110 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2634027954 | Jul 27 04:55:18 PM PDT 24 | Jul 27 04:55:20 PM PDT 24 | 140286553 ps | ||
T373 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3174284395 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:55 PM PDT 24 | 5781571227 ps | ||
T374 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.888506804 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 1547915774 ps | ||
T166 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3842713277 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 6921851883 ps | ||
T375 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4011377075 | Jul 27 04:55:49 PM PDT 24 | Jul 27 04:56:02 PM PDT 24 | 11871259297 ps | ||
T376 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1695984768 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:55:58 PM PDT 24 | 190149345 ps | ||
T171 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2154552450 | Jul 27 04:55:42 PM PDT 24 | Jul 27 04:59:11 PM PDT 24 | 67799391512 ps | ||
T377 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2103475916 | Jul 27 04:55:45 PM PDT 24 | Jul 27 04:55:54 PM PDT 24 | 1613005293 ps | ||
T102 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3803676605 | Jul 27 04:55:54 PM PDT 24 | Jul 27 04:56:02 PM PDT 24 | 514878138 ps | ||
T378 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4044586797 | Jul 27 04:55:44 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 196171324 ps | ||
T379 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3375614130 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:55:40 PM PDT 24 | 194753183 ps | ||
T380 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3312462339 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:37 PM PDT 24 | 119118772 ps | ||
T381 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1409412862 | Jul 27 04:55:40 PM PDT 24 | Jul 27 04:55:44 PM PDT 24 | 1206646295 ps | ||
T382 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3916303012 | Jul 27 04:55:45 PM PDT 24 | Jul 27 04:55:47 PM PDT 24 | 200370218 ps | ||
T383 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.590595659 | Jul 27 04:55:27 PM PDT 24 | Jul 27 04:56:03 PM PDT 24 | 13255205278 ps | ||
T384 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1968895717 | Jul 27 04:55:54 PM PDT 24 | Jul 27 04:55:55 PM PDT 24 | 120949712 ps | ||
T385 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1704051820 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:42 PM PDT 24 | 7634477490 ps | ||
T103 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3948691479 | Jul 27 04:55:36 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 74806204 ps | ||
T386 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3621152409 | Jul 27 04:55:14 PM PDT 24 | Jul 27 04:55:15 PM PDT 24 | 27993146 ps | ||
T387 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3840274094 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:05 PM PDT 24 | 483598840 ps | ||
T388 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.71119432 | Jul 27 04:55:40 PM PDT 24 | Jul 27 04:55:44 PM PDT 24 | 1345294392 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1835768580 | Jul 27 04:55:18 PM PDT 24 | Jul 27 04:55:22 PM PDT 24 | 286193371 ps | ||
T390 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1252233995 | Jul 27 04:55:33 PM PDT 24 | Jul 27 04:55:37 PM PDT 24 | 175364455 ps | ||
T391 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2910446519 | Jul 27 04:55:49 PM PDT 24 | Jul 27 04:56:12 PM PDT 24 | 22296093102 ps | ||
T392 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.671316458 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 7733979597 ps | ||
T111 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3944738681 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:56:08 PM PDT 24 | 6514303201 ps | ||
T393 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4224067978 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:55:47 PM PDT 24 | 123910031 ps | ||
T104 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2022688833 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:28 PM PDT 24 | 343857239 ps | ||
T394 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3260109116 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:56:00 PM PDT 24 | 720712174 ps | ||
T395 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1002128364 | Jul 27 04:55:54 PM PDT 24 | Jul 27 04:56:13 PM PDT 24 | 18766563599 ps | ||
T396 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2414899572 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:42 PM PDT 24 | 959308875 ps | ||
T397 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3355595618 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:56:55 PM PDT 24 | 10270971098 ps | ||
T398 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.530299363 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:56:32 PM PDT 24 | 45525245088 ps | ||
T399 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1125433370 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:20 PM PDT 24 | 53467439 ps | ||
T400 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1913560396 | Jul 27 04:55:33 PM PDT 24 | Jul 27 04:55:34 PM PDT 24 | 890597523 ps | ||
T401 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2979336336 | Jul 27 04:56:01 PM PDT 24 | Jul 27 04:56:03 PM PDT 24 | 93537768 ps | ||
T402 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1799378274 | Jul 27 04:55:44 PM PDT 24 | Jul 27 04:56:15 PM PDT 24 | 11810234373 ps | ||
T403 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2171849125 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:23 PM PDT 24 | 388780229 ps | ||
T404 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4064761640 | Jul 27 04:55:33 PM PDT 24 | Jul 27 04:55:37 PM PDT 24 | 323675665 ps | ||
T105 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.985860014 | Jul 27 04:55:23 PM PDT 24 | Jul 27 04:55:31 PM PDT 24 | 855655668 ps | ||
T405 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1862771328 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:22 PM PDT 24 | 122843185 ps | ||
T406 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2752581205 | Jul 27 04:55:43 PM PDT 24 | Jul 27 04:55:50 PM PDT 24 | 4442317527 ps | ||
T407 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1734377397 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:56:34 PM PDT 24 | 48270561055 ps | ||
T408 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3543604154 | Jul 27 04:56:02 PM PDT 24 | Jul 27 04:56:03 PM PDT 24 | 88828288 ps | ||
T93 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2930961250 | Jul 27 04:55:19 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 10809456488 ps | ||
T409 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.760132345 | Jul 27 04:55:23 PM PDT 24 | Jul 27 04:55:25 PM PDT 24 | 587279114 ps | ||
T410 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2085011891 | Jul 27 04:55:35 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 5545341374 ps | ||
T411 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1925161651 | Jul 27 04:55:44 PM PDT 24 | Jul 27 04:55:46 PM PDT 24 | 195123330 ps | ||
T412 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1667840965 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:56:18 PM PDT 24 | 62983307420 ps | ||
T108 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2786429718 | Jul 27 04:55:48 PM PDT 24 | Jul 27 04:56:19 PM PDT 24 | 3596236177 ps | ||
T413 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.284031569 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:55:53 PM PDT 24 | 3847254976 ps | ||
T414 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.315646822 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:56:24 PM PDT 24 | 15816709295 ps | ||
T415 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1852969698 | Jul 27 04:55:51 PM PDT 24 | Jul 27 04:56:16 PM PDT 24 | 3208356835 ps | ||
T416 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3809552373 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 329183841 ps | ||
T417 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2783247312 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:55:44 PM PDT 24 | 749265774 ps | ||
T418 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2654772599 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:55:54 PM PDT 24 | 282549314 ps | ||
T419 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.591067104 | Jul 27 04:55:17 PM PDT 24 | Jul 27 04:55:18 PM PDT 24 | 250512627 ps | ||
T420 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.627889759 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:36 PM PDT 24 | 209366555 ps | ||
T421 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2239948371 | Jul 27 04:55:40 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 315948616 ps | ||
T422 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1550067074 | Jul 27 04:55:39 PM PDT 24 | Jul 27 04:58:08 PM PDT 24 | 18411893633 ps | ||
T423 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.690667078 | Jul 27 04:55:40 PM PDT 24 | Jul 27 04:55:47 PM PDT 24 | 211037843 ps | ||
T424 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2472741626 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 248457356 ps | ||
T425 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3693211239 | Jul 27 04:55:49 PM PDT 24 | Jul 27 04:55:56 PM PDT 24 | 753445602 ps | ||
T426 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2502889506 | Jul 27 04:55:56 PM PDT 24 | Jul 27 04:55:58 PM PDT 24 | 119910966 ps | ||
T427 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3769708346 | Jul 27 04:55:40 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 3547070259 ps | ||
T428 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4083336662 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:21 PM PDT 24 | 402039592 ps | ||
T168 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2368279586 | Jul 27 04:55:20 PM PDT 24 | Jul 27 04:55:31 PM PDT 24 | 1134506291 ps | ||
T429 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3138192319 | Jul 27 04:55:21 PM PDT 24 | Jul 27 04:55:22 PM PDT 24 | 247372739 ps | ||
T430 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.682154903 | Jul 27 04:55:50 PM PDT 24 | Jul 27 04:56:50 PM PDT 24 | 40989582597 ps | ||
T431 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.779474574 | Jul 27 04:55:57 PM PDT 24 | Jul 27 04:56:06 PM PDT 24 | 5327064602 ps | ||
T432 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1730504771 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:40 PM PDT 24 | 414899813 ps | ||
T94 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3067991513 | Jul 27 04:55:15 PM PDT 24 | Jul 27 04:55:19 PM PDT 24 | 1583993854 ps | ||
T433 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3724760927 | Jul 27 04:55:18 PM PDT 24 | Jul 27 04:55:20 PM PDT 24 | 121267441 ps | ||
T434 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.510718823 | Jul 27 04:55:46 PM PDT 24 | Jul 27 04:57:07 PM PDT 24 | 46988120598 ps | ||
T435 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.68426135 | Jul 27 04:55:38 PM PDT 24 | Jul 27 04:56:07 PM PDT 24 | 21134897555 ps | ||
T436 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3073687174 | Jul 27 04:55:24 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 4783375318 ps | ||
T437 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2965770954 | Jul 27 04:55:45 PM PDT 24 | Jul 27 04:55:55 PM PDT 24 | 5366217637 ps | ||
T438 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3390942464 | Jul 27 04:55:44 PM PDT 24 | Jul 27 04:55:51 PM PDT 24 | 615907968 ps | ||
T439 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2574851857 | Jul 27 04:55:34 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 242427853 ps | ||
T440 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3472129042 | Jul 27 04:55:55 PM PDT 24 | Jul 27 04:56:01 PM PDT 24 | 3228172777 ps | ||
T441 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2401674913 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:41 PM PDT 24 | 2152105380 ps | ||
T442 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2628223523 | Jul 27 04:55:42 PM PDT 24 | Jul 27 04:55:45 PM PDT 24 | 93398844 ps | ||
T443 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2616089966 | Jul 27 04:55:59 PM PDT 24 | Jul 27 04:56:36 PM PDT 24 | 36841115267 ps | ||
T444 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2234304878 | Jul 27 04:55:25 PM PDT 24 | Jul 27 04:55:26 PM PDT 24 | 58348612 ps | ||
T445 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.667589133 | Jul 27 04:55:37 PM PDT 24 | Jul 27 04:55:38 PM PDT 24 | 138411247 ps |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.2922133829 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 3431544170 ps |
CPU time | 3.64 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:04 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-c075a4ad-ccfc-4b2d-99c5-1bf36b403b7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922133829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2922133829 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3862971029 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 153951235321 ps |
CPU time | 835.44 seconds |
Started | Jul 27 04:58:01 PM PDT 24 |
Finished | Jul 27 05:11:56 PM PDT 24 |
Peak memory | 236280 kb |
Host | smart-a258e9c4-1e24-4719-a699-a0fa4ff86fe7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862971029 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3862971029 |
Directory | /workspace/4.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3544151703 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 66695388738 ps |
CPU time | 58.47 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:59:18 PM PDT 24 |
Peak memory | 221488 kb |
Host | smart-3c91e929-61bc-480c-bb7b-5fedfdf664a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544151703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3544151703 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.1761035500 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 39919685 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:25 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-28cf7d62-557b-41f9-aa9f-46f22dbdebeb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761035500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1761035500 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3376023158 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 55656655734 ps |
CPU time | 55.65 seconds |
Started | Jul 27 04:55:12 PM PDT 24 |
Finished | Jul 27 04:56:08 PM PDT 24 |
Peak memory | 219444 kb |
Host | smart-ba32f2c6-e6cc-453e-9cb1-2bc2fa456278 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376023158 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3376023158 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3131512286 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1683264496 ps |
CPU time | 17.5 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:54 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-95329fdd-e2ff-4d72-9fd8-543765750e3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131512286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3 131512286 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3676480987 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 32836547459 ps |
CPU time | 52.47 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:58:44 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-26a7c2f5-ae77-41ad-aca5-c59863fb95f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676480987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3676480987 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4111433266 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 775744941523 ps |
CPU time | 796.19 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 05:11:25 PM PDT 24 |
Peak memory | 240684 kb |
Host | smart-85a8c8ef-710a-47e6-a1df-fd6d1096995f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111433266 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.4111433266 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.814622483 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 54072190114 ps |
CPU time | 132.28 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 05:00:19 PM PDT 24 |
Peak memory | 214412 kb |
Host | smart-5d5440ef-85ca-44b3-a241-1cbab995485f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=814622483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.814622483 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.174068135 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2027019444840 ps |
CPU time | 2753.96 seconds |
Started | Jul 27 04:57:54 PM PDT 24 |
Finished | Jul 27 05:43:48 PM PDT 24 |
Peak memory | 263932 kb |
Host | smart-dbc10e1f-4459-4807-acd8-2ec259376dad |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174068135 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.174068135 |
Directory | /workspace/0.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3664044010 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 758222188 ps |
CPU time | 2.18 seconds |
Started | Jul 27 04:57:52 PM PDT 24 |
Finished | Jul 27 04:57:55 PM PDT 24 |
Peak memory | 229156 kb |
Host | smart-15acb07f-37ce-45ca-9ceb-85b231f82fae |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664044010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3664044010 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.113456280 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 637150505 ps |
CPU time | 0.96 seconds |
Started | Jul 27 04:57:53 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-f1907c40-e483-4fb6-9671-958c23d03cc5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113456280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.113456280 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3128028842 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 1470863250 ps |
CPU time | 1.5 seconds |
Started | Jul 27 04:57:55 PM PDT 24 |
Finished | Jul 27 04:57:57 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-a43e81da-aaa2-4b12-a6c9-5908ccb5ecb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128028842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3128028842 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.271825736 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 370624257 ps |
CPU time | 2.19 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:21 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-9c4cf1ad-2ccd-4ec9-8eae-b9bd7d170d49 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271825736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.271825736 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1802037608 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 583391072 ps |
CPU time | 1.13 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-4b4276bd-62bf-4a0d-9f65-29b0e7607727 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802037608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1802037608 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.3547759450 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 132587035 ps |
CPU time | 0.9 seconds |
Started | Jul 27 04:57:56 PM PDT 24 |
Finished | Jul 27 04:57:57 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-aaf18f99-f141-43c3-bcf7-ff4705965f40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547759450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3547759450 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.3602955817 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 259348138 ps |
CPU time | 0.86 seconds |
Started | Jul 27 04:57:53 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-4b1f028b-1315-42bc-bb0f-53bd3f9ecb45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602955817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3602955817 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1171166504 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 17853572404 ps |
CPU time | 40.95 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:59:05 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-33fc1ac1-d859-4b8b-bd83-4390572780da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171166504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1171166504 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3255261737 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 3217234284 ps |
CPU time | 20.64 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:22 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-d5f63673-c628-439b-8e80-0dcfd4c434f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255261737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 255261737 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.3747997789 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 3986835602 ps |
CPU time | 6.96 seconds |
Started | Jul 27 04:58:11 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-3c4b19ec-7468-4a8e-8740-8fe6b07a2297 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747997789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3747997789 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1180831145 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 7587153668 ps |
CPU time | 66.88 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:56:27 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-00cf33e8-d202-41b5-b0d1-a3833b2aa482 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180831145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1180831145 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.4073130412 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 3073457526 ps |
CPU time | 3.29 seconds |
Started | Jul 27 04:57:50 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-2e9b6ace-32da-4c51-be41-6b3fcf5217c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073130412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4073130412 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.3981290495 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 82824604 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:52 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-2cfcb87b-69fd-4385-bafe-1ff1628ee895 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981290495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3981290495 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3833691671 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 8596720115 ps |
CPU time | 13.34 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:58:05 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-c602ee5e-41e9-4560-9a11-ecad6984aed6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833691671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3833691671 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2368279586 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1134506291 ps |
CPU time | 11 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:31 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-4e0a57fa-5568-4180-9f4c-714fa9349e8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368279586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2368279586 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.992518290 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 5246166280 ps |
CPU time | 21.32 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-2533c7cc-2625-417c-a58b-c24413d3682b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992518290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.992518290 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.1006363925 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 5085522669 ps |
CPU time | 8.31 seconds |
Started | Jul 27 04:58:21 PM PDT 24 |
Finished | Jul 27 04:58:29 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-fb6db86f-283f-4d33-b544-194d5986aa7a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006363925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1006363925 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4006166727 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 972198956 ps |
CPU time | 1.33 seconds |
Started | Jul 27 04:55:24 PM PDT 24 |
Finished | Jul 27 04:55:25 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-a2989f2b-307c-4c33-9475-1e518b0783b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006166727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4 006166727 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1455700877 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 182811267 ps |
CPU time | 6.67 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:26 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-da84c654-f31a-472d-8e60-8cce1bab1233 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455700877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.1455700877 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3067991513 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 1583993854 ps |
CPU time | 3.52 seconds |
Started | Jul 27 04:55:15 PM PDT 24 |
Finished | Jul 27 04:55:19 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-c5cbff58-2902-43c0-9c4f-374aee9fbed0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067991513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.3067991513 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1369710791 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 199381777 ps |
CPU time | 1.15 seconds |
Started | Jul 27 04:57:49 PM PDT 24 |
Finished | Jul 27 04:57:51 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-4e764f84-a00f-4d5f-a6b9-42c9d4456faf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369710791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1369710791 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3842713277 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 6921851883 ps |
CPU time | 31.55 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-c2b0418f-d42d-4d36-8304-6a6788ebab3e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842713277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3842713277 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2406589550 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 5282704177 ps |
CPU time | 15.98 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-6f030b46-5636-4710-abf6-dcc0e485604d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406589550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2406589550 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1232783173 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 3124164287 ps |
CPU time | 3.37 seconds |
Started | Jul 27 04:58:05 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-6bc3201d-ce24-45ac-8dc8-48ccb4ab3e0b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1232783173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.1232783173 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.2022654662 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 3704115719 ps |
CPU time | 6.47 seconds |
Started | Jul 27 04:58:26 PM PDT 24 |
Finished | Jul 27 04:58:33 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-9d73fa54-cea9-4f90-b06e-cc294cdba44a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022654662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2022654662 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.1861792190 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 3001768946 ps |
CPU time | 5.01 seconds |
Started | Jul 27 04:58:16 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-bec36331-8f53-404f-a5f1-61e3e3c8c185 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861792190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1861792190 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.850282297 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 181939664 ps |
CPU time | 2.37 seconds |
Started | Jul 27 04:55:35 PM PDT 24 |
Finished | Jul 27 04:55:37 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-3eeb6469-3922-4ef0-8ddf-7040133d0c19 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850282297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.850282297 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.4085527424 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 45340544 ps |
CPU time | 0.72 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-b35c1f4b-0e8c-4998-89bf-05af559215c3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085527424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4085527424 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1549168612 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 3545780229 ps |
CPU time | 75.94 seconds |
Started | Jul 27 04:55:23 PM PDT 24 |
Finished | Jul 27 04:56:39 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-ee09ae78-581f-47dc-b656-5c655665c7d1 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549168612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1549168612 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2427875123 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 3866918148 ps |
CPU time | 36.11 seconds |
Started | Jul 27 04:55:15 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-24d5fd05-f786-4e78-ac4e-fc9d156a25ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427875123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2427875123 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3724760927 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 121267441 ps |
CPU time | 1.79 seconds |
Started | Jul 27 04:55:18 PM PDT 24 |
Finished | Jul 27 04:55:20 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-067d7a17-fc8d-49c0-80fc-edabad7eb025 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724760927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3724760927 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2401674913 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 2152105380 ps |
CPU time | 3.95 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 219740 kb |
Host | smart-bd0c2853-dc10-4d88-beb6-1ac9befaf51a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401674913 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2401674913 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2634027954 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 140286553 ps |
CPU time | 1.64 seconds |
Started | Jul 27 04:55:18 PM PDT 24 |
Finished | Jul 27 04:55:20 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-29e132fc-2e42-44b4-9e47-3180ff4dbd5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634027954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2634027954 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2863411611 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 22290875225 ps |
CPU time | 58.28 seconds |
Started | Jul 27 04:55:12 PM PDT 24 |
Finished | Jul 27 04:56:10 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-e66a1343-63ea-4468-84bd-01b5dd5f24bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863411611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.2863411611 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2732259602 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 112845466309 ps |
CPU time | 145.78 seconds |
Started | Jul 27 04:55:06 PM PDT 24 |
Finished | Jul 27 04:57:32 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-43512c06-0096-440d-9f38-4f92f6864ff0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732259602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.2732259602 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2773155048 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 13738101811 ps |
CPU time | 37.41 seconds |
Started | Jul 27 04:55:08 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-a3ac31a6-5530-4379-8023-2ca0447a50a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773155048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2773155048 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3568476770 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 12048947307 ps |
CPU time | 9.65 seconds |
Started | Jul 27 04:55:22 PM PDT 24 |
Finished | Jul 27 04:55:32 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-a4db0d50-98b1-49f5-bbf4-9053c7096a14 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568476770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 568476770 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4083336662 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 402039592 ps |
CPU time | 1.23 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:21 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-eb5b22d8-cf71-4b68-9142-c738831ad467 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083336662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.4083336662 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2841972325 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 37676874641 ps |
CPU time | 50.8 seconds |
Started | Jul 27 04:55:08 PM PDT 24 |
Finished | Jul 27 04:55:59 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-ea8750e6-536a-4178-91e9-749744d77ece |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841972325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.2841972325 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.815306560 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 420879185 ps |
CPU time | 1.68 seconds |
Started | Jul 27 04:55:09 PM PDT 24 |
Finished | Jul 27 04:55:10 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-f5c3df4c-5ede-4707-8663-43c329379315 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815306560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _hw_reset.815306560 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.591067104 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 250512627 ps |
CPU time | 0.82 seconds |
Started | Jul 27 04:55:17 PM PDT 24 |
Finished | Jul 27 04:55:18 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-e596a5bf-a841-4a34-8b95-6c3ceaa1588c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591067104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.591067104 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3621152409 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 27993146 ps |
CPU time | 0.7 seconds |
Started | Jul 27 04:55:14 PM PDT 24 |
Finished | Jul 27 04:55:15 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-3b7c6f06-ec3d-4688-ab75-a15b33ec4db5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621152409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.3621152409 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3037854742 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 50283356 ps |
CPU time | 0.78 seconds |
Started | Jul 27 04:55:28 PM PDT 24 |
Finished | Jul 27 04:55:35 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-214b758d-9649-4d83-b6d5-a86a53b19ade |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037854742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3037854742 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1835768580 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 286193371 ps |
CPU time | 3.21 seconds |
Started | Jul 27 04:55:18 PM PDT 24 |
Finished | Jul 27 04:55:22 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-6ea5bfe5-69df-49f1-aebf-f333f32cfb24 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835768580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1835768580 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.794483920 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 3513246853 ps |
CPU time | 10.75 seconds |
Started | Jul 27 04:55:11 PM PDT 24 |
Finished | Jul 27 04:55:22 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-b2a58dc7-ef4e-4529-94d0-07eb3106ef00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794483920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.794483920 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3174284395 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 5781571227 ps |
CPU time | 35.11 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:55 PM PDT 24 |
Peak memory | 213724 kb |
Host | smart-b3ab39fe-ec89-496a-9f50-2f28564b8b91 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174284395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3174284395 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2031375586 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 99625225 ps |
CPU time | 1.57 seconds |
Started | Jul 27 04:55:43 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-430e8ef9-b179-45ac-9c16-01c74297a6f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031375586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2031375586 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2856188992 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 217158290 ps |
CPU time | 2.36 seconds |
Started | Jul 27 04:55:27 PM PDT 24 |
Finished | Jul 27 04:55:30 PM PDT 24 |
Peak memory | 221636 kb |
Host | smart-40ca2298-d4c8-467d-a67f-e788e63ae195 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856188992 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2856188992 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3948691479 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 74806204 ps |
CPU time | 1.56 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-a21b9c31-73c5-4936-8735-9eedbf7a2e5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948691479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3948691479 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1734377397 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 48270561055 ps |
CPU time | 36.69 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:56:34 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-080bd755-e697-48d7-aa3b-c23ffd997e50 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734377397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1734377397 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1762878600 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 54064335245 ps |
CPU time | 146.05 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-db4f876e-5ccc-445c-9b49-cf0586d1fc1a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762878600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.1762878600 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2414899572 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 959308875 ps |
CPU time | 3.4 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:42 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-5ff13f3b-3be1-4365-abbd-cbd0362e0060 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414899572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 414899572 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1913560396 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 890597523 ps |
CPU time | 1.17 seconds |
Started | Jul 27 04:55:33 PM PDT 24 |
Finished | Jul 27 04:55:34 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-33bce6e0-9772-48e8-a3d2-32cb902ebdb6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913560396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.1913560396 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.590595659 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 13255205278 ps |
CPU time | 35.61 seconds |
Started | Jul 27 04:55:27 PM PDT 24 |
Finished | Jul 27 04:56:03 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-d525ebec-5109-4ab0-a184-1b16c9ec9379 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590595659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.590595659 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2881500437 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 121368107 ps |
CPU time | 0.99 seconds |
Started | Jul 27 04:55:18 PM PDT 24 |
Finished | Jul 27 04:55:19 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-3b0e6f3c-a10d-4d34-b30f-acde5da8ac54 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881500437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2881500437 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1479850925 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 74839768 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:55:17 PM PDT 24 |
Finished | Jul 27 04:55:18 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-7d5bfb10-d3cd-482c-9164-54e862af62db |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479850925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1479850925 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2051511269 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 229773786 ps |
CPU time | 0.69 seconds |
Started | Jul 27 04:55:24 PM PDT 24 |
Finished | Jul 27 04:55:25 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-633a91fc-1876-4dc2-9e51-dfe3d1c7326b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051511269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2051511269 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.985860014 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 855655668 ps |
CPU time | 7.67 seconds |
Started | Jul 27 04:55:23 PM PDT 24 |
Finished | Jul 27 04:55:31 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-47c6a32f-1fff-430e-8596-ffeafd6d3fa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985860014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c sr_outstanding.985860014 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3648193427 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 31446607014 ps |
CPU time | 77.35 seconds |
Started | Jul 27 04:55:27 PM PDT 24 |
Finished | Jul 27 04:56:44 PM PDT 24 |
Peak memory | 220540 kb |
Host | smart-1f01ad71-cf22-496c-9607-42f71133f571 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648193427 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3648193427 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1033356368 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 472243239 ps |
CPU time | 2.95 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:23 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-c7d6fc32-ae8d-487f-b630-da9d89184a20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033356368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1033356368 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2293247480 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 153556910 ps |
CPU time | 2.48 seconds |
Started | Jul 27 04:55:42 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 217556 kb |
Host | smart-08672865-a45d-4f62-b750-a6677afcbf6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293247480 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2293247480 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1040889783 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 150703133 ps |
CPU time | 1.59 seconds |
Started | Jul 27 04:55:55 PM PDT 24 |
Finished | Jul 27 04:55:57 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-f99b1bf4-88fb-47de-a05d-d84c27f78bfd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040889783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1040889783 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1002128364 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 18766563599 ps |
CPU time | 18.44 seconds |
Started | Jul 27 04:55:54 PM PDT 24 |
Finished | Jul 27 04:56:13 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-6e3bf590-579d-4712-872c-030d38ea7bbe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002128364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.1002128364 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2752581205 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 4442317527 ps |
CPU time | 6.93 seconds |
Started | Jul 27 04:55:43 PM PDT 24 |
Finished | Jul 27 04:55:50 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-182b480e-4439-4c2b-8cac-569ab039a478 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752581205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2752581205 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4224067978 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 123910031 ps |
CPU time | 0.96 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:47 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-c33a6760-ce9c-4641-8242-364b06dda93f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224067978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 4224067978 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.798126329 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 405981905 ps |
CPU time | 4.3 seconds |
Started | Jul 27 04:55:41 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-cf0bd657-0a0d-454a-82f7-15c1f9217fb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798126329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_ csr_outstanding.798126329 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1328059460 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 227359917 ps |
CPU time | 3.2 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 213720 kb |
Host | smart-1f9e05e7-3bf0-490a-8bd5-dc5ba34369cc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328059460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1328059460 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2761451154 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 2718875587 ps |
CPU time | 22.99 seconds |
Started | Jul 27 04:56:06 PM PDT 24 |
Finished | Jul 27 04:56:29 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-d2106427-186b-4088-a9a8-a99d7191ecc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761451154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 761451154 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1252233995 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 175364455 ps |
CPU time | 3.74 seconds |
Started | Jul 27 04:55:33 PM PDT 24 |
Finished | Jul 27 04:55:37 PM PDT 24 |
Peak memory | 218908 kb |
Host | smart-e1254380-256e-4897-ae72-fac711196496 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252233995 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1252233995 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2472741626 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 248457356 ps |
CPU time | 2.39 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-95015e86-7f9a-4fb1-a7a5-0c62fcec1ee5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472741626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2472741626 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.961947336 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 25849607 ps |
CPU time | 0.71 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:56:00 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-da841a06-7ffd-40a3-9c10-2a0b75a38735 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961947336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.961947336 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1690742074 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 3242650738 ps |
CPU time | 5.8 seconds |
Started | Jul 27 04:56:18 PM PDT 24 |
Finished | Jul 27 04:56:24 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-d027e402-f182-46a2-952f-dd1c2555ef1a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690742074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 1690742074 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1923730964 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 441751649 ps |
CPU time | 1.09 seconds |
Started | Jul 27 04:55:49 PM PDT 24 |
Finished | Jul 27 04:55:50 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-2edc07c8-d0ef-4b3f-bea7-38fd48e2de0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923730964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 1923730964 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2574851857 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 242427853 ps |
CPU time | 6.66 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-b60693d8-0e05-40bf-a270-b13ed01f838d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574851857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2574851857 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2783247312 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 749265774 ps |
CPU time | 4.17 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-71a74692-5940-4f44-8cb3-35413844701e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783247312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2783247312 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1852969698 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 3208356835 ps |
CPU time | 24.88 seconds |
Started | Jul 27 04:55:51 PM PDT 24 |
Finished | Jul 27 04:56:16 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-922cc603-fffa-4295-b0f4-8376357c233a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852969698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1 852969698 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1409412862 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 1206646295 ps |
CPU time | 3.58 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 221236 kb |
Host | smart-7a74c4de-f043-424c-8a93-f8e57f5a29dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409412862 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1409412862 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1986712959 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 205103400 ps |
CPU time | 1.61 seconds |
Started | Jul 27 04:55:48 PM PDT 24 |
Finished | Jul 27 04:55:50 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-81dc22bf-d2c6-4b5e-9d11-72065d1faafc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986712959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1986712959 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.8261395 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 28278433683 ps |
CPU time | 75.84 seconds |
Started | Jul 27 04:55:41 PM PDT 24 |
Finished | Jul 27 04:56:57 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-ddea56e6-5141-4969-ba4a-64cced85cf18 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8261395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv _dm_jtag_dmi_csr_bit_bash.8261395 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2247123744 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 2555555284 ps |
CPU time | 8.19 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:55:48 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-da70ee34-2a33-4a64-8011-05bc609dbc9c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247123744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 2247123744 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1695984768 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 190149345 ps |
CPU time | 1.17 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:55:58 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-f2d72399-72f4-4210-b183-6d4465731abe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695984768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1695984768 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3910465666 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 621495481 ps |
CPU time | 8.39 seconds |
Started | Jul 27 04:55:43 PM PDT 24 |
Finished | Jul 27 04:55:52 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-8b154b87-ed8c-4c45-8291-a2e8f86a389e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910465666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.3910465666 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.548062577 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 289762697 ps |
CPU time | 4.82 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:55:55 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-39039ce5-29ae-4282-b6ff-ce769b9477fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548062577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.548062577 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3916303012 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 200370218 ps |
CPU time | 2.18 seconds |
Started | Jul 27 04:55:45 PM PDT 24 |
Finished | Jul 27 04:55:47 PM PDT 24 |
Peak memory | 217656 kb |
Host | smart-61f0259f-7483-42fc-89b5-c2fa47300803 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916303012 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3916303012 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1916497433 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 166055276 ps |
CPU time | 2.06 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:39 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-36e79e04-5924-4d5b-bcdf-b9e41457871c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916497433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1916497433 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1422180572 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 33792574922 ps |
CPU time | 87.78 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:57:04 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-ca22af44-b184-4f2d-9906-a61be995f381 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422180572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1422180572 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.356642420 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 4383129966 ps |
CPU time | 7.26 seconds |
Started | Jul 27 04:55:31 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-7ce73a29-3e08-4ef3-a2a7-7af2ca84aebc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356642420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.356642420 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4044664137 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 698882384 ps |
CPU time | 1.49 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:47 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-1f5fa8b6-c27a-4112-aaf4-40a3b751aac4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044664137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 4044664137 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3803676605 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 514878138 ps |
CPU time | 7.63 seconds |
Started | Jul 27 04:55:54 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-5776047f-bb29-4952-bb9a-de8d2c60ea30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803676605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.3803676605 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2701957912 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 239839474 ps |
CPU time | 2.74 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-44cb4058-e634-4e29-b80e-f8a9b0cda068 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701957912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2701957912 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.888506804 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1547915774 ps |
CPU time | 8.46 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-b54c941b-dfe0-4333-bac2-a323a4f1f2b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888506804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.888506804 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4201461962 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 218532564 ps |
CPU time | 2.66 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:43 PM PDT 24 |
Peak memory | 218392 kb |
Host | smart-f543dd72-2589-49b6-8bac-2e4b015fc16d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201461962 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4201461962 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.627889759 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 209366555 ps |
CPU time | 1.51 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:36 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-d743a5c0-f714-4b06-91bd-df7320918483 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627889759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.627889759 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4246391873 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 11161799000 ps |
CPU time | 18.4 seconds |
Started | Jul 27 04:55:43 PM PDT 24 |
Finished | Jul 27 04:56:01 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-30904ec6-cf71-4772-af95-718fb66f0731 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246391873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.4246391873 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2085011891 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 5545341374 ps |
CPU time | 2.69 seconds |
Started | Jul 27 04:55:35 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-4353eea8-7a89-44f5-a7f0-03797172422d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085011891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 2085011891 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4096101702 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 261821250 ps |
CPU time | 0.78 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:55:58 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-a04df1f2-ea3a-4220-8586-632a70363ef7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096101702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4096101702 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3190451995 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 576765623 ps |
CPU time | 6.66 seconds |
Started | Jul 27 04:55:58 PM PDT 24 |
Finished | Jul 27 04:56:10 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-9fe184fc-b631-46c5-85a0-d7e2c884ae0f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190451995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3190451995 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2161461674 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 142077012 ps |
CPU time | 3.64 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:39 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-d7b2e33c-6e12-4e5f-88b6-8564798ed6b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161461674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2161461674 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1317252424 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 9916692525 ps |
CPU time | 23.6 seconds |
Started | Jul 27 04:55:35 PM PDT 24 |
Finished | Jul 27 04:55:59 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-362b416a-901a-40cd-b9eb-617419509f2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317252424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 317252424 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.660932512 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 68839723 ps |
CPU time | 2.8 seconds |
Started | Jul 27 04:55:56 PM PDT 24 |
Finished | Jul 27 04:55:58 PM PDT 24 |
Peak memory | 219572 kb |
Host | smart-00fa9d9b-4619-4fe9-91a6-479289e1c8d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660932512 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.660932512 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1730504771 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 414899813 ps |
CPU time | 2.51 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-9f9032e2-37e7-4146-a142-b7547a5d4069 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730504771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1730504771 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3769708346 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 3547070259 ps |
CPU time | 10.8 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-6d72fcaa-5c74-4c85-b379-6ade152962b8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769708346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.3769708346 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.69535703 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 5130670196 ps |
CPU time | 13.55 seconds |
Started | Jul 27 04:55:47 PM PDT 24 |
Finished | Jul 27 04:56:01 PM PDT 24 |
Peak memory | 204148 kb |
Host | smart-73bcb371-7ebc-4f5a-afad-a14431bcc841 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69535703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.69535703 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2592814699 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 279059411 ps |
CPU time | 1.02 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:35 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-e0be1326-2df8-463f-97ae-acad910a34fe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592814699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 2592814699 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2242646435 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 278154016 ps |
CPU time | 4.1 seconds |
Started | Jul 27 04:56:02 PM PDT 24 |
Finished | Jul 27 04:56:06 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-5bac67c0-cab8-42df-9008-8da014c8fbcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242646435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2242646435 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1024856994 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 413728087 ps |
CPU time | 2.24 seconds |
Started | Jul 27 04:55:35 PM PDT 24 |
Finished | Jul 27 04:55:43 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-c80a2eee-f511-451d-8cc3-d5e6145c5eb8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024856994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1024856994 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2098004607 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 596351246 ps |
CPU time | 8.44 seconds |
Started | Jul 27 04:56:02 PM PDT 24 |
Finished | Jul 27 04:56:11 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-037ef0b7-d4e4-4dae-b410-372d3ea7c6ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098004607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 098004607 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4026548245 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 337701180 ps |
CPU time | 4.06 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 219788 kb |
Host | smart-6737ebad-908c-4849-ab8c-3eaa17a51042 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026548245 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4026548245 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2151117056 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 593050320 ps |
CPU time | 2.11 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:55:59 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-d8eab8c1-65e5-42b2-ac72-3b34cf644ab3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151117056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2151117056 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2965770954 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 5366217637 ps |
CPU time | 9.54 seconds |
Started | Jul 27 04:55:45 PM PDT 24 |
Finished | Jul 27 04:55:55 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-f81e6fe0-147e-489a-8131-de76dd9af6f7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965770954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2965770954 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4085076061 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2866930107 ps |
CPU time | 2.57 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:04 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-e1b817df-722d-46bd-a3a5-f2c18e42b974 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085076061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 4085076061 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2842287643 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 111483607 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-154bd1a4-b95c-494f-9066-1f3420857635 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842287643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2842287643 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.476887688 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 526240875 ps |
CPU time | 7.61 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:42 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-96afa16f-7c9d-45eb-b8cc-b2e52dbf1133 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476887688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_ csr_outstanding.476887688 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2438657367 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 556652833 ps |
CPU time | 4.91 seconds |
Started | Jul 27 04:56:03 PM PDT 24 |
Finished | Jul 27 04:56:08 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-89a936ea-2942-4941-9230-cba54dfdc3bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438657367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2438657367 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2605479853 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 344304063 ps |
CPU time | 2.17 seconds |
Started | Jul 27 04:55:41 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 216632 kb |
Host | smart-58f0b040-fee2-4ed4-8791-34c46ab9bc02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605479853 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2605479853 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3543604154 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 88828288 ps |
CPU time | 1.55 seconds |
Started | Jul 27 04:56:02 PM PDT 24 |
Finished | Jul 27 04:56:03 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-b47339c6-bece-442a-bb89-8bc3318be2ef |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543604154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3543604154 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3681787968 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 7600088530 ps |
CPU time | 7.07 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-8394c54b-bbec-4680-b989-c8ac12d134b5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681787968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3681787968 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1178927573 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 1804183365 ps |
CPU time | 3.39 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-01efbccc-c2be-4ef7-944b-b3d7a5297813 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178927573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 1178927573 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2677086820 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 476353045 ps |
CPU time | 1.82 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:56:04 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-def75c69-f8b0-450e-b87b-fb5960c6544b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677086820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2677086820 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.671316458 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 7733979597 ps |
CPU time | 8.84 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-aa51c35a-5d44-4908-9562-cd5ffd1e0d41 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671316458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.671316458 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2628223523 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 93398844 ps |
CPU time | 2.05 seconds |
Started | Jul 27 04:55:42 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-a18b4aa8-0970-4549-960f-fe2cc6e1d139 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628223523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2628223523 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3548387022 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1268093217 ps |
CPU time | 12.24 seconds |
Started | Jul 27 04:56:03 PM PDT 24 |
Finished | Jul 27 04:56:16 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-b23addf1-72f2-47a1-b44a-35bf06d03b06 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548387022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3 548387022 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.549255355 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 582640406 ps |
CPU time | 4.17 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:50 PM PDT 24 |
Peak memory | 221640 kb |
Host | smart-f2570ec7-f8dc-4f69-a115-36082f9d3bfe |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549255355 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.549255355 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2502889506 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 119910966 ps |
CPU time | 1.58 seconds |
Started | Jul 27 04:55:56 PM PDT 24 |
Finished | Jul 27 04:55:58 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-7971d7d8-0bb2-4db3-a002-1d9ef8ebaa32 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502889506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2502889506 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3648041015 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 12178487144 ps |
CPU time | 8.46 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-8b014c02-2aa3-459a-861f-3e61d6d224e8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648041015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.3648041015 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.711910712 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 2865715277 ps |
CPU time | 4.8 seconds |
Started | Jul 27 04:55:47 PM PDT 24 |
Finished | Jul 27 04:55:52 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-a8148a3b-6960-4a31-b4eb-d6b851d49f70 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711910712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.711910712 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3024253476 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 258947767 ps |
CPU time | 0.86 seconds |
Started | Jul 27 04:55:42 PM PDT 24 |
Finished | Jul 27 04:55:43 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-5ad7d228-5fe6-457e-aafc-4c7d1a117ab0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024253476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 3024253476 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3840274094 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 483598840 ps |
CPU time | 4.23 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:05 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-b76a702b-9d8a-4928-9b18-b23da0024e33 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840274094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3840274094 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2654772599 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 282549314 ps |
CPU time | 4.46 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:55:54 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-3ed65e73-b48b-4518-a48e-ae00138dad9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654772599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2654772599 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2471678363 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1710695725 ps |
CPU time | 12 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:58 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-2c7f7dbf-7783-42d5-8e0b-32fc9329c42c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471678363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2 471678363 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3260109116 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 720712174 ps |
CPU time | 2.29 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:56:00 PM PDT 24 |
Peak memory | 218020 kb |
Host | smart-475ed485-5df9-4e81-a7fe-fe0f24581e82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260109116 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3260109116 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2623466877 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 424614999 ps |
CPU time | 2.4 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-ca43601d-8d2d-471a-bac6-4ed6cd6cd972 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623466877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2623466877 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4011377075 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 11871259297 ps |
CPU time | 12.26 seconds |
Started | Jul 27 04:55:49 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-eea89c52-afe1-4b67-a4cb-32b520be36d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011377075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.4011377075 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.406402402 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 7367346020 ps |
CPU time | 18.92 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:56:19 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-5817bec2-2b73-461f-9444-8ec6c7a87937 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406402402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.406402402 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2239948371 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 315948616 ps |
CPU time | 0.87 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-0bde6263-4b70-475a-b843-0d0874c82aa7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239948371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2239948371 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3937775438 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 980704260 ps |
CPU time | 4.47 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:05 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-e685459a-ce85-4be2-8d53-ded92a819f2d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937775438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.3937775438 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.121343034 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 4406192493 ps |
CPU time | 7.06 seconds |
Started | Jul 27 04:56:14 PM PDT 24 |
Finished | Jul 27 04:56:21 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-4d664a0a-0ee2-43fb-8461-c56889c204db |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121343034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.121343034 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2786429718 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3596236177 ps |
CPU time | 30.65 seconds |
Started | Jul 27 04:55:48 PM PDT 24 |
Finished | Jul 27 04:56:19 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-252c0ce1-f4be-4132-a285-98aecfaa48ea |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786429718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2786429718 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2133979886 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 5202888075 ps |
CPU time | 67.09 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:56:28 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-4061af35-d408-4955-aec9-a2aa8a9e54b7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133979886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2133979886 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2345759657 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 82233624 ps |
CPU time | 1.62 seconds |
Started | Jul 27 04:55:27 PM PDT 24 |
Finished | Jul 27 04:55:29 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-57ece122-a302-4514-911a-bd8f883aa3ff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345759657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2345759657 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1535413437 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 250176320 ps |
CPU time | 2.75 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:37 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-e315c109-076b-4b26-b88c-7e866603bd16 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535413437 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1535413437 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1258229422 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 126288361 ps |
CPU time | 2.31 seconds |
Started | Jul 27 04:55:15 PM PDT 24 |
Finished | Jul 27 04:55:18 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-952ba3e4-3632-4229-8ab4-492ad1b57ce3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258229422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1258229422 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2268086673 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 84195481407 ps |
CPU time | 242.34 seconds |
Started | Jul 27 04:55:29 PM PDT 24 |
Finished | Jul 27 04:59:32 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-c7f34a5b-702b-4498-98e6-966ebc21e4bd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268086673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2268086673 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1161311484 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 28735785352 ps |
CPU time | 24.02 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-6f81945e-3a2b-4cce-930b-4b27207c18e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161311484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.1161311484 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2930961250 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 10809456488 ps |
CPU time | 27.24 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-8a9496e0-e4e0-4cba-8339-957ab1bf24eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930961250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2930961250 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3729924620 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 4724913356 ps |
CPU time | 3.56 seconds |
Started | Jul 27 04:55:43 PM PDT 24 |
Finished | Jul 27 04:55:47 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-3bd17a16-f22e-434f-a295-b128edcb75cc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729924620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 729924620 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1512898973 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 321952109 ps |
CPU time | 0.98 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-662b4be2-ad8b-4119-a747-1c04042c7ea8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512898973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1512898973 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1181500631 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 28259875730 ps |
CPU time | 20.21 seconds |
Started | Jul 27 04:55:32 PM PDT 24 |
Finished | Jul 27 04:55:52 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-4a044830-a67d-4443-855c-f039f1a440ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181500631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1181500631 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3809552373 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 329183841 ps |
CPU time | 1.55 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-9f2ff6be-a0cd-4df7-9f7c-9b877a0348ee |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809552373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3809552373 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3315210842 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 561523929 ps |
CPU time | 1.93 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:39 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-1770e5d5-0ee9-460f-92e5-0cfd3c2f067c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315210842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3 315210842 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2856462922 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 93492526 ps |
CPU time | 0.68 seconds |
Started | Jul 27 04:55:27 PM PDT 24 |
Finished | Jul 27 04:55:27 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-e98d0e99-0421-403d-9385-05939383a2e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856462922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.2856462922 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.667589133 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 138411247 ps |
CPU time | 0.69 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-38864841-466e-41f7-ae01-f1c564ac10d7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667589133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.667589133 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.779474574 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 5327064602 ps |
CPU time | 8.43 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:56:06 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-4476818b-bbb9-4efb-86ef-2762a8e2559f |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779474574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.779474574 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.57635807 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 166078076 ps |
CPU time | 3.99 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:55:42 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-08a36f26-a4c7-42db-a31b-d78cfddebd65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.57635807 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1757413808 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 14058867034 ps |
CPU time | 21 seconds |
Started | Jul 27 04:55:14 PM PDT 24 |
Finished | Jul 27 04:55:35 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-a61793f5-7f9a-4659-9b1a-b231067372e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757413808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1757413808 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1225834337 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 13485648823 ps |
CPU time | 75.28 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:57:15 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-a39f9053-6f55-405c-a5ce-ae10d3d38f89 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225834337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1225834337 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3706820782 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 40764103915 ps |
CPU time | 75.32 seconds |
Started | Jul 27 04:55:33 PM PDT 24 |
Finished | Jul 27 04:56:48 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-68f821b6-50d9-4ab5-932a-a94382042f22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706820782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3706820782 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1193111743 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 125731769 ps |
CPU time | 1.52 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:48 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-8ab4f91e-66e1-44ed-bf7c-32694d41c04a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193111743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1193111743 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1925161651 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 195123330 ps |
CPU time | 2.5 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 217140 kb |
Host | smart-5d26e3e5-d885-405c-ae2f-04d0073b79b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925161651 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1925161651 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2979336336 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 93537768 ps |
CPU time | 1.43 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:03 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-c522141c-e9cc-4501-a629-77f93d8d65e2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979336336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2979336336 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3114482312 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 52273039323 ps |
CPU time | 21.91 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-f90e1f38-8658-47ea-ac6a-b0cf9a253cb3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114482312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.3114482312 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.682154903 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 40989582597 ps |
CPU time | 59.95 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:56:50 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-49757d97-9b74-4666-9f8c-0f4eb0f99481 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682154903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r v_dm_jtag_dmi_csr_bit_bash.682154903 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2659807527 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 2692273856 ps |
CPU time | 2.79 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:56:03 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-c5f0b580-7647-47fa-9e56-dbffb0b0a8f9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659807527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2659807527 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3472129042 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 3228172777 ps |
CPU time | 5.46 seconds |
Started | Jul 27 04:55:55 PM PDT 24 |
Finished | Jul 27 04:56:01 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-993316f9-36c9-4551-9019-6f5a3f02ca66 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472129042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3 472129042 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4044586797 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 196171324 ps |
CPU time | 1.15 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-de3d58a9-4f3a-4d7d-a470-f86a6f756730 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044586797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.4044586797 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.68426135 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 21134897555 ps |
CPU time | 28.81 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:56:07 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-f56d0679-4522-43d5-85c9-9df8ad0c9c42 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68426135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_ bit_bash.68426135 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1968895717 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 120949712 ps |
CPU time | 0.85 seconds |
Started | Jul 27 04:55:54 PM PDT 24 |
Finished | Jul 27 04:55:55 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-411aed21-e374-4bcc-a227-2d37be0289f1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968895717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1968895717 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2931472798 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 239942391 ps |
CPU time | 1.27 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d3a609f0-a234-425a-ace0-f0269f069ccb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931472798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 931472798 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1862771328 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 122843185 ps |
CPU time | 0.73 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:22 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-441b5627-09ad-44b1-8e68-8cc78c9a0f6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862771328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1862771328 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.573549765 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 156035738 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:55:55 PM PDT 24 |
Finished | Jul 27 04:55:56 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-9c150efb-3410-4da1-9f3e-3ce4b64dd67a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573549765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.573549765 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2022688833 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 343857239 ps |
CPU time | 6.4 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:28 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-0a89db6e-bfc5-4bd7-b3f4-48630330e71e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022688833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.2022688833 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2154552450 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 67799391512 ps |
CPU time | 209.15 seconds |
Started | Jul 27 04:55:42 PM PDT 24 |
Finished | Jul 27 04:59:11 PM PDT 24 |
Peak memory | 223708 kb |
Host | smart-4bc57e9f-0e34-4c54-8ae2-7609d668f377 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154552450 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2154552450 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.980929095 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 322546448 ps |
CPU time | 2.33 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:23 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-39f0df8c-f164-47b4-abb8-dbd85fc7b7c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980929095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.980929095 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3944738681 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 6514303201 ps |
CPU time | 30.48 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:56:08 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-fdc6a42b-0466-4d58-b039-8074652996b5 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944738681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.3944738681 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3355595618 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 10270971098 ps |
CPU time | 64.88 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:56:55 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-7d282206-9be7-41f3-a772-ccecbdf2dbc9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355595618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3355595618 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2898764415 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 335423951 ps |
CPU time | 2.75 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:22 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-85db954d-f917-458f-a2f8-a3955edc3d30 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898764415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2898764415 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2171849125 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 388780229 ps |
CPU time | 2.25 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:23 PM PDT 24 |
Peak memory | 215644 kb |
Host | smart-3d1f9dc2-a89a-4e0b-ac86-8d34d2c83a1a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171849125 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2171849125 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.530299363 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 45525245088 ps |
CPU time | 57.42 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:56:32 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-e9f9d966-01fb-4238-acf4-12c62c18327c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530299363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _aliasing.530299363 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.315646822 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 15816709295 ps |
CPU time | 37.71 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:56:24 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-2217df00-070a-4076-b52a-ae565d18064f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315646822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r v_dm_jtag_dmi_csr_bit_bash.315646822 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.368893379 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 7143493249 ps |
CPU time | 11.31 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:50 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-6bb44fa0-e335-48d0-9e67-076df11d63bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368893379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _hw_reset.368893379 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2306866231 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 6756025709 ps |
CPU time | 6.68 seconds |
Started | Jul 27 04:55:20 PM PDT 24 |
Finished | Jul 27 04:55:26 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-722c107f-a1cc-4aac-b2d6-e809632f9463 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306866231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 306866231 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4208949681 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 223719725 ps |
CPU time | 1.2 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:56:01 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-8b13238a-8b23-462c-b24a-15d9c4f7d380 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208949681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.4208949681 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1704051820 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 7634477490 ps |
CPU time | 20.84 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:42 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-9da68819-bb5e-4650-b5cc-ea3d11ad99ac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704051820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1704051820 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1483139489 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 282131611 ps |
CPU time | 0.89 seconds |
Started | Jul 27 04:56:00 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-58efb56b-d827-470b-8827-37888b5d507f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483139489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1483139489 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3138192319 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 247372739 ps |
CPU time | 1.08 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:22 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-c1318683-c044-4c72-8eb9-47e7b1baebd9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138192319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3 138192319 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1125433370 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 53467439 ps |
CPU time | 0.7 seconds |
Started | Jul 27 04:55:19 PM PDT 24 |
Finished | Jul 27 04:55:20 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-54f3b2cf-d0ac-479a-bf4c-0e5026cb5e09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125433370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1125433370 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2234304878 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 58348612 ps |
CPU time | 0.71 seconds |
Started | Jul 27 04:55:25 PM PDT 24 |
Finished | Jul 27 04:55:26 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-64ad1492-866e-47ab-928b-a8ffb7e0150a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234304878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2234304878 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1715807481 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2277645605 ps |
CPU time | 7.81 seconds |
Started | Jul 27 04:55:59 PM PDT 24 |
Finished | Jul 27 04:56:07 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-863cb8fc-1a75-4e1b-83e1-a51234952fb7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715807481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.1715807481 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.539172200 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 13813648544 ps |
CPU time | 46.62 seconds |
Started | Jul 27 04:55:31 PM PDT 24 |
Finished | Jul 27 04:56:18 PM PDT 24 |
Peak memory | 220016 kb |
Host | smart-a947e133-f109-4458-82d2-9d311d8a309e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539172200 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.539172200 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2297171875 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 220365465 ps |
CPU time | 2.85 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:39 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-c4ced6be-f156-47be-bc30-c9f9ed261aa3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297171875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2297171875 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3784052447 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 5787473501 ps |
CPU time | 20.03 seconds |
Started | Jul 27 04:55:21 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-2bcc4471-50d1-4e7b-82e1-8ae2e0a23386 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784052447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3784052447 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4064761640 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 323675665 ps |
CPU time | 3.03 seconds |
Started | Jul 27 04:55:33 PM PDT 24 |
Finished | Jul 27 04:55:37 PM PDT 24 |
Peak memory | 217972 kb |
Host | smart-c4022600-fc10-4b71-ba20-349bcf82b7e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064761640 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4064761640 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3073687174 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 4783375318 ps |
CPU time | 13.44 seconds |
Started | Jul 27 04:55:24 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-fecc8470-ec3f-4f3c-a75f-e907a00572c0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073687174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.3073687174 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2587413466 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 7381632660 ps |
CPU time | 10.64 seconds |
Started | Jul 27 04:56:01 PM PDT 24 |
Finished | Jul 27 04:56:12 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-fc26c449-765d-4301-9b29-3806c49e1529 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587413466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2 587413466 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1171078122 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 240444444 ps |
CPU time | 0.97 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-ed25fec3-79ba-494a-a59e-85d9bd80de07 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171078122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 171078122 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3390942464 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 615907968 ps |
CPU time | 6.79 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:55:51 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-9e68893a-d05a-4406-af11-d5ee30a35cf9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390942464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3390942464 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1550067074 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 18411893633 ps |
CPU time | 149.05 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 221652 kb |
Host | smart-26e50890-8179-442b-804d-43b8b4bee10e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550067074 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1550067074 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2745531115 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 169991803 ps |
CPU time | 4.68 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-53b07343-30cd-45df-b086-a3c7801599a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745531115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2745531115 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.334185046 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 2379828681 ps |
CPU time | 19.34 seconds |
Started | Jul 27 04:55:41 PM PDT 24 |
Finished | Jul 27 04:56:00 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-d03e6452-2d24-4329-875d-7c12c56f6336 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334185046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.334185046 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.71119432 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1345294392 ps |
CPU time | 3.89 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:44 PM PDT 24 |
Peak memory | 218984 kb |
Host | smart-46516875-92e7-4e5f-a0a4-41dcb2ffb26f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71119432 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.71119432 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.760132345 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 587279114 ps |
CPU time | 2.47 seconds |
Started | Jul 27 04:55:23 PM PDT 24 |
Finished | Jul 27 04:55:25 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-ba62b720-8dd7-4c5a-b0ec-43d6ae552787 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760132345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.760132345 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1667840965 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 62983307420 ps |
CPU time | 41.37 seconds |
Started | Jul 27 04:55:37 PM PDT 24 |
Finished | Jul 27 04:56:18 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-fa591fd6-62c8-4c29-9593-7e4d7a5e6abe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667840965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1667840965 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.284031569 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 3847254976 ps |
CPU time | 7.04 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:55:53 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-52a19fbe-16b7-4f3b-be8e-e067776f5ff6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284031569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.284031569 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3312462339 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 119118772 ps |
CPU time | 0.8 seconds |
Started | Jul 27 04:55:36 PM PDT 24 |
Finished | Jul 27 04:55:37 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-93d48769-0280-4cfd-836f-257a17143007 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312462339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 312462339 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2755929894 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 692762500 ps |
CPU time | 8.04 seconds |
Started | Jul 27 04:55:50 PM PDT 24 |
Finished | Jul 27 04:55:59 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-f36540a4-f222-43e3-b54b-40fded314b0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755929894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.2755929894 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.510718823 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 46988120598 ps |
CPU time | 80.77 seconds |
Started | Jul 27 04:55:46 PM PDT 24 |
Finished | Jul 27 04:57:07 PM PDT 24 |
Peak memory | 221612 kb |
Host | smart-9bf7b0d2-25a2-43d7-98c1-d278dafd254a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510718823 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.510718823 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.258279068 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 242089755 ps |
CPU time | 5.19 seconds |
Started | Jul 27 04:56:02 PM PDT 24 |
Finished | Jul 27 04:56:08 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-aa7b1c81-873b-49a1-8d31-a4c2e54c5524 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258279068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.258279068 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.100632256 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 6488466392 ps |
CPU time | 23.36 seconds |
Started | Jul 27 04:55:30 PM PDT 24 |
Finished | Jul 27 04:55:53 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-5b6688b9-7c47-4226-8353-1e3fe7e733f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100632256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.100632256 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.859331391 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 245115641 ps |
CPU time | 4.13 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:38 PM PDT 24 |
Peak memory | 219180 kb |
Host | smart-47878663-cb09-4db2-827d-14c8aed4eda0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859331391 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.859331391 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2200797113 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 672339316 ps |
CPU time | 2.28 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:55:46 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-3805d903-d752-421a-aea6-5761fc9564e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200797113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2200797113 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2616089966 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 36841115267 ps |
CPU time | 36.15 seconds |
Started | Jul 27 04:55:59 PM PDT 24 |
Finished | Jul 27 04:56:36 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-f9872bc4-ecba-49e4-ac2e-49c693cac6ad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616089966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.2616089966 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.358206540 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 2311328567 ps |
CPU time | 4.51 seconds |
Started | Jul 27 04:55:47 PM PDT 24 |
Finished | Jul 27 04:55:52 PM PDT 24 |
Peak memory | 204212 kb |
Host | smart-4250cbd0-a090-46fd-8e6e-b8427b4f83bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358206540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.358206540 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2544709058 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 239687152 ps |
CPU time | 1.26 seconds |
Started | Jul 27 04:55:29 PM PDT 24 |
Finished | Jul 27 04:55:30 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-aab08962-9e4e-4685-810f-6210ca351b89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544709058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2 544709058 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3771324881 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 3315194669 ps |
CPU time | 8.14 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:42 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-19d6d884-3f12-461d-b850-e92a1333eef7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771324881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3771324881 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3490187947 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 37752704691 ps |
CPU time | 26.07 seconds |
Started | Jul 27 04:55:55 PM PDT 24 |
Finished | Jul 27 04:56:21 PM PDT 24 |
Peak memory | 221704 kb |
Host | smart-df4276ee-889b-448a-b912-de56d0167ea4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490187947 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3490187947 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2127138103 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 107156043 ps |
CPU time | 2.97 seconds |
Started | Jul 27 04:55:31 PM PDT 24 |
Finished | Jul 27 04:55:35 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-98082494-cf8e-4deb-ab51-271a8f73479c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127138103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2127138103 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1300250579 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 2064046074 ps |
CPU time | 10.57 seconds |
Started | Jul 27 04:55:32 PM PDT 24 |
Finished | Jul 27 04:55:43 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-ce6485b9-2b4c-44bd-aec6-3ffc33221c82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300250579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1300250579 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2474437824 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 410914614 ps |
CPU time | 2.22 seconds |
Started | Jul 27 04:55:38 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 221616 kb |
Host | smart-6c27af22-f1d4-4af5-9f49-e1179a28ffe1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474437824 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2474437824 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3876315737 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 96147745 ps |
CPU time | 2.28 seconds |
Started | Jul 27 04:55:56 PM PDT 24 |
Finished | Jul 27 04:55:59 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-a12d6d54-6068-448e-825d-32c3c9c3cca2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876315737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3876315737 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3630189403 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 7964264785 ps |
CPU time | 7.68 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:41 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-06a6512b-0dc6-4563-8875-2bd71aeaf981 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630189403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.3630189403 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1799378274 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 11810234373 ps |
CPU time | 31.31 seconds |
Started | Jul 27 04:55:44 PM PDT 24 |
Finished | Jul 27 04:56:15 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-f547faff-77e1-4e77-b10b-a4eff3a9d8a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799378274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 799378274 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2586906173 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 174347309 ps |
CPU time | 1.22 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:36 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-6a02fe00-1693-4650-b8cb-5f617c016858 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586906173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 586906173 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.690667078 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 211037843 ps |
CPU time | 6.64 seconds |
Started | Jul 27 04:55:40 PM PDT 24 |
Finished | Jul 27 04:55:47 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-7450cf67-b93b-4283-b3ea-c05b08978243 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690667078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c sr_outstanding.690667078 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.757101907 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 330410943 ps |
CPU time | 3 seconds |
Started | Jul 27 04:55:31 PM PDT 24 |
Finished | Jul 27 04:55:34 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-bcbdcc49-5a1c-4003-8cfa-cab2eefb9fd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757101907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.757101907 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4176000487 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2610595761 ps |
CPU time | 10.98 seconds |
Started | Jul 27 04:55:34 PM PDT 24 |
Finished | Jul 27 04:55:45 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-f35c87e0-3f81-47fb-822c-0ea51f6b1ac5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176000487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4176000487 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.507207448 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 355625519 ps |
CPU time | 4.36 seconds |
Started | Jul 27 04:55:57 PM PDT 24 |
Finished | Jul 27 04:56:02 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-bbf9e209-826a-48a9-abb9-89e28a673463 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507207448 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.507207448 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3375614130 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 194753183 ps |
CPU time | 1.61 seconds |
Started | Jul 27 04:55:39 PM PDT 24 |
Finished | Jul 27 04:55:40 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-90949fed-eacf-4d98-a154-b2497a4d1964 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375614130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3375614130 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.207209743 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 9450850928 ps |
CPU time | 13.65 seconds |
Started | Jul 27 04:55:58 PM PDT 24 |
Finished | Jul 27 04:56:12 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-ae65f9aa-24ab-43d6-98d3-c7a45563adbe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207209743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r v_dm_jtag_dmi_csr_bit_bash.207209743 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3318070305 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 5074063555 ps |
CPU time | 4.16 seconds |
Started | Jul 27 04:55:35 PM PDT 24 |
Finished | Jul 27 04:55:39 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-b3a32dc1-7383-4bce-a6b6-2570009ff1a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318070305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 318070305 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2694093704 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 511830507 ps |
CPU time | 0.91 seconds |
Started | Jul 27 04:55:29 PM PDT 24 |
Finished | Jul 27 04:55:30 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-743f88b0-4c2b-4c62-9bc9-67a9861a4e02 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694093704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2 694093704 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3693211239 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 753445602 ps |
CPU time | 6.7 seconds |
Started | Jul 27 04:55:49 PM PDT 24 |
Finished | Jul 27 04:55:56 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-63b7dd64-0351-4bf4-9b3e-7a6e2a88950a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693211239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.3693211239 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2910446519 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 22296093102 ps |
CPU time | 22.19 seconds |
Started | Jul 27 04:55:49 PM PDT 24 |
Finished | Jul 27 04:56:12 PM PDT 24 |
Peak memory | 221228 kb |
Host | smart-261553fe-37c0-40b4-89e6-cf84cd8403d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910446519 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2910446519 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1890260215 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 219720923 ps |
CPU time | 4.8 seconds |
Started | Jul 27 04:55:25 PM PDT 24 |
Finished | Jul 27 04:55:30 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-b196861c-72c5-43bc-96c3-46a76ec24475 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890260215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1890260215 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2103475916 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 1613005293 ps |
CPU time | 8.79 seconds |
Started | Jul 27 04:55:45 PM PDT 24 |
Finished | Jul 27 04:55:54 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-9f058cd8-78e1-4326-8059-5dac0b46fe2e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103475916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2103475916 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2880148733 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 129188519 ps |
CPU time | 1.03 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:52 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-ec208587-da37-48f9-9126-e80623078559 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880148733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2880148733 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2422863038 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 10339444708 ps |
CPU time | 19.57 seconds |
Started | Jul 27 04:57:56 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-f24f1685-50b0-49d5-8e6b-f436a753b0bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2422863038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2422863038 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1842355448 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1831524778 ps |
CPU time | 3.03 seconds |
Started | Jul 27 04:57:49 PM PDT 24 |
Finished | Jul 27 04:57:52 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-7fe92ae2-a057-4e40-87c7-ec2800ae793d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842355448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1842355448 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.4003241480 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 433917747 ps |
CPU time | 1.65 seconds |
Started | Jul 27 04:57:44 PM PDT 24 |
Finished | Jul 27 04:57:46 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-f3d20828-2d4d-425c-ab40-4c24e454af2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003241480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4003241480 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3189787536 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 203579183 ps |
CPU time | 1.23 seconds |
Started | Jul 27 04:57:55 PM PDT 24 |
Finished | Jul 27 04:57:56 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-7d5ebb8a-e55e-4e02-9fce-adb2c72b79ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189787536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3189787536 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.4044546492 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 339784431 ps |
CPU time | 1.48 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:01 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-765d5f78-6cdd-4b5c-81b0-c5330088d3d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044546492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.4044546492 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.3743432079 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 81859223 ps |
CPU time | 0.89 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 215072 kb |
Host | smart-7121b68f-f155-4dd9-8a1b-3085eec4144f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743432079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3743432079 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1437372687 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 2207196950 ps |
CPU time | 6.11 seconds |
Started | Jul 27 04:57:47 PM PDT 24 |
Finished | Jul 27 04:57:53 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-4560175a-12b2-4728-b4b7-2a4ccb33c7ab |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1437372687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.1437372687 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2835284707 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2382808709 ps |
CPU time | 7.4 seconds |
Started | Jul 27 04:57:53 PM PDT 24 |
Finished | Jul 27 04:58:01 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-4dec7012-eb52-45bd-a5cd-dbf8e26ff8ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835284707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2835284707 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.4230245678 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 232317710 ps |
CPU time | 0.86 seconds |
Started | Jul 27 04:57:52 PM PDT 24 |
Finished | Jul 27 04:57:53 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-6d9fb7db-4e47-40a4-acaf-ca6174fc1650 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230245678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4230245678 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.166411299 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 234155773 ps |
CPU time | 0.81 seconds |
Started | Jul 27 04:57:52 PM PDT 24 |
Finished | Jul 27 04:57:53 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-4a9d8736-07bb-49a2-b7ba-2548334dde94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166411299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.166411299 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3403882848 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 306413647 ps |
CPU time | 1.6 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 04:58:10 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-3e2b0121-86df-45c1-b7e3-390f5b9a61de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403882848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3403882848 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.440126332 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 1133429592 ps |
CPU time | 3.32 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-2eae14a4-bc59-498a-8901-0ed6ea3b8257 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440126332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.440126332 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4135126130 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 269733253 ps |
CPU time | 1.29 seconds |
Started | Jul 27 04:57:57 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-e47a7c91-71cb-4276-84a7-ce874717ec27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4135126130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4135126130 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4127115634 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 311215356 ps |
CPU time | 0.86 seconds |
Started | Jul 27 04:57:49 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-a78e9605-eefe-4431-b624-437c12349f1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127115634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4127115634 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3801121070 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 319367492 ps |
CPU time | 1.15 seconds |
Started | Jul 27 04:57:48 PM PDT 24 |
Finished | Jul 27 04:57:50 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-39946cb6-9820-43c1-8894-ab7e7d0dfd7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801121070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3801121070 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1336329097 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 268281989 ps |
CPU time | 0.93 seconds |
Started | Jul 27 04:57:47 PM PDT 24 |
Finished | Jul 27 04:57:48 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-90ae7439-dbb0-4ff2-930e-3d747ada6739 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336329097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1336329097 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2731174640 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1075536088 ps |
CPU time | 1.22 seconds |
Started | Jul 27 04:57:52 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-fe0577fb-d7b4-49bd-becd-f92449e52dd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731174640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2731174640 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3146895842 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 138355475 ps |
CPU time | 0.92 seconds |
Started | Jul 27 04:57:48 PM PDT 24 |
Finished | Jul 27 04:57:49 PM PDT 24 |
Peak memory | 213104 kb |
Host | smart-88030f7e-a1ee-46d7-bf74-e13a7c385007 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146895842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3146895842 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3776734025 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1626015381 ps |
CPU time | 2.73 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-9e375d2b-938c-4a89-85c0-ab0f056fa188 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776734025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3776734025 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1252321233 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 3407040724 ps |
CPU time | 3.18 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:58:02 PM PDT 24 |
Peak memory | 205436 kb |
Host | smart-ae80549c-ed79-4383-b7c5-61388eb8fbd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252321233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1252321233 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.1652598036 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 372289439 ps |
CPU time | 1.84 seconds |
Started | Jul 27 04:57:47 PM PDT 24 |
Finished | Jul 27 04:57:49 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-bfb5b1c9-9382-4ade-ab98-f8a20d07c708 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652598036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1652598036 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.2242098450 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 7778141673 ps |
CPU time | 6.77 seconds |
Started | Jul 27 04:57:43 PM PDT 24 |
Finished | Jul 27 04:57:50 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-edd4005a-8643-4e52-b998-252bfd9fac16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242098450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2242098450 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.4098261423 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 122423862 ps |
CPU time | 0.85 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-2b229269-8855-4d8a-aae0-3b1dc43cc391 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098261423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4098261423 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1881096042 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 31142655 ps |
CPU time | 0.73 seconds |
Started | Jul 27 04:57:50 PM PDT 24 |
Finished | Jul 27 04:57:51 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-9908936a-11ce-4d48-96fc-1f3ea39a2427 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881096042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1881096042 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1168044734 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 6756077392 ps |
CPU time | 17.03 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-9ef63153-5dcd-48d0-a9bb-3605310bb9b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168044734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1168044734 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2134216547 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 314386758 ps |
CPU time | 1.46 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-aa9d05fe-6be8-41e6-90e7-a7466294a0f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134216547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2134216547 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.1833755064 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 299830857 ps |
CPU time | 1.45 seconds |
Started | Jul 27 04:58:07 PM PDT 24 |
Finished | Jul 27 04:58:09 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-e34bfb93-2ca1-4528-ba98-e1ad0f3e63d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833755064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1833755064 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1098668330 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2018079181 ps |
CPU time | 3.1 seconds |
Started | Jul 27 04:58:05 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-887df142-ce63-4b72-9d65-8a492bef4c10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098668330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1098668330 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3335202218 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 350369573 ps |
CPU time | 1.19 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:06 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-eae9c986-a064-4fbc-977e-13f74ff2fa97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335202218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3335202218 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.867199695 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 224469627 ps |
CPU time | 0.81 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-2fd3588f-693c-4fe2-8bfc-acbc8311c800 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867199695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.867199695 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2124177406 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 131541699 ps |
CPU time | 1.12 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:01 PM PDT 24 |
Peak memory | 215176 kb |
Host | smart-2d979957-193f-4c19-b657-81519bade0a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124177406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2124177406 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1343785550 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1867454762 ps |
CPU time | 2.44 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-5669a82b-03e7-4a1d-8a31-229e8e589de7 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1343785550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.1343785550 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.2087225537 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 167591675 ps |
CPU time | 0.88 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-94602f4f-0480-4f3a-aaee-d464bbb971b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087225537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2087225537 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3289702126 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 739291626 ps |
CPU time | 2.81 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-1017cf4b-ec6a-4b00-b588-a2f318b520d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3289702126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3289702126 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.4063506641 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 110650297 ps |
CPU time | 0.84 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-3bf46078-d1fb-4d12-8079-7dafda8974f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063506641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4063506641 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3993033925 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 96218165 ps |
CPU time | 0.91 seconds |
Started | Jul 27 04:57:48 PM PDT 24 |
Finished | Jul 27 04:57:49 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-3811e832-ec9a-46d4-8cd8-7dacfb4f447a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993033925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3993033925 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1540647504 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 655118041 ps |
CPU time | 1.65 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-4a286eb2-14f5-4d65-a0a6-a137fc91d8ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540647504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1540647504 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1120065789 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 514318261 ps |
CPU time | 1.9 seconds |
Started | Jul 27 04:57:57 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-be6b5062-0234-4bd3-b1d0-b1af036ffa2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120065789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1120065789 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3326929230 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 666239832 ps |
CPU time | 0.85 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:05 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-d7fafe0f-07dc-4fb4-9413-2b93cd1b553c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3326929230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3326929230 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2269179249 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1391785566 ps |
CPU time | 4.72 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-6816c518-a843-4042-907f-491496731dc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269179249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2269179249 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.423416855 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1432721738 ps |
CPU time | 2.2 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-73a8f6f4-a49e-48e8-934e-4243f027178f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423416855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.423416855 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.2138674194 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 230505511 ps |
CPU time | 1.3 seconds |
Started | Jul 27 04:58:01 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 213068 kb |
Host | smart-250d5cc1-2220-42aa-a674-5055a10b280a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138674194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2138674194 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3461494558 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 377282293 ps |
CPU time | 1.29 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:52 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-a0eb4584-5b45-4034-8059-66a324183ecd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461494558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3461494558 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.4240500970 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 788028246 ps |
CPU time | 1.99 seconds |
Started | Jul 27 04:57:50 PM PDT 24 |
Finished | Jul 27 04:57:52 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-20abf850-6113-4b4a-a111-ee7c6cd168d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240500970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4240500970 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.4119220549 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 747767382 ps |
CPU time | 1.37 seconds |
Started | Jul 27 04:57:53 PM PDT 24 |
Finished | Jul 27 04:57:55 PM PDT 24 |
Peak memory | 229432 kb |
Host | smart-d71341f8-3c83-4e9b-b076-a1c16a8e5887 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119220549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4119220549 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.3204150292 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 4273779228 ps |
CPU time | 6.55 seconds |
Started | Jul 27 04:57:57 PM PDT 24 |
Finished | Jul 27 04:58:04 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-2272e773-1b3d-49a5-b653-6948d41d2f50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204150292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3204150292 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.641310646 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 3910073923 ps |
CPU time | 7.72 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-536a6def-7d33-44f6-934d-c591b543f909 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641310646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.641310646 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1555500952 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 195333393914 ps |
CPU time | 432.77 seconds |
Started | Jul 27 04:57:50 PM PDT 24 |
Finished | Jul 27 05:05:03 PM PDT 24 |
Peak memory | 229888 kb |
Host | smart-59d07a74-ddd6-4a48-8875-251620ce6321 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555500952 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1555500952 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3629051492 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2157831195 ps |
CPU time | 2.54 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:20 PM PDT 24 |
Peak memory | 214168 kb |
Host | smart-73108e2b-605a-4bfa-9c0a-1765affe0b4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629051492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3629051492 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2195577059 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 11987625160 ps |
CPU time | 18.35 seconds |
Started | Jul 27 04:58:11 PM PDT 24 |
Finished | Jul 27 04:58:30 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-dd941bec-192a-435d-9391-e077715d6134 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195577059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2195577059 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.881538096 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2954478721 ps |
CPU time | 9.46 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:58:01 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-cbc9bda4-4950-4054-b44c-41f9a0f1dd82 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=881538096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t l_access.881538096 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.2392139465 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1355801356 ps |
CPU time | 1.99 seconds |
Started | Jul 27 04:57:49 PM PDT 24 |
Finished | Jul 27 04:57:57 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-743ad110-bd7e-44eb-bba9-d38b5a0a286a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392139465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2392139465 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.1481806827 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 8065409152 ps |
CPU time | 12.05 seconds |
Started | Jul 27 04:58:15 PM PDT 24 |
Finished | Jul 27 04:58:27 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-641076e4-f18e-40f8-a556-1b7117d4fd1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481806827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1481806827 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1882262795 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 51179286 ps |
CPU time | 0.77 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:14 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-31d4df7b-5022-4014-ab5b-e97c9c259e10 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882262795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1882262795 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2217479139 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 988801984 ps |
CPU time | 3.64 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-1e89826e-f46d-4e01-a948-a1811012a984 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217479139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2217479139 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.821766224 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 8129725451 ps |
CPU time | 11.03 seconds |
Started | Jul 27 04:58:03 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-7d1deddc-613a-43a5-9569-c3b3cf8ef684 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821766224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.821766224 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2081935547 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 2714509353 ps |
CPU time | 3.04 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:22 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-7e01405d-9a40-4fe8-b5e3-e8b9b44b4526 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081935547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2081935547 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1444932591 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 127405641 ps |
CPU time | 0.77 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:25 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-64c75add-1e47-4c3a-9715-91812a84b5bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444932591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1444932591 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.108293804 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 62749917368 ps |
CPU time | 31.3 seconds |
Started | Jul 27 04:58:27 PM PDT 24 |
Finished | Jul 27 04:58:58 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-0087cd9f-0f44-4260-a0d6-9d212af0bd1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108293804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.108293804 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1279200448 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2557259340 ps |
CPU time | 7.78 seconds |
Started | Jul 27 04:58:07 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-fd17fa6f-5585-4e4f-82bd-9b3f6c17cfb6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279200448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1279200448 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3007524889 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 1265734995 ps |
CPU time | 1.7 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-16a5bdad-2b8e-44a9-8125-4aff319d8182 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3007524889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3007524889 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.1384721438 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 2313176697 ps |
CPU time | 2.77 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-20e25366-28b3-424c-82df-97590933d9be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384721438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1384721438 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.1589772430 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 3022377171 ps |
CPU time | 3.02 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:22 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-d3d56ba6-3dec-4515-9ee2-8a685b699c29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589772430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1589772430 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.4117920481 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 123762824 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:25 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-8ef84e33-f685-4087-9952-3b5482c54eb7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117920481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4117920481 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1042094745 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 10877932913 ps |
CPU time | 32.11 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:57 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-d88c6a7c-cb99-4071-a27d-a7d72cccdd09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042094745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1042094745 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2093054004 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 12996830479 ps |
CPU time | 12.78 seconds |
Started | Jul 27 04:58:26 PM PDT 24 |
Finished | Jul 27 04:58:39 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-dc33c02f-25df-4d16-a9cc-29e77d90d093 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2093054004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.2093054004 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.497202079 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 2140143495 ps |
CPU time | 2.36 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 04:58:10 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-203ed2a5-8868-4b0d-be4b-29ee40d16924 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497202079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.497202079 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.3952927213 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 5640408721 ps |
CPU time | 9.47 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-95358d64-cb40-4082-a192-f77cf7b70afc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952927213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3952927213 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.3802264196 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 67631419 ps |
CPU time | 0.82 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:25 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-75e14e70-aa86-46c2-b673-976d928ab46c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802264196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3802264196 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2592666026 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 2602609533 ps |
CPU time | 2.32 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:14 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-53a78f3d-5ab8-4ece-bb02-b75bb8f4067a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2592666026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2592666026 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2613206366 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 6117423250 ps |
CPU time | 3.22 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:28 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-810b3e61-1301-4d03-8139-73ce2fdc3df2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2613206366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2613206366 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1903654017 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 14928037415 ps |
CPU time | 42.56 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:56 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-86d04f85-d728-4fd3-b27f-ce576eb481ca |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1903654017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.1903654017 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.837486318 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1416547686 ps |
CPU time | 1.72 seconds |
Started | Jul 27 04:58:15 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-4b7a6c75-c6ca-4f14-a835-5510469e0caa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837486318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.837486318 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.2706679624 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 167523474 ps |
CPU time | 0.72 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-ca5366ac-be03-44d0-8c06-221c486e1eea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706679624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2706679624 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1597170022 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 41471647088 ps |
CPU time | 29.23 seconds |
Started | Jul 27 04:58:25 PM PDT 24 |
Finished | Jul 27 04:58:54 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-36dc16dc-52d6-47e1-9955-5c38a375a2d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597170022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1597170022 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2012177448 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 4754545232 ps |
CPU time | 4.51 seconds |
Started | Jul 27 04:58:37 PM PDT 24 |
Finished | Jul 27 04:58:42 PM PDT 24 |
Peak memory | 215148 kb |
Host | smart-6f7c23e8-7663-41d6-a453-0d134084041d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012177448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2012177448 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1984387225 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 7091034307 ps |
CPU time | 4.03 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 221812 kb |
Host | smart-e9b16925-60ae-485f-a934-3b2153dbdd09 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1984387225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1984387225 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.2025697256 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 2544782302 ps |
CPU time | 8.52 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:22 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-75c9ef02-36f8-45b3-a2d0-8f18fbd51372 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025697256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2025697256 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.685020515 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 5347844457 ps |
CPU time | 1.86 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-f0e39097-96c8-4d9b-b876-938d60525884 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685020515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.685020515 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.310986151 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 60292763 ps |
CPU time | 0.8 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-274e8fed-1a34-4a34-bb07-dfa0585c9856 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310986151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.310986151 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.66412605 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 45896050938 ps |
CPU time | 112.89 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:59:59 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-28523bfb-9844-4aaf-8186-2a2c02347cfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66412605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.66412605 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1704501241 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 7026726737 ps |
CPU time | 2.59 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-59ae800e-cd5d-4c5b-9c35-3e6f81a16eda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704501241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1704501241 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4188843583 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 3226152487 ps |
CPU time | 5.44 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-df2beed3-4d85-4a0c-83a9-c7a6c0a5f076 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4188843583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.4188843583 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.3794234609 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 5145833637 ps |
CPU time | 15.84 seconds |
Started | Jul 27 04:58:15 PM PDT 24 |
Finished | Jul 27 04:58:31 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-d6808e0f-ea15-4050-b770-fbdea61bf20c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794234609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3794234609 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.3775617728 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 7044871893 ps |
CPU time | 3.04 seconds |
Started | Jul 27 04:58:18 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-ba637dc9-e2c3-49e2-99fa-0b632ddb2b11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775617728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3775617728 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2565183835 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 134924677 ps |
CPU time | 0.73 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-5e2e3a61-502e-4e69-8f11-105b1d43e787 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565183835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2565183835 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1218644617 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 18122835558 ps |
CPU time | 27.64 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:46 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-fd0e535d-0da8-4138-a8cc-921e4f6ef000 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218644617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1218644617 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3527375879 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 864015001 ps |
CPU time | 3.53 seconds |
Started | Jul 27 04:58:15 PM PDT 24 |
Finished | Jul 27 04:58:19 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-ae6991e0-6a48-40e1-946e-220b8212232e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527375879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3527375879 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3322291294 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 16628030500 ps |
CPU time | 22.53 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:22 PM PDT 24 |
Peak memory | 221664 kb |
Host | smart-2fcbfe0f-c5df-4884-94f6-ef71ed52a39f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3322291294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.3322291294 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.1958106836 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 12559643647 ps |
CPU time | 7.2 seconds |
Started | Jul 27 04:58:13 PM PDT 24 |
Finished | Jul 27 04:58:20 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-be2eddfd-edf9-4956-b682-ed34c7df416a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1958106836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1958106836 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.3600503235 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 2619647430 ps |
CPU time | 7.88 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-e7d303a1-fc1a-4d94-91a0-bcb1c0bec626 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600503235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3600503235 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3659396047 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 129781149 ps |
CPU time | 1 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-931b0355-0868-44d7-8db1-0e780b796923 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659396047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3659396047 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2698750686 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 26338005275 ps |
CPU time | 20.99 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:35 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-d2e30f51-03c8-4a1d-804c-179e8102a3c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698750686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2698750686 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1990290444 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2908075588 ps |
CPU time | 1.68 seconds |
Started | Jul 27 04:58:31 PM PDT 24 |
Finished | Jul 27 04:58:33 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-af813e09-0ed7-444f-8e70-2cc41e2a8e2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990290444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1990290444 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3202673990 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 931444395 ps |
CPU time | 3.57 seconds |
Started | Jul 27 04:58:28 PM PDT 24 |
Finished | Jul 27 04:58:31 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-012b9524-42b7-465f-9233-c27254563281 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3202673990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3202673990 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1450028575 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 1703583687 ps |
CPU time | 5.01 seconds |
Started | Jul 27 04:58:05 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-074dae01-e6d1-48cc-ae7d-5b41e815e976 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450028575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1450028575 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.2670649743 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 209136668 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:16 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-26e32ce9-4cd9-4bb5-8993-4d0bb5a16f41 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670649743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2670649743 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3451572835 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2272063236 ps |
CPU time | 2.05 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:14 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-92524f7b-a552-4a7e-a2a2-21f93c19dc8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451572835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3451572835 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2686963505 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 3202975175 ps |
CPU time | 3.08 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:20 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-52409914-555b-4b6c-b328-5cf0c402dbcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686963505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2686963505 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1643069722 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 5285547420 ps |
CPU time | 5.03 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:24 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-f2abaa9d-0296-4321-a1d9-d026366a5dd7 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1643069722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1643069722 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.3198013313 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 988611693 ps |
CPU time | 1.88 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-c2212b00-20dc-47a8-b877-d44f0e6cc224 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198013313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3198013313 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.2167697165 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2265736177 ps |
CPU time | 5.07 seconds |
Started | Jul 27 04:58:11 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-8e760d69-ec55-4749-a991-7c7b3dfbd9ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167697165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2167697165 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.4242975319 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 66692765 ps |
CPU time | 0.69 seconds |
Started | Jul 27 04:58:00 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-2ba70e99-ea96-4f7a-8b7d-9b4e2397b292 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242975319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4242975319 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1147873297 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 12827646221 ps |
CPU time | 35.21 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:39 PM PDT 24 |
Peak memory | 215096 kb |
Host | smart-d9246a6d-6a6f-4b54-82c4-ca84b341829d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147873297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1147873297 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2502492383 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 1818127017 ps |
CPU time | 3.59 seconds |
Started | Jul 27 04:57:53 PM PDT 24 |
Finished | Jul 27 04:57:56 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-e2e1e5a8-4283-4cbb-9e80-56f85459d5da |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2502492383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.2502492383 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2852678805 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 263261921 ps |
CPU time | 0.76 seconds |
Started | Jul 27 04:58:27 PM PDT 24 |
Finished | Jul 27 04:58:28 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-fe45729b-3149-441c-b9a2-bd9c985ed70d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852678805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2852678805 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2135305919 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 7519159416 ps |
CPU time | 11.4 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:58:10 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-eb811933-2087-4b32-9ee7-d5662ffd8df8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135305919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2135305919 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.2756121397 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 978709702 ps |
CPU time | 1.61 seconds |
Started | Jul 27 04:58:09 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 229820 kb |
Host | smart-adb37ec6-9753-41ea-a003-ab2e535c0b7a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756121397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2756121397 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2253096238 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 50995433 ps |
CPU time | 0.71 seconds |
Started | Jul 27 04:58:09 PM PDT 24 |
Finished | Jul 27 04:58:10 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-3ba6acde-57f8-4d26-9639-b4dbd2972f70 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253096238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2253096238 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2546204860 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 47860487 ps |
CPU time | 0.7 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 04:58:09 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-31cd28ba-06f4-40fb-b27a-c7d0ffbbd674 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546204860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2546204860 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1045446302 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 137444122 ps |
CPU time | 1.03 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:13 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-e7acde86-2f34-4f2e-b6ca-f924e21fbd6a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045446302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1045446302 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3205121869 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 41194210 ps |
CPU time | 0.79 seconds |
Started | Jul 27 04:58:22 PM PDT 24 |
Finished | Jul 27 04:58:23 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-7f743f46-f4c1-422f-91f9-9399eac6b167 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205121869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3205121869 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.4153689913 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 5535227013 ps |
CPU time | 6.48 seconds |
Started | Jul 27 04:58:23 PM PDT 24 |
Finished | Jul 27 04:58:29 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-06225438-b8ea-41cc-86a5-e59ae64c53f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153689913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4153689913 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1294866588 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 192067514 ps |
CPU time | 0.69 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:24 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-7bd2b21b-ed5e-4483-b57a-2b5744bf575e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294866588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1294866588 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.3006854562 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 75965736 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:58:35 PM PDT 24 |
Finished | Jul 27 04:58:36 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-01fe5cdf-db0e-45a5-91cb-a833725d65c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006854562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3006854562 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.2277471551 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 3531680301 ps |
CPU time | 10.53 seconds |
Started | Jul 27 04:58:20 PM PDT 24 |
Finished | Jul 27 04:58:30 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-25d67aae-81f5-4964-8442-e6562972f1ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277471551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2277471551 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.4164928195 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 32315489 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:58:30 PM PDT 24 |
Finished | Jul 27 04:58:31 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-e42161a0-7924-42b7-b723-20fce5b55962 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164928195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4164928195 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.4068901264 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 2501809828 ps |
CPU time | 2.64 seconds |
Started | Jul 27 04:58:33 PM PDT 24 |
Finished | Jul 27 04:58:36 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-8ebd080a-97b0-4495-81a1-a615c78ee0ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068901264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4068901264 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.1567080548 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 66490812 ps |
CPU time | 0.72 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:20 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-86429f3f-27e8-4058-a375-613f81023cc2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567080548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1567080548 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2475152720 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 92597898 ps |
CPU time | 0.81 seconds |
Started | Jul 27 04:58:27 PM PDT 24 |
Finished | Jul 27 04:58:29 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-199e1ec6-e2bd-40ec-a50a-40965ee76a24 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475152720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2475152720 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.788388842 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 3766565491 ps |
CPU time | 3.93 seconds |
Started | Jul 27 04:58:22 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-07091190-1cfe-4ca0-9961-ec30ddc5bb08 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788388842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.788388842 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.3255388127 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 68361688 ps |
CPU time | 0.83 seconds |
Started | Jul 27 04:58:42 PM PDT 24 |
Finished | Jul 27 04:58:44 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-2db4c2bd-2669-493f-8580-deebd6f4a335 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255388127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3255388127 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3799850048 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 37522858 ps |
CPU time | 0.78 seconds |
Started | Jul 27 04:57:50 PM PDT 24 |
Finished | Jul 27 04:57:51 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-6e5e352e-ae19-4279-bb5e-d381d547d2b2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799850048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3799850048 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2120014119 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 4693871857 ps |
CPU time | 8.25 seconds |
Started | Jul 27 04:58:04 PM PDT 24 |
Finished | Jul 27 04:58:13 PM PDT 24 |
Peak memory | 214652 kb |
Host | smart-350423fc-95ea-42e0-ac57-686441185af2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120014119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2120014119 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1028052257 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 5943333274 ps |
CPU time | 7.13 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-17e42305-88a0-4585-8c27-e120e4ae7c2e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1028052257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.1028052257 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.2116341045 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 326161199 ps |
CPU time | 1.53 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:53 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-33da1d88-ae0a-4ab7-9de6-f5ff62de6a09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116341045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2116341045 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3501704747 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 2074852190 ps |
CPU time | 4.17 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:14 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-7c538bec-4869-44aa-aa33-d997da50d0eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501704747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3501704747 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3114710728 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 811318373 ps |
CPU time | 1.65 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 228836 kb |
Host | smart-7a009882-534e-4629-97dd-06d0d4377fe7 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114710728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3114710728 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3327972253 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 4691933254 ps |
CPU time | 12.64 seconds |
Started | Jul 27 04:57:54 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-50177a82-c946-4468-b6cc-ae2cec5b1138 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327972253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3327972253 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.1781294123 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 85992254 ps |
CPU time | 0.84 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-76ea80c9-acf1-4d54-9860-7d00976c1183 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781294123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1781294123 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1208540897 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 136782895 ps |
CPU time | 0.85 seconds |
Started | Jul 27 04:58:37 PM PDT 24 |
Finished | Jul 27 04:58:38 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-b94d9990-15cf-4faa-9ac3-558c81d1ba8b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208540897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1208540897 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.609593585 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 86833427 ps |
CPU time | 0.7 seconds |
Started | Jul 27 04:58:09 PM PDT 24 |
Finished | Jul 27 04:58:09 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-6526a5d5-7fd2-4f3d-a02f-b7fa95ee38e0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609593585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.609593585 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1835936282 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 150752201 ps |
CPU time | 0.79 seconds |
Started | Jul 27 04:58:34 PM PDT 24 |
Finished | Jul 27 04:58:35 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-42dbe18c-0f03-4f2b-b19b-ef5be87e21cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835936282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1835936282 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.439440002 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 139269271 ps |
CPU time | 0.98 seconds |
Started | Jul 27 04:58:39 PM PDT 24 |
Finished | Jul 27 04:58:40 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-a23fa73e-b451-4b5e-aa94-9d1dfa3479d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439440002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.439440002 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3247428329 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 11531910217 ps |
CPU time | 31.7 seconds |
Started | Jul 27 04:58:32 PM PDT 24 |
Finished | Jul 27 04:59:04 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-c9e4af1a-fe09-47ac-b98c-4ffbc9e90abf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247428329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3247428329 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.3427244914 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 43326515 ps |
CPU time | 0.78 seconds |
Started | Jul 27 04:58:16 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-3b438e3a-d511-4191-9947-763502132964 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427244914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3427244914 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2810510943 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 56154491 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:20 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-ec385d68-32a8-45fc-ac94-fb6e6822499f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810510943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2810510943 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.2259062081 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 6696702940 ps |
CPU time | 14.46 seconds |
Started | Jul 27 04:58:22 PM PDT 24 |
Finished | Jul 27 04:58:36 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-765a93d3-1aa2-47d6-a8bd-e55cff5108c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259062081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2259062081 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.4031385101 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 41006433 ps |
CPU time | 0.76 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-3ebbc7f9-dbd2-4ca1-8531-60a7c6505daa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031385101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4031385101 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.2784529945 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 74140744 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:40 PM PDT 24 |
Finished | Jul 27 04:58:41 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-30bfb1b1-84d7-4229-9317-3c468bd3e819 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784529945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2784529945 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.1109707318 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 53424885 ps |
CPU time | 0.81 seconds |
Started | Jul 27 04:58:34 PM PDT 24 |
Finished | Jul 27 04:58:35 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-4ccadf3d-5dce-40d9-98fe-45a278f92f86 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109707318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1109707318 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.196456276 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 3360172414 ps |
CPU time | 5.35 seconds |
Started | Jul 27 04:58:18 PM PDT 24 |
Finished | Jul 27 04:58:23 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-cc182401-af31-4029-8270-9a0acf64764e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196456276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.196456276 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.2691541814 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 66861416 ps |
CPU time | 0.75 seconds |
Started | Jul 27 04:57:58 PM PDT 24 |
Finished | Jul 27 04:57:59 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-55c52d09-f3ef-44ee-ba69-6155e57d4ee2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691541814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2691541814 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3864002135 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1661174950 ps |
CPU time | 5.49 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 213988 kb |
Host | smart-ed24d8e4-f607-4e31-ad9a-3f89bb830dd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3864002135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3864002135 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1580669463 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1903456201 ps |
CPU time | 6.37 seconds |
Started | Jul 27 04:58:02 PM PDT 24 |
Finished | Jul 27 04:58:09 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-cb2bb33f-6fbe-4dfe-b3a3-ffe466b095db |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1580669463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.1580669463 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.2524966611 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 621888352 ps |
CPU time | 1.13 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:11 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-87c6cac5-153d-47f3-a906-f20ed9374539 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524966611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2524966611 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.1604385392 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 2514927631 ps |
CPU time | 5.29 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:04 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-b5d6bf5f-60bb-45e8-8329-f73b98f13cbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604385392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1604385392 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.1359751797 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 795483777 ps |
CPU time | 1.6 seconds |
Started | Jul 27 04:58:03 PM PDT 24 |
Finished | Jul 27 04:58:04 PM PDT 24 |
Peak memory | 228784 kb |
Host | smart-9848df8f-9798-4810-8be2-0692eade6712 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359751797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1359751797 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.3857218863 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 121967256 ps |
CPU time | 0.89 seconds |
Started | Jul 27 04:58:21 PM PDT 24 |
Finished | Jul 27 04:58:22 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-eb4d54b0-93e3-4137-b165-f59036559800 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857218863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3857218863 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.3651841791 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 4785940174 ps |
CPU time | 3.76 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-767ec49f-a27d-43b1-a6ad-e5994396ee03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651841791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3651841791 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.1190483081 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 32442280 ps |
CPU time | 0.71 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:18 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-1210e803-5998-4142-9604-368e82f5cdf9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190483081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1190483081 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.769496462 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 4694869745 ps |
CPU time | 14.78 seconds |
Started | Jul 27 04:58:17 PM PDT 24 |
Finished | Jul 27 04:58:32 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-dd74de57-ae23-4feb-9991-2fb365a0b293 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769496462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.769496462 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2309687870 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 41642044 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:24 PM PDT 24 |
Finished | Jul 27 04:58:25 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-447e36a1-3480-4abb-9a6d-3b965dbed66b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309687870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2309687870 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.4289592037 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 3473672118 ps |
CPU time | 3.84 seconds |
Started | Jul 27 04:58:35 PM PDT 24 |
Finished | Jul 27 04:58:39 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-fcdb9a4b-2942-4ef8-8ae3-e2c543ca45e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289592037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4289592037 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1642410901 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 119501023 ps |
CPU time | 0.92 seconds |
Started | Jul 27 04:58:22 PM PDT 24 |
Finished | Jul 27 04:58:23 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-2b7bc1bd-9603-4441-93ca-8c4841097872 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642410901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1642410901 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3184202465 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 7599363135 ps |
CPU time | 15.08 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:29 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-f18ba688-7277-48d6-bd7a-1c60ed54884a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184202465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3184202465 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.743816607 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 58422859 ps |
CPU time | 0.73 seconds |
Started | Jul 27 04:58:38 PM PDT 24 |
Finished | Jul 27 04:58:39 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-58792188-cba6-411f-94c1-d73dfeb8b37a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743816607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.743816607 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.63450922 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 5787819542 ps |
CPU time | 8.06 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:27 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-71c6189d-65bc-47f1-8fdc-ef9aad4d1c74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63450922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.63450922 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.4176844801 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 32316165 ps |
CPU time | 0.77 seconds |
Started | Jul 27 04:58:36 PM PDT 24 |
Finished | Jul 27 04:58:37 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-ec01808a-040c-4b39-a3b0-1addc87746cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176844801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4176844801 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.2530702056 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 3435800463 ps |
CPU time | 2.87 seconds |
Started | Jul 27 04:58:22 PM PDT 24 |
Finished | Jul 27 04:58:25 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-4e2b45e3-2826-4521-9cad-bcfa007bbc49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530702056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2530702056 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2522531521 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 248352871 ps |
CPU time | 0.78 seconds |
Started | Jul 27 04:58:20 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-2c39882e-7610-44b8-81e5-9415537ae49c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522531521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2522531521 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.665765414 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 5126750030 ps |
CPU time | 8.6 seconds |
Started | Jul 27 04:58:21 PM PDT 24 |
Finished | Jul 27 04:58:35 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-924b2c5b-f790-4e13-95ad-61502e5b7894 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665765414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.665765414 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.704645507 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 66288967 ps |
CPU time | 0.83 seconds |
Started | Jul 27 04:58:16 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-90d85f85-1dfb-4bc5-94a1-cff856aa6885 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704645507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.704645507 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.162225501 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 4333792104 ps |
CPU time | 5.34 seconds |
Started | Jul 27 04:58:26 PM PDT 24 |
Finished | Jul 27 04:58:32 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-920e7dcb-edbd-4f21-8d99-a387d9c37e92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162225501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.162225501 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.278196463 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 49057301 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:58:23 PM PDT 24 |
Finished | Jul 27 04:58:24 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-f0e270a7-9fd3-4e04-abc6-334eded476e9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278196463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.278196463 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2632770263 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 2659543758 ps |
CPU time | 4.86 seconds |
Started | Jul 27 04:58:16 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-91a10a3d-1beb-4250-bc73-9ef3552ae22f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632770263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2632770263 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.815359339 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 66551262 ps |
CPU time | 0.7 seconds |
Started | Jul 27 04:58:35 PM PDT 24 |
Finished | Jul 27 04:58:36 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-43dc3a0b-eb2c-4574-9629-8cdb863f9596 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815359339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.815359339 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.397659953 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 4672016202 ps |
CPU time | 3.83 seconds |
Started | Jul 27 04:58:11 PM PDT 24 |
Finished | Jul 27 04:58:15 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-d75b867a-1279-4bdc-a6ef-8e18b82ce6d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397659953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.397659953 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.371715628 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 45745460 ps |
CPU time | 0.82 seconds |
Started | Jul 27 04:58:02 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-a6f35109-2ee6-4524-a93b-cf57dca45cef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371715628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.371715628 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1644509003 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 2540333356 ps |
CPU time | 4.58 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:16 PM PDT 24 |
Peak memory | 213652 kb |
Host | smart-b2f538e0-d191-4a2e-bec5-5341dc4c6749 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644509003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1644509003 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.156421476 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 5102546318 ps |
CPU time | 4.69 seconds |
Started | Jul 27 04:58:03 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-d25e4aa5-fc29-4b60-9f7a-b0701faf770b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156421476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.156421476 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3061530940 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 7647619691 ps |
CPU time | 7.83 seconds |
Started | Jul 27 04:57:55 PM PDT 24 |
Finished | Jul 27 04:58:03 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-1a081da7-0f79-4553-93d2-0a8f9c97644d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3061530940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.3061530940 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.1585720109 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1383232559 ps |
CPU time | 1.53 seconds |
Started | Jul 27 04:58:01 PM PDT 24 |
Finished | Jul 27 04:58:02 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-e8d32cd3-a7d3-42c6-b3f0-7fc28b6c24d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585720109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1585720109 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.1051785371 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 9131651946 ps |
CPU time | 5.6 seconds |
Started | Jul 27 04:57:55 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-9e825347-dbe0-4e90-a84e-ada61a21418b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051785371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1051785371 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.505353715 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 37261146095 ps |
CPU time | 287.45 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 05:02:46 PM PDT 24 |
Peak memory | 229888 kb |
Host | smart-437e34fa-fa27-4e0f-b34b-97e2b904ab49 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505353715 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.505353715 |
Directory | /workspace/5.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3268927042 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 37129168 ps |
CPU time | 0.74 seconds |
Started | Jul 27 04:57:59 PM PDT 24 |
Finished | Jul 27 04:58:00 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-e3c86c3f-b950-4f38-b573-b416a185c13c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268927042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3268927042 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3809135330 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2259458288 ps |
CPU time | 7.13 seconds |
Started | Jul 27 04:58:01 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-67b64433-478c-4b46-b5ac-aee10b263202 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809135330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3809135330 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.495726285 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1591226920 ps |
CPU time | 4.94 seconds |
Started | Jul 27 04:58:01 PM PDT 24 |
Finished | Jul 27 04:58:06 PM PDT 24 |
Peak memory | 221708 kb |
Host | smart-829cabc4-6432-49f0-a8a0-2559cd88d03c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495726285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.495726285 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3099186693 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 2202887011 ps |
CPU time | 3.14 seconds |
Started | Jul 27 04:58:05 PM PDT 24 |
Finished | Jul 27 04:58:09 PM PDT 24 |
Peak memory | 213604 kb |
Host | smart-54983102-9b8c-4535-8cc8-deaff6adbdd0 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3099186693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.3099186693 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2076659168 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 1866744689 ps |
CPU time | 2.57 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:08 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-52f52ee6-daaf-469a-a7cc-8a5a9a30ba20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076659168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2076659168 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.3438809064 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 10145146114 ps |
CPU time | 11.35 seconds |
Started | Jul 27 04:58:02 PM PDT 24 |
Finished | Jul 27 04:58:14 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-0b76b9ce-d390-4187-b2ef-3e55bdb27fe2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438809064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3438809064 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.980816501 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 239800414789 ps |
CPU time | 1414.5 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 05:21:41 PM PDT 24 |
Peak memory | 240784 kb |
Host | smart-558c5418-208a-47a5-91a4-4dc6382a0f5d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980816501 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.980816501 |
Directory | /workspace/6.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3157004469 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 129612066 ps |
CPU time | 0.69 seconds |
Started | Jul 27 04:58:06 PM PDT 24 |
Finished | Jul 27 04:58:07 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-a6cb5f8b-a80e-492f-abde-47a1bb421c58 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157004469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3157004469 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1004375464 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 12691991270 ps |
CPU time | 11.7 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:26 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-1f93d4cc-2206-40a9-8bbc-db83943d4809 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004375464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1004375464 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1122016082 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 1656224201 ps |
CPU time | 2.13 seconds |
Started | Jul 27 04:57:52 PM PDT 24 |
Finished | Jul 27 04:57:54 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-f33f8930-31fa-4a34-8064-489a95a5f2cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122016082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1122016082 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3251179517 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2908103140 ps |
CPU time | 2.11 seconds |
Started | Jul 27 04:58:15 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-d0cfb2be-0990-42a9-99c7-396f36c6e9b6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3251179517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.3251179517 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.2287654107 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 1356571983 ps |
CPU time | 2.63 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-5d9870ec-bacc-4e81-871a-3ce15004c391 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287654107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2287654107 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.3894291279 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 2771393907 ps |
CPU time | 8.5 seconds |
Started | Jul 27 04:58:08 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-1656dfb1-111c-43d4-bf09-41e85453788f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894291279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3894291279 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3345184647 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 302235295534 ps |
CPU time | 3513.95 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 05:56:48 PM PDT 24 |
Peak memory | 273304 kb |
Host | smart-8f4f85c1-ea65-414f-a31a-63c2f234f480 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345184647 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.3345184647 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.2739921903 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 30143385 ps |
CPU time | 0.73 seconds |
Started | Jul 27 04:58:09 PM PDT 24 |
Finished | Jul 27 04:58:10 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-d0c774f1-dfc7-4f0d-a558-f6d8bc5cedeb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739921903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2739921903 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3742841958 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 6212435575 ps |
CPU time | 6.27 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:21 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-0e757f29-16ca-4df4-b6b7-6ee1eadd2784 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742841958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3742841958 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3953428447 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2207243078 ps |
CPU time | 4.43 seconds |
Started | Jul 27 04:58:12 PM PDT 24 |
Finished | Jul 27 04:58:17 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-97820c03-da05-4c03-99b2-38d96fb32019 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953428447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3953428447 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.393204822 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 17045997032 ps |
CPU time | 51.61 seconds |
Started | Jul 27 04:58:11 PM PDT 24 |
Finished | Jul 27 04:59:03 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-1d773e33-39a9-46e8-a388-f24b02ef29c1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=393204822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl _access.393204822 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.3778002300 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 1796390240 ps |
CPU time | 4.73 seconds |
Started | Jul 27 04:57:51 PM PDT 24 |
Finished | Jul 27 04:57:56 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-8221ebec-896b-49cc-958d-5e1c9bb547c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778002300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3778002300 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.2050003351 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 4068649203 ps |
CPU time | 8.85 seconds |
Started | Jul 27 04:57:56 PM PDT 24 |
Finished | Jul 27 04:58:05 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-380bcddd-5410-4d77-af2d-01e2e1c860bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050003351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2050003351 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.663966704 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 72706477193 ps |
CPU time | 401.46 seconds |
Started | Jul 27 04:58:05 PM PDT 24 |
Finished | Jul 27 05:04:46 PM PDT 24 |
Peak memory | 235832 kb |
Host | smart-9e175a2f-81ae-407c-98ed-a3b2310689ba |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663966704 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.663966704 |
Directory | /workspace/8.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2488565903 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 13873010480 ps |
CPU time | 20.45 seconds |
Started | Jul 27 04:58:10 PM PDT 24 |
Finished | Jul 27 04:58:31 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-20687f4d-56fe-4ba4-b7ae-9dcd73a0195d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488565903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2488565903 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3290610443 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 3634249995 ps |
CPU time | 11.03 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:31 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-de01ac98-8f60-4358-92bc-f304df4066ab |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3290610443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.3290610443 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.1324573155 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 7111772374 ps |
CPU time | 8.07 seconds |
Started | Jul 27 04:58:14 PM PDT 24 |
Finished | Jul 27 04:58:23 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-5a6f3423-a73b-437c-b37d-f4f99547cc1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324573155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1324573155 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.3572499906 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 7967592622 ps |
CPU time | 13.29 seconds |
Started | Jul 27 04:58:19 PM PDT 24 |
Finished | Jul 27 04:58:33 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-fd6c6894-12cf-4adc-be4d-021703a7b62d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572499906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3572499906 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |