Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.67 95.72 83.72 89.91 75.00 88.00 98.53 54.78


Total tests in report: 445
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.22 59.22 87.32 87.32 57.66 57.66 51.93 51.93 50.00 50.00 69.00 69.00 93.48 93.48 5.15 5.15 /workspace/coverage/default/2.rv_dm_stress_all.2922133829
70.21 10.99 89.34 2.01 69.10 11.45 59.35 7.42 57.50 7.50 76.17 7.17 94.53 1.05 45.47 40.32 /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3862971029
76.40 6.19 92.66 3.32 75.31 6.21 74.69 15.34 67.50 10.00 82.33 6.17 96.00 1.47 46.32 0.86 /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3544151703
77.97 1.56 93.11 0.45 77.79 2.48 81.83 7.14 67.50 0.00 82.83 0.50 96.00 0.00 46.69 0.37 /workspace/coverage/default/9.rv_dm_alert_test.1761035500
79.22 1.25 93.16 0.05 78.07 0.28 81.83 0.00 75.00 7.50 83.33 0.50 96.21 0.21 46.94 0.25 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3376023158
80.18 0.96 93.26 0.10 79.59 1.52 83.22 1.39 75.00 0.00 83.83 0.50 96.21 0.00 50.12 3.19 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3131512286
80.86 0.68 93.26 0.00 79.86 0.28 87.53 4.31 75.00 0.00 84.00 0.17 96.21 0.00 50.12 0.00 /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3676480987
81.20 0.35 94.01 0.75 80.69 0.83 87.53 0.00 75.00 0.00 84.83 0.83 96.21 0.00 50.12 0.00 /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4111433266
81.51 0.31 94.27 0.25 81.24 0.55 87.78 0.25 75.00 0.00 85.33 0.50 96.21 0.00 50.74 0.61 /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.814622483
81.78 0.27 94.57 0.30 81.52 0.28 88.76 0.98 75.00 0.00 85.67 0.33 96.21 0.00 50.74 0.00 /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.174068135
82.02 0.24 94.57 0.00 81.93 0.41 89.66 0.90 75.00 0.00 85.67 0.00 96.32 0.11 50.98 0.25 /workspace/coverage/default/0.rv_dm_sec_cm.3664044010
82.22 0.20 95.02 0.45 82.34 0.41 89.75 0.08 75.00 0.00 86.00 0.33 96.32 0.00 51.10 0.12 /workspace/coverage/default/0.rv_dm_abstractcmd_status.113456280
82.41 0.19 95.32 0.30 82.76 0.41 89.75 0.00 75.00 0.00 86.50 0.50 96.32 0.00 51.23 0.12 /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3128028842
82.59 0.18 95.32 0.00 82.76 0.00 89.75 0.00 75.00 0.00 86.50 0.00 97.58 1.26 51.23 0.00 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.271825736
82.72 0.13 95.47 0.15 82.90 0.14 89.75 0.00 75.00 0.00 87.00 0.50 97.58 0.00 51.35 0.12 /workspace/coverage/default/0.rv_dm_cmderr_exception.1802037608
82.82 0.10 95.52 0.05 83.03 0.14 89.75 0.00 75.00 0.00 87.50 0.50 97.58 0.00 51.35 0.00 /workspace/coverage/default/1.rv_dm_rom_read_access.3547759450
82.91 0.09 95.57 0.05 83.45 0.41 89.75 0.00 75.00 0.00 87.67 0.17 97.58 0.00 51.35 0.00 /workspace/coverage/default/0.rv_dm_dmi_failed_op.3602955817
83.00 0.09 95.57 0.00 83.45 0.00 89.75 0.00 75.00 0.00 87.67 0.00 97.58 0.00 51.96 0.61 /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1171166504
83.07 0.07 95.57 0.00 83.45 0.00 89.75 0.00 75.00 0.00 87.67 0.00 97.58 0.00 52.45 0.49 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3255261737
83.14 0.07 95.57 0.00 83.45 0.00 89.75 0.00 75.00 0.00 87.67 0.00 97.58 0.00 52.94 0.49 /workspace/coverage/default/21.rv_dm_stress_all.3747997789
83.20 0.06 95.57 0.00 83.45 0.00 89.75 0.00 75.00 0.00 87.67 0.00 98.00 0.42 52.94 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1180831145
83.25 0.05 95.57 0.00 83.45 0.00 89.75 0.00 75.00 0.00 87.67 0.00 98.00 0.00 53.31 0.37 /workspace/coverage/default/0.rv_dm_stress_all.4073130412
83.30 0.05 95.62 0.05 83.59 0.14 89.75 0.00 75.00 0.00 87.83 0.17 98.00 0.00 53.31 0.00 /workspace/coverage/default/0.rv_dm_hartsel_warl.3981290495
83.34 0.04 95.62 0.00 83.59 0.00 89.91 0.16 75.00 0.00 87.83 0.00 98.00 0.00 53.43 0.12 /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3833691671
83.38 0.04 95.62 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 53.68 0.25 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2368279586
83.41 0.04 95.62 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 53.92 0.25 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.992518290
83.45 0.04 95.62 0.00 83.59 0.00 89.91 0.00 75.00 0.00 87.83 0.00 98.00 0.00 54.17 0.25 /workspace/coverage/default/20.rv_dm_stress_all.1006363925
83.48 0.03 95.67 0.05 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.17 98.00 0.00 54.17 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4006166727
83.51 0.03 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.21 0.21 54.17 0.00 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1455700877
83.54 0.03 95.67 0.00 83.59 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.21 54.17 0.00 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3067991513
83.56 0.02 95.67 0.00 83.72 0.14 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.17 0.00 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1369710791
83.57 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.29 0.12 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3842713277
83.59 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.41 0.12 /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2406589550
83.61 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.53 0.12 /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1232783173
83.63 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.66 0.12 /workspace/coverage/default/11.rv_dm_stress_all.2022654662
83.64 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.42 0.00 54.78 0.12 /workspace/coverage/default/14.rv_dm_stress_all.1861792190
83.66 0.02 95.67 0.00 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.53 0.11 54.78 0.00 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.850282297
83.67 0.01 95.72 0.05 83.72 0.00 89.91 0.00 75.00 0.00 88.00 0.00 98.53 0.00 54.78 0.00 /workspace/coverage/default/10.rv_dm_alert_test.4085527424

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1549168612
/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2427875123
/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3724760927
/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2401674913
/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2634027954
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2863411611
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2732259602
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2773155048
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3568476770
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4083336662
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2841972325
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.815306560
/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.591067104
/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3621152409
/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3037854742
/workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1835768580
/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.794483920
/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3174284395
/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2031375586
/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2856188992
/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3948691479
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1734377397
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1762878600
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2414899572
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1913560396
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.590595659
/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2881500437
/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1479850925
/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2051511269
/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.985860014
/workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3648193427
/workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1033356368
/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2293247480
/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1040889783
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1002128364
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2752581205
/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4224067978
/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.798126329
/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1328059460
/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2761451154
/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1252233995
/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2472741626
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.961947336
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1690742074
/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1923730964
/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2574851857
/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2783247312
/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1852969698
/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1409412862
/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1986712959
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.8261395
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2247123744
/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1695984768
/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3910465666
/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.548062577
/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3916303012
/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1916497433
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1422180572
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.356642420
/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4044664137
/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3803676605
/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2701957912
/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.888506804
/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4201461962
/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.627889759
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4246391873
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2085011891
/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4096101702
/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3190451995
/workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2161461674
/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1317252424
/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.660932512
/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1730504771
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3769708346
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.69535703
/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2592814699
/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2242646435
/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1024856994
/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2098004607
/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4026548245
/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2151117056
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2965770954
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4085076061
/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2842287643
/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.476887688
/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2438657367
/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2605479853
/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3543604154
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3681787968
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1178927573
/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2677086820
/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.671316458
/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2628223523
/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3548387022
/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.549255355
/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2502889506
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3648041015
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.711910712
/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3024253476
/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3840274094
/workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2654772599
/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2471678363
/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3260109116
/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2623466877
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4011377075
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.406402402
/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2239948371
/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3937775438
/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.121343034
/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2786429718
/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2133979886
/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2345759657
/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1535413437
/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1258229422
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2268086673
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1161311484
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2930961250
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3729924620
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1512898973
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1181500631
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3809552373
/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3315210842
/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2856462922
/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.667589133
/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.779474574
/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.57635807
/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1757413808
/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1225834337
/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3706820782
/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1193111743
/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1925161651
/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2979336336
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3114482312
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.682154903
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2659807527
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3472129042
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4044586797
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.68426135
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1968895717
/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2931472798
/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1862771328
/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.573549765
/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2022688833
/workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2154552450
/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.980929095
/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3944738681
/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3355595618
/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2898764415
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/workspace/coverage/default/3.rv_dm_alert_test.3799850048
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/workspace/coverage/default/30.rv_dm_alert_test.1781294123
/workspace/coverage/default/31.rv_dm_alert_test.1208540897
/workspace/coverage/default/32.rv_dm_alert_test.609593585
/workspace/coverage/default/33.rv_dm_alert_test.1835936282
/workspace/coverage/default/34.rv_dm_alert_test.439440002
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/workspace/coverage/default/4.rv_dm_alert_test.2691541814
/workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3864002135
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/workspace/coverage/default/4.rv_dm_hart_unavail.2524966611
/workspace/coverage/default/4.rv_dm_sba_tl_access.1604385392
/workspace/coverage/default/4.rv_dm_sec_cm.1359751797
/workspace/coverage/default/40.rv_dm_alert_test.3857218863
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/workspace/coverage/default/41.rv_dm_alert_test.1190483081
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/workspace/coverage/default/6.rv_dm_alert_test.3268927042
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/workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2488565903
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/workspace/coverage/default/9.rv_dm_sba_tl_access.1324573155
/workspace/coverage/default/9.rv_dm_stress_all.3572499906



Total test records in report: 445
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.rv_dm_sba_tl_access.2081935547 Jul 27 04:58:19 PM PDT 24 Jul 27 04:58:22 PM PDT 24 2714509353 ps
T2 /workspace/coverage/default/2.rv_dm_stress_all.2922133829 Jul 27 04:58:00 PM PDT 24 Jul 27 04:58:04 PM PDT 24 3431544170 ps
T3 /workspace/coverage/default/1.rv_dm_smoke.3204150292 Jul 27 04:57:57 PM PDT 24 Jul 27 04:58:04 PM PDT 24 4273779228 ps
T39 /workspace/coverage/default/39.rv_dm_alert_test.1109707318 Jul 27 04:58:34 PM PDT 24 Jul 27 04:58:35 PM PDT 24 53424885 ps
T7 /workspace/coverage/default/4.rv_dm_hart_unavail.2524966611 Jul 27 04:58:10 PM PDT 24 Jul 27 04:58:11 PM PDT 24 621888352 ps
T4 /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3461494558 Jul 27 04:57:51 PM PDT 24 Jul 27 04:57:52 PM PDT 24 377282293 ps
T40 /workspace/coverage/default/0.rv_dm_sec_cm.3664044010 Jul 27 04:57:52 PM PDT 24 Jul 27 04:57:55 PM PDT 24 758222188 ps
T41 /workspace/coverage/default/13.rv_dm_alert_test.4117920481 Jul 27 04:58:25 PM PDT 24 Jul 27 04:58:26 PM PDT 24 123762824 ps
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T21 /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.4111433266 Jul 27 04:58:08 PM PDT 24 Jul 27 05:11:25 PM PDT 24 775744941523 ps
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T27 /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3345184647 Jul 27 04:58:14 PM PDT 24 Jul 27 05:56:48 PM PDT 24 302235295534 ps
T143 /workspace/coverage/default/16.rv_dm_stress_all.3775617728 Jul 27 04:58:18 PM PDT 24 Jul 27 04:58:21 PM PDT 24 7044871893 ps
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T245 /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3322291294 Jul 27 04:57:59 PM PDT 24 Jul 27 04:58:22 PM PDT 24 16628030500 ps
T246 /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4135126130 Jul 27 04:57:57 PM PDT 24 Jul 27 04:57:59 PM PDT 24 269733253 ps
T247 /workspace/coverage/default/14.rv_dm_sba_tl_access.837486318 Jul 27 04:58:15 PM PDT 24 Jul 27 04:58:17 PM PDT 24 1416547686 ps
T153 /workspace/coverage/default/20.rv_dm_stress_all.1006363925 Jul 27 04:58:21 PM PDT 24 Jul 27 04:58:29 PM PDT 24 5085522669 ps
T55 /workspace/coverage/default/2.rv_dm_sec_cm.2756121397 Jul 27 04:58:09 PM PDT 24 Jul 27 04:58:11 PM PDT 24 978709702 ps
T248 /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1643069722 Jul 27 04:58:14 PM PDT 24 Jul 27 04:58:24 PM PDT 24 5285547420 ps
T249 /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2731174640 Jul 27 04:57:52 PM PDT 24 Jul 27 04:57:54 PM PDT 24 1075536088 ps
T38 /workspace/coverage/default/0.rv_dm_abstractcmd_status.113456280 Jul 27 04:57:53 PM PDT 24 Jul 27 04:57:54 PM PDT 24 637150505 ps
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T251 /workspace/coverage/default/6.rv_dm_sba_tl_access.2076659168 Jul 27 04:58:06 PM PDT 24 Jul 27 04:58:08 PM PDT 24 1866744689 ps
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T253 /workspace/coverage/default/5.rv_dm_alert_test.371715628 Jul 27 04:58:02 PM PDT 24 Jul 27 04:58:03 PM PDT 24 45745460 ps
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T254 /workspace/coverage/default/12.rv_dm_stress_all.1589772430 Jul 27 04:58:19 PM PDT 24 Jul 27 04:58:22 PM PDT 24 3022377171 ps
T255 /workspace/coverage/default/13.rv_dm_sba_tl_access.497202079 Jul 27 04:58:08 PM PDT 24 Jul 27 04:58:10 PM PDT 24 2140143495 ps
T256 /workspace/coverage/default/12.rv_dm_alert_test.1444932591 Jul 27 04:58:24 PM PDT 24 Jul 27 04:58:25 PM PDT 24 127405641 ps
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T258 /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1990290444 Jul 27 04:58:31 PM PDT 24 Jul 27 04:58:33 PM PDT 24 2908075588 ps
T259 /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1004375464 Jul 27 04:58:14 PM PDT 24 Jul 27 04:58:26 PM PDT 24 12691991270 ps
T260 /workspace/coverage/default/0.rv_dm_alert_test.2880148733 Jul 27 04:57:51 PM PDT 24 Jul 27 04:57:52 PM PDT 24 129188519 ps
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T265 /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2502492383 Jul 27 04:57:53 PM PDT 24 Jul 27 04:57:56 PM PDT 24 1818127017 ps
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T133 /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1171166504 Jul 27 04:58:24 PM PDT 24 Jul 27 04:59:05 PM PDT 24 17853572404 ps
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T271 /workspace/coverage/default/0.rv_dm_ndmreset_req.1336329097 Jul 27 04:57:47 PM PDT 24 Jul 27 04:57:48 PM PDT 24 268281989 ps
T272 /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3953428447 Jul 27 04:58:12 PM PDT 24 Jul 27 04:58:17 PM PDT 24 2207243078 ps
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T274 /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3809135330 Jul 27 04:58:01 PM PDT 24 Jul 27 04:58:08 PM PDT 24 2259458288 ps
T275 /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3189787536 Jul 27 04:57:55 PM PDT 24 Jul 27 04:57:56 PM PDT 24 203579183 ps
T276 /workspace/coverage/default/43.rv_dm_stress_all.3184202465 Jul 27 04:58:14 PM PDT 24 Jul 27 04:58:29 PM PDT 24 7599363135 ps
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T279 /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3451572835 Jul 27 04:58:12 PM PDT 24 Jul 27 04:58:14 PM PDT 24 2272063236 ps
T280 /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.66412605 Jul 27 04:58:06 PM PDT 24 Jul 27 04:59:59 PM PDT 24 45896050938 ps
T281 /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2488565903 Jul 27 04:58:10 PM PDT 24 Jul 27 04:58:31 PM PDT 24 13873010480 ps
T282 /workspace/coverage/default/19.rv_dm_sba_tl_access.3198013313 Jul 27 04:58:06 PM PDT 24 Jul 27 04:58:08 PM PDT 24 988611693 ps
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T284 /workspace/coverage/default/3.rv_dm_hart_unavail.2116341045 Jul 27 04:57:51 PM PDT 24 Jul 27 04:57:53 PM PDT 24 326161199 ps
T285 /workspace/coverage/default/4.rv_dm_sba_tl_access.1604385392 Jul 27 04:57:59 PM PDT 24 Jul 27 04:58:04 PM PDT 24 2514927631 ps
T286 /workspace/coverage/default/38.rv_dm_alert_test.2784529945 Jul 27 04:58:40 PM PDT 24 Jul 27 04:58:41 PM PDT 24 74140744 ps
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T50 /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.174068135 Jul 27 04:57:54 PM PDT 24 Jul 27 05:43:48 PM PDT 24 2027019444840 ps
T288 /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.423416855 Jul 27 04:58:00 PM PDT 24 Jul 27 04:58:03 PM PDT 24 1432721738 ps
T289 /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1437372687 Jul 27 04:57:47 PM PDT 24 Jul 27 04:57:53 PM PDT 24 2207196950 ps
T33 /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1369710791 Jul 27 04:57:49 PM PDT 24 Jul 27 04:57:51 PM PDT 24 199381777 ps
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T291 /workspace/coverage/default/1.rv_dm_alert_test.1881096042 Jul 27 04:57:50 PM PDT 24 Jul 27 04:57:51 PM PDT 24 31142655 ps
T70 /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.505353715 Jul 27 04:57:59 PM PDT 24 Jul 27 05:02:46 PM PDT 24 37261146095 ps
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T293 /workspace/coverage/default/42.rv_dm_alert_test.2309687870 Jul 27 04:58:24 PM PDT 24 Jul 27 04:58:25 PM PDT 24 41642044 ps
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T295 /workspace/coverage/default/33.rv_dm_alert_test.1835936282 Jul 27 04:58:34 PM PDT 24 Jul 27 04:58:35 PM PDT 24 150752201 ps
T71 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2474437824 Jul 27 04:55:38 PM PDT 24 Jul 27 04:55:40 PM PDT 24 410914614 ps
T72 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3131512286 Jul 27 04:55:37 PM PDT 24 Jul 27 04:55:54 PM PDT 24 1683264496 ps
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T297 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.507207448 Jul 27 04:55:57 PM PDT 24 Jul 27 04:56:02 PM PDT 24 355625519 ps
T169 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.859331391 Jul 27 04:55:34 PM PDT 24 Jul 27 04:55:38 PM PDT 24 245115641 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2031375586 Jul 27 04:55:43 PM PDT 24 Jul 27 04:55:44 PM PDT 24 99625225 ps
T84 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3876315737 Jul 27 04:55:56 PM PDT 24 Jul 27 04:55:59 PM PDT 24 96147745 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1757413808 Jul 27 04:55:14 PM PDT 24 Jul 27 04:55:35 PM PDT 24 14058867034 ps
T62 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1181500631 Jul 27 04:55:32 PM PDT 24 Jul 27 04:55:52 PM PDT 24 28259875730 ps
T63 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4096101702 Jul 27 04:55:57 PM PDT 24 Jul 27 04:55:58 PM PDT 24 261821250 ps
T85 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1193111743 Jul 27 04:55:46 PM PDT 24 Jul 27 04:55:48 PM PDT 24 125731769 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2732259602 Jul 27 04:55:06 PM PDT 24 Jul 27 04:57:32 PM PDT 24 112845466309 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2297171875 Jul 27 04:55:36 PM PDT 24 Jul 27 04:55:39 PM PDT 24 220365465 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1483139489 Jul 27 04:56:00 PM PDT 24 Jul 27 04:56:02 PM PDT 24 282131611 ps
T301 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.8261395 Jul 27 04:55:41 PM PDT 24 Jul 27 04:56:57 PM PDT 24 28278433683 ps
T302 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.406402402 Jul 27 04:56:00 PM PDT 24 Jul 27 04:56:19 PM PDT 24 7367346020 ps
T128 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.992518290 Jul 27 04:55:40 PM PDT 24 Jul 27 04:56:02 PM PDT 24 5246166280 ps
T303 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3681787968 Jul 27 04:55:44 PM PDT 24 Jul 27 04:55:51 PM PDT 24 7600088530 ps
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