SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.34 | 95.72 | 83.72 | 89.91 | 75.00 | 88.00 | 98.21 | 52.77 |
T295 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.873293695 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:57 PM PDT 24 | 15127701813 ps | ||
T296 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2026548191 | Jul 28 05:00:15 PM PDT 24 | Jul 28 05:00:18 PM PDT 24 | 2346736154 ps | ||
T297 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.862125221 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 96930887 ps | ||
T76 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.398609371 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:00:56 PM PDT 24 | 215117322 ps | ||
T298 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.97192714 | Jul 28 05:00:26 PM PDT 24 | Jul 28 05:00:29 PM PDT 24 | 148982078 ps | ||
T299 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3460002469 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 341839508 ps | ||
T77 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3074614638 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 117445948 ps | ||
T58 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.331486468 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 361773997 ps | ||
T78 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2507050547 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 952476270 ps | ||
T79 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1386458898 | Jul 28 05:00:48 PM PDT 24 | Jul 28 05:01:17 PM PDT 24 | 2990952765 ps | ||
T80 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2480306267 | Jul 28 05:00:55 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 787449670 ps | ||
T55 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1791405502 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:04:29 PM PDT 24 | 17704160697 ps | ||
T300 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1428603928 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:02:11 PM PDT 24 | 77252342529 ps | ||
T301 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4187812846 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:01:06 PM PDT 24 | 5365044657 ps | ||
T302 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2082733574 | Jul 28 05:00:39 PM PDT 24 | Jul 28 05:00:40 PM PDT 24 | 600188720 ps | ||
T81 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3558550899 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:27 PM PDT 24 | 701239840 ps | ||
T89 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1508465042 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 237711675 ps | ||
T113 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.512479438 | Jul 28 05:01:10 PM PDT 24 | Jul 28 05:01:14 PM PDT 24 | 577189932 ps | ||
T86 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3974386159 | Jul 28 05:00:23 PM PDT 24 | Jul 28 05:00:28 PM PDT 24 | 2546377075 ps | ||
T303 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2499804369 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 9620587163 ps | ||
T304 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4092596949 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 235935777 ps | ||
T305 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.763850040 | Jul 28 05:00:29 PM PDT 24 | Jul 28 05:00:30 PM PDT 24 | 220385044 ps | ||
T306 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2926906233 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:33 PM PDT 24 | 485982824 ps | ||
T307 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4280064502 | Jul 28 05:00:59 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 3690812987 ps | ||
T308 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2105161790 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 2938721162 ps | ||
T153 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.807029699 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 904251072 ps | ||
T90 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3595605876 | Jul 28 05:00:11 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 2648962562 ps | ||
T91 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.424723239 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:23 PM PDT 24 | 325262489 ps | ||
T106 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3003066422 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 303566270 ps | ||
T309 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4129664415 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 3307944775 ps | ||
T310 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3069144866 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 6532141799 ps | ||
T97 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1561768833 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 326204847 ps | ||
T311 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3255686359 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 401607326 ps | ||
T312 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1082315291 | Jul 28 05:00:56 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 245838183 ps | ||
T313 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1491417420 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 461117197 ps | ||
T314 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3888617588 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:00:34 PM PDT 24 | 78138030 ps | ||
T107 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2846346 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 2243005026 ps | ||
T315 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3329724843 | Jul 28 05:00:19 PM PDT 24 | Jul 28 05:00:24 PM PDT 24 | 538882134 ps | ||
T316 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2837185078 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 271143136 ps | ||
T154 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3587411254 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:01:13 PM PDT 24 | 10473355499 ps | ||
T317 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2675906421 | Jul 28 05:00:32 PM PDT 24 | Jul 28 05:03:52 PM PDT 24 | 75462782191 ps | ||
T318 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4255019912 | Jul 28 05:00:58 PM PDT 24 | Jul 28 05:02:24 PM PDT 24 | 87772114617 ps | ||
T98 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2121296842 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 221445057 ps | ||
T319 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2779894093 | Jul 28 05:00:59 PM PDT 24 | Jul 28 05:01:01 PM PDT 24 | 167658098 ps | ||
T320 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2304745541 | Jul 28 05:00:37 PM PDT 24 | Jul 28 05:01:16 PM PDT 24 | 14067603822 ps | ||
T321 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4026587092 | Jul 28 05:00:37 PM PDT 24 | Jul 28 05:00:38 PM PDT 24 | 1674311874 ps | ||
T322 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.216006400 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 237619344 ps | ||
T323 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3278448186 | Jul 28 05:00:39 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 248567804 ps | ||
T108 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3013030453 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 631674936 ps | ||
T324 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3588957588 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 216763487 ps | ||
T156 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2516296196 | Jul 28 05:00:32 PM PDT 24 | Jul 28 05:00:41 PM PDT 24 | 479104580 ps | ||
T325 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.314894553 | Jul 28 05:01:01 PM PDT 24 | Jul 28 05:01:06 PM PDT 24 | 504842565 ps | ||
T326 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.121015283 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 4844134598 ps | ||
T109 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3612490759 | Jul 28 05:01:01 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 1806078433 ps | ||
T327 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3105636177 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 934876130 ps | ||
T99 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2602072530 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:01:40 PM PDT 24 | 2945569014 ps | ||
T328 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1099011503 | Jul 28 05:00:35 PM PDT 24 | Jul 28 05:00:37 PM PDT 24 | 486473298 ps | ||
T329 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1075722400 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:01:02 PM PDT 24 | 505938586 ps | ||
T330 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2423890813 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 160868009 ps | ||
T155 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2637275798 | Jul 28 05:00:55 PM PDT 24 | Jul 28 05:01:12 PM PDT 24 | 1381604964 ps | ||
T159 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3120295418 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:01:46 PM PDT 24 | 45609933191 ps | ||
T331 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.40743608 | Jul 28 05:01:23 PM PDT 24 | Jul 28 05:01:31 PM PDT 24 | 2564611146 ps | ||
T157 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1837992821 | Jul 28 05:00:19 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 3776010703 ps | ||
T332 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2847919907 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 231352027 ps | ||
T333 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4166489765 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:00:58 PM PDT 24 | 5018733264 ps | ||
T100 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.369162485 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 2191080433 ps | ||
T334 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2264723894 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:25 PM PDT 24 | 186263589 ps | ||
T335 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.975159546 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:01:43 PM PDT 24 | 23609636749 ps | ||
T336 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3628943961 | Jul 28 05:00:26 PM PDT 24 | Jul 28 05:00:29 PM PDT 24 | 5362523996 ps | ||
T337 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1764433351 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:56 PM PDT 24 | 298389942 ps | ||
T338 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2122552022 | Jul 28 05:00:32 PM PDT 24 | Jul 28 05:01:26 PM PDT 24 | 21807396423 ps | ||
T101 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2451365783 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 700290168 ps | ||
T110 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1369621204 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 129254014 ps | ||
T339 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1435623734 | Jul 28 05:00:50 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 658187317 ps | ||
T340 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1265578789 | Jul 28 05:00:51 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 564963709 ps | ||
T341 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.965776128 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:02:18 PM PDT 24 | 37305354987 ps | ||
T342 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2450402820 | Jul 28 05:00:38 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 3336393289 ps | ||
T343 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.723764905 | Jul 28 05:01:08 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 155168656 ps | ||
T152 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.852837336 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:01:11 PM PDT 24 | 7094604411 ps | ||
T344 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4066658868 | Jul 28 05:00:52 PM PDT 24 | Jul 28 05:00:54 PM PDT 24 | 428974190 ps | ||
T345 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.9902656 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 73043593 ps | ||
T104 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1861238883 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:01:59 PM PDT 24 | 73064669804 ps | ||
T346 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2446414615 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:33 PM PDT 24 | 599680980 ps | ||
T92 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1580360234 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:39 PM PDT 24 | 2302960432 ps | ||
T158 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.887974345 | Jul 28 05:00:48 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 753212314 ps | ||
T347 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3180293055 | Jul 28 05:00:43 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 420705700 ps | ||
T348 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.367634833 | Jul 28 05:00:36 PM PDT 24 | Jul 28 05:00:37 PM PDT 24 | 384198857 ps | ||
T349 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.461320356 | Jul 28 05:00:51 PM PDT 24 | Jul 28 05:07:35 PM PDT 24 | 168486017669 ps | ||
T93 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3948956500 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 250081844 ps | ||
T350 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3969942373 | Jul 28 05:01:13 PM PDT 24 | Jul 28 05:01:24 PM PDT 24 | 1207183520 ps | ||
T94 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3969492139 | Jul 28 05:00:48 PM PDT 24 | Jul 28 05:00:56 PM PDT 24 | 577516061 ps | ||
T351 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3006502158 | Jul 28 05:00:35 PM PDT 24 | Jul 28 05:00:36 PM PDT 24 | 238394410 ps | ||
T352 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2181835128 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 293591242 ps | ||
T353 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1840360422 | Jul 28 05:00:52 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 398146918 ps | ||
T354 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3251564339 | Jul 28 05:01:02 PM PDT 24 | Jul 28 05:01:08 PM PDT 24 | 1940860327 ps | ||
T355 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3966602494 | Jul 28 05:00:38 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 933271728 ps | ||
T105 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2361671924 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 260604905 ps | ||
T356 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4241245378 | Jul 28 05:00:41 PM PDT 24 | Jul 28 05:00:54 PM PDT 24 | 4226381019 ps | ||
T357 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1096481207 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 155766693 ps | ||
T358 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1032652484 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 8437538736 ps | ||
T87 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2709907639 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:28 PM PDT 24 | 1437213353 ps | ||
T359 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1075402516 | Jul 28 05:01:04 PM PDT 24 | Jul 28 05:01:08 PM PDT 24 | 2996415153 ps | ||
T102 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.827585093 | Jul 28 05:00:58 PM PDT 24 | Jul 28 05:01:00 PM PDT 24 | 226174073 ps | ||
T360 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.298613286 | Jul 28 05:00:20 PM PDT 24 | Jul 28 05:00:33 PM PDT 24 | 3101420885 ps | ||
T361 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3736862724 | Jul 28 05:00:39 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 325476071 ps | ||
T362 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3704203 | Jul 28 05:00:19 PM PDT 24 | Jul 28 05:05:47 PM PDT 24 | 115615888677 ps | ||
T363 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2088599933 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 16264776714 ps | ||
T364 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2466685391 | Jul 28 05:00:23 PM PDT 24 | Jul 28 05:03:20 PM PDT 24 | 200838674953 ps | ||
T365 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.220490054 | Jul 28 05:00:41 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 317726810 ps | ||
T366 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1623117566 | Jul 28 05:00:41 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 442095539 ps | ||
T95 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1161331885 | Jul 28 05:01:01 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 481394119 ps | ||
T367 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3731310581 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 85518617 ps | ||
T368 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3776756021 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:01:04 PM PDT 24 | 11254280294 ps | ||
T369 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2814991081 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:42 PM PDT 24 | 65674940 ps | ||
T370 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2691928181 | Jul 28 05:00:32 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 6005218784 ps | ||
T371 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2207975144 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 1000838168 ps | ||
T372 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3210876624 | Jul 28 05:00:51 PM PDT 24 | Jul 28 05:00:57 PM PDT 24 | 161115504 ps | ||
T373 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2571755633 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:50 PM PDT 24 | 215378714 ps | ||
T374 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.155910277 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:50 PM PDT 24 | 772504056 ps | ||
T375 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.858162614 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:01:19 PM PDT 24 | 73018599903 ps | ||
T376 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1934594372 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:01:32 PM PDT 24 | 20910247101 ps | ||
T377 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2349655314 | Jul 28 05:01:08 PM PDT 24 | Jul 28 05:01:11 PM PDT 24 | 2069491056 ps | ||
T378 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.475316242 | Jul 28 05:00:20 PM PDT 24 | Jul 28 05:01:26 PM PDT 24 | 3479490682 ps | ||
T379 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.794990335 | Jul 28 05:01:04 PM PDT 24 | Jul 28 05:01:10 PM PDT 24 | 1296273623 ps | ||
T380 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2847327196 | Jul 28 05:01:00 PM PDT 24 | Jul 28 05:01:09 PM PDT 24 | 868362661 ps | ||
T150 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2054611429 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:01:01 PM PDT 24 | 4544804238 ps | ||
T381 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1697826011 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:01:10 PM PDT 24 | 18552386452 ps | ||
T382 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2562898551 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:41 PM PDT 24 | 129806299 ps | ||
T383 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.400147483 | Jul 28 05:00:54 PM PDT 24 | Jul 28 05:01:42 PM PDT 24 | 32848415725 ps | ||
T384 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.292919017 | Jul 28 05:00:21 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 11242226447 ps | ||
T385 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4191193069 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 6948503829 ps | ||
T386 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2054514694 | Jul 28 05:00:52 PM PDT 24 | Jul 28 05:01:01 PM PDT 24 | 6321190720 ps | ||
T96 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3268780903 | Jul 28 05:00:38 PM PDT 24 | Jul 28 05:00:42 PM PDT 24 | 419287156 ps | ||
T387 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1818405053 | Jul 28 05:00:36 PM PDT 24 | Jul 28 05:01:03 PM PDT 24 | 28111647003 ps | ||
T388 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3532435498 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 1086107191 ps | ||
T389 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3223833022 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 416238215 ps | ||
T390 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2347126662 | Jul 28 05:00:15 PM PDT 24 | Jul 28 05:00:29 PM PDT 24 | 9706017398 ps | ||
T391 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3458386134 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:46 PM PDT 24 | 715422692 ps | ||
T392 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2364234601 | Jul 28 05:00:39 PM PDT 24 | Jul 28 05:00:56 PM PDT 24 | 3259904982 ps | ||
T393 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1950769614 | Jul 28 05:00:28 PM PDT 24 | Jul 28 05:00:30 PM PDT 24 | 180774844 ps | ||
T394 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1648309457 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:46 PM PDT 24 | 536543025 ps | ||
T395 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3015233261 | Jul 28 05:00:40 PM PDT 24 | Jul 28 05:00:45 PM PDT 24 | 2804138162 ps | ||
T396 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2796175976 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:01:40 PM PDT 24 | 108161877994 ps | ||
T397 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3156916245 | Jul 28 05:00:29 PM PDT 24 | Jul 28 05:00:30 PM PDT 24 | 47193519 ps | ||
T151 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1325110447 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:01:01 PM PDT 24 | 1489511480 ps | ||
T398 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1443591146 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 1268409876 ps | ||
T399 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2811850905 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:03:05 PM PDT 24 | 61340202265 ps | ||
T400 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2591744499 | Jul 28 05:00:38 PM PDT 24 | Jul 28 05:01:52 PM PDT 24 | 4020353680 ps | ||
T401 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3525277199 | Jul 28 05:00:14 PM PDT 24 | Jul 28 05:00:15 PM PDT 24 | 384757999 ps | ||
T402 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3522486961 | Jul 28 05:00:42 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 184098480 ps | ||
T403 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2748995452 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 2187905981 ps | ||
T404 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2163586898 | Jul 28 05:00:14 PM PDT 24 | Jul 28 05:00:34 PM PDT 24 | 39797197885 ps | ||
T405 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1893589701 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 293482123 ps | ||
T406 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3836940782 | Jul 28 05:00:55 PM PDT 24 | Jul 28 05:00:56 PM PDT 24 | 764325465 ps | ||
T407 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3187990592 | Jul 28 05:00:45 PM PDT 24 | Jul 28 05:00:47 PM PDT 24 | 880204947 ps | ||
T408 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.107482983 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:01:01 PM PDT 24 | 1207625459 ps | ||
T409 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1195812793 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 327204073 ps | ||
T410 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.775811611 | Jul 28 05:00:41 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 91405849 ps | ||
T411 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1671211250 | Jul 28 05:00:22 PM PDT 24 | Jul 28 05:00:44 PM PDT 24 | 7706496165 ps | ||
T412 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3848400378 | Jul 28 05:00:39 PM PDT 24 | Jul 28 05:00:40 PM PDT 24 | 165160619 ps | ||
T413 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1858248275 | Jul 28 05:00:55 PM PDT 24 | Jul 28 05:01:00 PM PDT 24 | 2950607289 ps | ||
T414 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2756938393 | Jul 28 05:00:27 PM PDT 24 | Jul 28 05:00:28 PM PDT 24 | 291928340 ps | ||
T415 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3815579623 | Jul 28 05:00:33 PM PDT 24 | Jul 28 05:01:38 PM PDT 24 | 10227466058 ps | ||
T416 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2090560822 | Jul 28 05:00:49 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 245563014 ps | ||
T417 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.600449777 | Jul 28 05:00:53 PM PDT 24 | Jul 28 05:01:04 PM PDT 24 | 5411232805 ps | ||
T418 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.254972535 | Jul 28 05:01:00 PM PDT 24 | Jul 28 05:01:04 PM PDT 24 | 471422612 ps | ||
T419 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1323702031 | Jul 28 05:00:52 PM PDT 24 | Jul 28 05:00:53 PM PDT 24 | 357364712 ps | ||
T420 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1419020485 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 413642522 ps | ||
T103 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1469416729 | Jul 28 05:00:41 PM PDT 24 | Jul 28 05:00:43 PM PDT 24 | 69443773 ps | ||
T421 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3552788295 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:32 PM PDT 24 | 211767220 ps | ||
T422 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1560451777 | Jul 28 05:00:48 PM PDT 24 | Jul 28 05:02:26 PM PDT 24 | 56228644412 ps | ||
T88 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2730303748 | Jul 28 05:00:31 PM PDT 24 | Jul 28 05:00:38 PM PDT 24 | 4101535857 ps | ||
T423 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.848036293 | Jul 28 05:01:01 PM PDT 24 | Jul 28 05:01:04 PM PDT 24 | 1574795262 ps | ||
T424 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3353322750 | Jul 28 05:00:51 PM PDT 24 | Jul 28 05:00:54 PM PDT 24 | 215401869 ps | ||
T425 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2507173698 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:01:02 PM PDT 24 | 1585973700 ps | ||
T426 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4192169651 | Jul 28 05:01:03 PM PDT 24 | Jul 28 05:01:07 PM PDT 24 | 263027621 ps | ||
T427 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.137865702 | Jul 28 05:00:58 PM PDT 24 | Jul 28 05:01:00 PM PDT 24 | 115746812 ps | ||
T428 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1214087407 | Jul 28 05:00:48 PM PDT 24 | Jul 28 05:00:49 PM PDT 24 | 91704112 ps | ||
T429 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1205769466 | Jul 28 05:00:35 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 20934622907 ps | ||
T430 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2548176663 | Jul 28 05:00:52 PM PDT 24 | Jul 28 05:00:55 PM PDT 24 | 177316223 ps | ||
T431 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4043607814 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 301924176 ps | ||
T432 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2899814495 | Jul 28 05:00:57 PM PDT 24 | Jul 28 05:00:59 PM PDT 24 | 177017469 ps | ||
T433 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3098709255 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 147125719 ps | ||
T434 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.100896684 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:51 PM PDT 24 | 233001021 ps | ||
T435 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1413127484 | Jul 28 05:00:46 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 207895615 ps | ||
T436 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.179212069 | Jul 28 05:00:47 PM PDT 24 | Jul 28 05:00:52 PM PDT 24 | 2567225605 ps | ||
T437 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4078030234 | Jul 28 05:00:23 PM PDT 24 | Jul 28 05:00:24 PM PDT 24 | 178925403 ps | ||
T438 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1744692376 | Jul 28 05:00:59 PM PDT 24 | Jul 28 05:01:07 PM PDT 24 | 510297401 ps | ||
T439 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3396551741 | Jul 28 05:01:03 PM PDT 24 | Jul 28 05:01:07 PM PDT 24 | 608951097 ps | ||
T440 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1757259657 | Jul 28 05:00:16 PM PDT 24 | Jul 28 05:00:18 PM PDT 24 | 130429748 ps | ||
T441 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1691318947 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:46 PM PDT 24 | 167119855 ps | ||
T442 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1696143875 | Jul 28 05:00:29 PM PDT 24 | Jul 28 05:00:30 PM PDT 24 | 151410087 ps | ||
T443 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2910553096 | Jul 28 05:00:44 PM PDT 24 | Jul 28 05:00:48 PM PDT 24 | 357102101 ps |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.455478977 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 6481195327 ps |
CPU time | 10.03 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-e185ebbf-dfdf-48d0-9aa3-b5783f2ea247 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455478977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.455478977 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.902239750 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 70971445298 ps |
CPU time | 1194.06 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:20:57 PM PDT 24 |
Peak memory | 235492 kb |
Host | smart-919f5c31-1b18-47ad-b4d6-ebd8a87168ed |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902239750 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.902239750 |
Directory | /workspace/5.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1409220803 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 22270234136 ps |
CPU time | 64.87 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:02:10 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-b40b95d6-ce7f-4678-bada-05fe521bd6d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409220803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1409220803 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1947676702 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 8727435193 ps |
CPU time | 7.17 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-efcf497c-d1a0-47eb-acf0-6e7dcf0b4646 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1947676702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1947676702 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.2229953745 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 138364028270 ps |
CPU time | 513.95 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:09:37 PM PDT 24 |
Peak memory | 227744 kb |
Host | smart-bb16a6b3-887b-4466-9979-e1d8db9b2fd7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229953745 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.2229953745 |
Directory | /workspace/3.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3314159440 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 6008225711 ps |
CPU time | 22.22 seconds |
Started | Jul 28 05:00:50 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-46556827-a5a6-4246-8c9b-dfc351531d03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314159440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 314159440 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.589041470 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 785325245 ps |
CPU time | 2.26 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 229472 kb |
Host | smart-f9fec5fe-8e71-4b41-a189-4c9bce604d46 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589041470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.589041470 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.366464835 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 121981183 ps |
CPU time | 0.85 seconds |
Started | Jul 28 05:00:54 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-f6050292-2f61-4c87-908a-3eba17005242 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366464835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.366464835 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.4177919544 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1746117707 ps |
CPU time | 2.88 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-deabc742-f491-49a5-be1a-51a3cdf1b25e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177919544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.4177919544 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.424723239 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 325262489 ps |
CPU time | 2.29 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:23 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-60bf2c36-ae14-4b10-a2f9-fb57ade9d0b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424723239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.424723239 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.224304767 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 3947548080 ps |
CPU time | 4.15 seconds |
Started | Jul 28 05:01:17 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-954a854c-e6c1-4ce9-94a1-01685d5bc9ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224304767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.224304767 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1604574952 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 765745055 ps |
CPU time | 1.95 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-fc043a7e-d88c-4dfc-80ab-4267c00d0e77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604574952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1604574952 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1640322701 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2949775785 ps |
CPU time | 2.98 seconds |
Started | Jul 28 05:01:17 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-c8407f0e-447a-4f6f-bf27-f61d4a7111cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640322701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1640322701 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.1097795137 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 9757777083 ps |
CPU time | 8.36 seconds |
Started | Jul 28 05:01:17 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-e8029a8f-e9ac-403b-a773-7e369b430d65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097795137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1097795137 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1718781905 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 38578473 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-5dc3f030-0999-40c7-a935-4320eac9f8df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718781905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1718781905 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.107052835 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 563290011 ps |
CPU time | 0.84 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-f1d2d8f1-76fc-4fc8-a40f-4f063f730f9a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107052835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.107052835 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3558550899 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 701239840 ps |
CPU time | 6.55 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:27 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-a5a4f917-1cdc-417d-913d-eb44268df36e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558550899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.3558550899 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3016321499 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 91941850 ps |
CPU time | 0.99 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:03 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-7ffe6bbd-cd48-41e3-b18e-abdef28206b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016321499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3016321499 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3046262336 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1876052235 ps |
CPU time | 5.85 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-f7b9c975-3f56-438d-87f4-e36a3220e6cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046262336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3046262336 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.1866346696 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 87461229 ps |
CPU time | 0.85 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-9c22dc68-921c-4877-8663-1f76863b4c17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866346696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.1866346696 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.852837336 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 7094604411 ps |
CPU time | 23.65 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 214460 kb |
Host | smart-0942287f-2ba3-4d80-8fb4-da1e192d1c79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852837336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.852837336 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1672910983 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 1527952139 ps |
CPU time | 1.9 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-6e2f389f-dc24-4a19-9374-ffdd3e417552 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672910983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1672910983 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4191193069 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 6948503829 ps |
CPU time | 15.3 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 219608 kb |
Host | smart-47782b19-7bd6-49dc-89d2-b907c4789f37 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191193069 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.4191193069 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.3345907109 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 2772625426 ps |
CPU time | 5.15 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:29 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-89b46469-1fbb-46b4-82f6-1965c0fb492b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345907109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3345907109 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1735357821 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 3819210498 ps |
CPU time | 6.64 seconds |
Started | Jul 28 05:01:16 PM PDT 24 |
Finished | Jul 28 05:01:23 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-1f70d3e4-7bc5-40a4-97a0-a37ba7cc692e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735357821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1735357821 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3830869300 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 1156546581 ps |
CPU time | 2.24 seconds |
Started | Jul 28 05:00:26 PM PDT 24 |
Finished | Jul 28 05:00:28 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-a77def63-4174-4c1a-b2c3-14f4dace3c0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830869300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3830869300 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2730303748 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 4101535857 ps |
CPU time | 6.83 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:38 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-a3159fc3-d468-4cbe-809b-2b01bd4bc78f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730303748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2730303748 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2364234601 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3259904982 ps |
CPU time | 17.26 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-abc97366-e402-41ff-9719-4ce3d47b2985 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364234601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 364234601 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1837992821 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 3776010703 ps |
CPU time | 23.26 seconds |
Started | Jul 28 05:00:19 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-ec717e38-1ff5-4798-8cd9-f9087142db08 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837992821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1837992821 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3587411254 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 10473355499 ps |
CPU time | 20.67 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 221664 kb |
Host | smart-4d2a0f80-6135-4e71-943f-eb46d92b8627 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587411254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3587411254 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2619862955 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 147924778 ps |
CPU time | 1.02 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-7c38a101-4d0b-46da-94af-92ccef25b40c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619862955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2619862955 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.3458286272 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 610661377 ps |
CPU time | 2.31 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-65301602-d0af-41e1-b5ab-5e833eee9b85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458286272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3458286272 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2848102269 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 6246833963 ps |
CPU time | 8.96 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-6f8ac4f1-0992-4f3d-8bf6-9fe61f91142b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2848102269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.2848102269 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.927839011 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 6725386632 ps |
CPU time | 8.8 seconds |
Started | Jul 28 05:01:17 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-b0efc8db-ea86-4f09-8894-2b8e1f89cbc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927839011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.927839011 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.475316242 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 3479490682 ps |
CPU time | 65.71 seconds |
Started | Jul 28 05:00:20 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-c424cf5c-8cb5-4b74-9028-bee5126b868d |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475316242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.rv_dm_csr_aliasing.475316242 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3595605876 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 2648962562 ps |
CPU time | 31.96 seconds |
Started | Jul 28 05:00:11 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-97ed095f-1e29-4dd6-8e84-0087ad459380 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595605876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3595605876 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1950769614 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 180774844 ps |
CPU time | 2.51 seconds |
Started | Jul 28 05:00:28 PM PDT 24 |
Finished | Jul 28 05:00:30 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-e0a65e9f-8d24-456f-85a5-27eebaf82ef0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950769614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1950769614 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3460002469 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 341839508 ps |
CPU time | 3.72 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 221684 kb |
Host | smart-7d92181c-8b8a-44a1-bb9c-ab59957cebbb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460002469 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3460002469 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.802789771 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 215432200 ps |
CPU time | 2.43 seconds |
Started | Jul 28 05:00:14 PM PDT 24 |
Finished | Jul 28 05:00:17 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-8e6007e1-18e2-4b51-a831-e99a233489b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802789771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.802789771 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1428603928 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 77252342529 ps |
CPU time | 98.13 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:02:11 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-00bee26d-f945-4e3b-9b92-fbd62f04fec6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428603928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1428603928 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3776756021 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 11254280294 ps |
CPU time | 31.26 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-f5da010a-7bf5-411a-a3d0-dfedbb05deb9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776756021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3776756021 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3628943961 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 5362523996 ps |
CPU time | 2.2 seconds |
Started | Jul 28 05:00:26 PM PDT 24 |
Finished | Jul 28 05:00:29 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-ccc1f450-5f32-46ef-ac7e-01965fc8f41c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628943961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3628943961 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2026548191 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2346736154 ps |
CPU time | 2.28 seconds |
Started | Jul 28 05:00:15 PM PDT 24 |
Finished | Jul 28 05:00:18 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-a7a60458-9938-42ef-8730-ed3c36b26d75 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026548191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 026548191 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2163586898 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 39797197885 ps |
CPU time | 20.13 seconds |
Started | Jul 28 05:00:14 PM PDT 24 |
Finished | Jul 28 05:00:34 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-e62f3d4d-fd37-4cb7-af61-e73af7a0344d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163586898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.2163586898 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3006502158 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 238394410 ps |
CPU time | 0.95 seconds |
Started | Jul 28 05:00:35 PM PDT 24 |
Finished | Jul 28 05:00:36 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-0d21536b-10c3-43f9-95ef-05ed5098cd78 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006502158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3006502158 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1757259657 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 130429748 ps |
CPU time | 0.98 seconds |
Started | Jul 28 05:00:16 PM PDT 24 |
Finished | Jul 28 05:00:18 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-28d77eb1-6226-43d2-841b-f2fa3178e879 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757259657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 757259657 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.689479813 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 87634248 ps |
CPU time | 0.91 seconds |
Started | Jul 28 05:00:19 PM PDT 24 |
Finished | Jul 28 05:00:20 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-41f086ec-e282-474e-9939-1cc3e6a5cdbe |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689479813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.689479813 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3156916245 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 47193519 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:00:29 PM PDT 24 |
Finished | Jul 28 05:00:30 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-64b3c313-120a-4309-921a-a67eaf23d611 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156916245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3156916245 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2347126662 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 9706017398 ps |
CPU time | 13.7 seconds |
Started | Jul 28 05:00:15 PM PDT 24 |
Finished | Jul 28 05:00:29 PM PDT 24 |
Peak memory | 216944 kb |
Host | smart-7c74f1d8-4e66-4100-811e-04ec51255d97 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347126662 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2347126662 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.97192714 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 148982078 ps |
CPU time | 3.05 seconds |
Started | Jul 28 05:00:26 PM PDT 24 |
Finished | Jul 28 05:00:29 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-94bcac23-d8f0-4eec-bb5c-678eada6fb36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97192714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.97192714 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2516296196 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 479104580 ps |
CPU time | 9.3 seconds |
Started | Jul 28 05:00:32 PM PDT 24 |
Finished | Jul 28 05:00:41 PM PDT 24 |
Peak memory | 221556 kb |
Host | smart-cdbb04c0-6a1e-45dc-8b5f-2c1ca597c344 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516296196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2516296196 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.369162485 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 2191080433 ps |
CPU time | 26.09 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-a025a3fd-093e-492a-b0c1-d23b2ea38408 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369162485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.rv_dm_csr_aliasing.369162485 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1861238883 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 73064669804 ps |
CPU time | 86.15 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:01:59 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-7d01942a-73b5-4208-9be2-2eb6860c55cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861238883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1861238883 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2451365783 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 700290168 ps |
CPU time | 2.65 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-efde091d-9636-4c0d-a8e7-49192856b8ba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451365783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2451365783 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2264723894 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 186263589 ps |
CPU time | 3.77 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:25 PM PDT 24 |
Peak memory | 219068 kb |
Host | smart-225d9126-0353-42a1-afb2-47d3022717fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264723894 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2264723894 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3704203 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 115615888677 ps |
CPU time | 327.36 seconds |
Started | Jul 28 05:00:19 PM PDT 24 |
Finished | Jul 28 05:05:47 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-bde10568-3c66-4aac-8ac0-7b4ca8fefddd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_a liasing.3704203 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2043185996 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 9004167233 ps |
CPU time | 23.86 seconds |
Started | Jul 28 05:00:29 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-df27592f-2dd8-46a8-8edd-e052d83a8a55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043185996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.2043185996 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1671211250 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 7706496165 ps |
CPU time | 21.99 seconds |
Started | Jul 28 05:00:22 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-2d9cc029-8670-4a31-a1a2-019002480d8d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671211250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 671211250 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2926906233 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 485982824 ps |
CPU time | 1.53 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:33 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-1d9a705d-e43b-401a-988a-8bd9ec3d2b51 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926906233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2926906233 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2304745541 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 14067603822 ps |
CPU time | 38.9 seconds |
Started | Jul 28 05:00:37 PM PDT 24 |
Finished | Jul 28 05:01:16 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-6a0421fd-0456-4b4d-a92e-3c59ef25c711 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304745541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2304745541 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3525277199 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 384757999 ps |
CPU time | 0.86 seconds |
Started | Jul 28 05:00:14 PM PDT 24 |
Finished | Jul 28 05:00:15 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-ebbf6c27-6f87-4af4-b0fa-f4af13496366 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525277199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3525277199 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3105636177 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 934876130 ps |
CPU time | 1.8 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-b9c71e47-9cae-4b72-92b3-f2436869eaa9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105636177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 105636177 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1696143875 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 151410087 ps |
CPU time | 0.82 seconds |
Started | Jul 28 05:00:29 PM PDT 24 |
Finished | Jul 28 05:00:30 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-6b46c38e-2195-4e60-94db-8691704e4453 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696143875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1696143875 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.563642401 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 111696396 ps |
CPU time | 0.94 seconds |
Started | Jul 28 05:00:18 PM PDT 24 |
Finished | Jul 28 05:00:19 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-5c2bbbef-4749-4637-8361-cfad6469f466 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563642401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.563642401 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1580360234 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 2302960432 ps |
CPU time | 7.45 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:39 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-6f36f3ef-75ee-4ef6-9019-1dc8c50c9537 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580360234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.1580360234 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3329724843 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 538882134 ps |
CPU time | 4.58 seconds |
Started | Jul 28 05:00:19 PM PDT 24 |
Finished | Jul 28 05:00:24 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-d4aa8dc3-1eca-4f5d-a23e-2b93fdd49f19 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329724843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3329724843 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.298613286 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 3101420885 ps |
CPU time | 13.5 seconds |
Started | Jul 28 05:00:20 PM PDT 24 |
Finished | Jul 28 05:00:33 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-bd1b32e1-512e-494f-b4a0-6a304f8e39d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298613286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.298613286 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2779894093 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 167658098 ps |
CPU time | 2.41 seconds |
Started | Jul 28 05:00:59 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-03840881-d86d-488d-93a8-6ccdd94a0267 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779894093 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2779894093 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.398609371 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 215117322 ps |
CPU time | 2.26 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-a3b2d9ac-3fb3-4bd1-b63a-c402c0938c45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398609371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.398609371 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2497840449 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 19978978665 ps |
CPU time | 8.77 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-8e27df8f-58e3-4778-ae18-57590f07cf89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497840449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2497840449 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.873293695 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 15127701813 ps |
CPU time | 12.15 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:57 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-638fe8d5-f9c6-470a-bd83-ca1c18c58dd2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873293695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.873293695 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1323702031 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 357364712 ps |
CPU time | 0.89 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-5497ee55-e823-41fb-a3d5-86005519088c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323702031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 1323702031 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3353322750 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 215401869 ps |
CPU time | 3.6 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:00:54 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-671b2376-3d97-4cc8-bcc7-d2fb96652687 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353322750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.3353322750 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2207975144 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 1000838168 ps |
CPU time | 5.56 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-0e12a985-1092-4a3e-bc9c-6f39457e2755 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207975144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2207975144 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1840360422 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 398146918 ps |
CPU time | 2.66 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 218616 kb |
Host | smart-bd4e6ef1-54ce-4f4f-b4d2-23e203688444 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840360422 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1840360422 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4250777037 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 227724886 ps |
CPU time | 1.54 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-a7857dbe-90c3-4b6a-831f-29586d3a1687 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250777037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4250777037 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.965776128 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 37305354987 ps |
CPU time | 93.77 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:02:18 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-2db7c188-7b81-4b99-8758-e02c6676695f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965776128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.965776128 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3251564339 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 1940860327 ps |
CPU time | 6.01 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-c84d0a54-0b0c-48de-be0a-625895c1c9c2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251564339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 3251564339 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.216006400 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 237619344 ps |
CPU time | 1.21 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-5b92c4d9-a95f-4cff-8e58-9fee5d129277 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216006400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.216006400 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3969492139 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 577516061 ps |
CPU time | 8.13 seconds |
Started | Jul 28 05:00:48 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-d58a576d-00ff-4ac9-bf4c-ec588f523ade |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969492139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3969492139 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1189780432 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 166075904 ps |
CPU time | 4.25 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:50 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-7fe8c5e1-bdd9-4c0a-8caf-977b6ff855dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189780432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1189780432 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1075722400 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 505938586 ps |
CPU time | 4.2 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:02 PM PDT 24 |
Peak memory | 221624 kb |
Host | smart-21bf92d5-cf27-4b37-a34d-54354bd899ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075722400 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1075722400 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2548176663 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 177316223 ps |
CPU time | 2.59 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-2c7bbc63-e6f9-4832-ab59-d48d1e5fbc09 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548176663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2548176663 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1858248275 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 2950607289 ps |
CPU time | 5.09 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-b7583683-527d-4265-99b4-a0369662bc41 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858248275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1858248275 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2507173698 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 1585973700 ps |
CPU time | 4.85 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:02 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-57ed4249-56b6-474d-8cf5-60b0232af0af |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507173698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 2507173698 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.331486468 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 361773997 ps |
CPU time | 0.86 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-52afc87c-e229-4f3c-83f1-e0d21dcecded |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331486468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.331486468 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2507050547 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 952476270 ps |
CPU time | 4.27 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-c58d8519-7038-41be-8133-2109ad7f85a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507050547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2507050547 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4043607814 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 301924176 ps |
CPU time | 3.76 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-64b04a8a-1ec0-4ead-bcbd-ab287bfcb9cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043607814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4043607814 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.600449777 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 5411232805 ps |
CPU time | 11.23 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-cd1f48db-3036-4d6a-9226-8f9a098745e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600449777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.600449777 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.862125221 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 96930887 ps |
CPU time | 3.6 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 221516 kb |
Host | smart-cdad43f2-f9bb-48de-a73a-c4ef1af7a501 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862125221 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.862125221 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1413127484 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 207895615 ps |
CPU time | 1.65 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-ee585026-36d8-4795-8570-d07f2696d9ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413127484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1413127484 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2866054179 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 39035772612 ps |
CPU time | 22.06 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-1240537a-f62d-4a55-ac9a-0a152261b2cd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866054179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.2866054179 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2054514694 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 6321190720 ps |
CPU time | 9.49 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-b8ed56bf-4823-4de0-9c87-3c2267d87666 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054514694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 2054514694 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1321606834 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 226064228 ps |
CPU time | 1.29 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-eac0dd8d-bd19-4be9-8d57-0e401541fe12 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321606834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 1321606834 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3013030453 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 631674936 ps |
CPU time | 6.42 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-a09633b7-7151-4f26-bde8-536463f103bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013030453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.3013030453 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1893589701 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 293482123 ps |
CPU time | 6.45 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-cca482cd-b483-4a1c-8318-2539699c2b8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893589701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1893589701 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1623117566 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 442095539 ps |
CPU time | 3.85 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 218184 kb |
Host | smart-9d4a0e3f-d771-458a-a44b-be10186c4850 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623117566 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1623117566 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.137865702 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 115746812 ps |
CPU time | 1.52 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-ae2c3512-2898-4cd3-a8fe-5a69774dad3b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137865702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.137865702 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.461320356 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 168486017669 ps |
CPU time | 403.35 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:07:35 PM PDT 24 |
Peak memory | 207168 kb |
Host | smart-de4a4a88-8e6c-4818-87a0-16e538dde640 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461320356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rv_dm_jtag_dmi_csr_bit_bash.461320356 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1854667490 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2913413137 ps |
CPU time | 4.63 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-2e3e8655-45f1-4b2b-8480-b826132e2604 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854667490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1854667490 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4066658868 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 428974190 ps |
CPU time | 1.34 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:54 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-f758660d-eeb1-41fb-b61f-c5f61e51e27f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066658868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4066658868 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3003066422 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 303566270 ps |
CPU time | 4.12 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-3c22d922-8f8c-46c5-ac6c-12574c6c1470 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003066422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3003066422 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1995043906 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 59569075 ps |
CPU time | 3.02 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-e9869488-6596-447c-8c0d-525fba28841f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995043906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1995043906 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.374551155 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1569641156 ps |
CPU time | 10.93 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-f44fc722-7802-4f47-a72d-f28771d7bcc7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374551155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.374551155 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2181835128 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 293591242 ps |
CPU time | 3.69 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 219016 kb |
Host | smart-a4cfe9c6-5e88-4d19-82e1-4a92e82ed5a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181835128 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2181835128 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1195812793 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 327204073 ps |
CPU time | 2.12 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-b3daf9b4-3e76-4726-9385-f6dd33f17b0f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195812793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1195812793 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.400147483 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 32848415725 ps |
CPU time | 48.04 seconds |
Started | Jul 28 05:00:54 PM PDT 24 |
Finished | Jul 28 05:01:42 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-5ebcf816-b1d5-43a6-8cf3-55a259c60adf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400147483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rv_dm_jtag_dmi_csr_bit_bash.400147483 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1443591146 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1268409876 ps |
CPU time | 2.6 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-b241c012-efeb-42be-be45-35d4b426d62e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443591146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 1443591146 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3187990592 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 880204947 ps |
CPU time | 2.42 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-f4eafa45-69fc-42d3-b737-f90e8bc60df7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187990592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3187990592 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3612490759 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 1806078433 ps |
CPU time | 7.77 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-c5f29d30-19d4-4e09-a4f7-0c52972c13c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612490759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.3612490759 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1082315291 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 245838183 ps |
CPU time | 3.18 seconds |
Started | Jul 28 05:00:56 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-3c4a2347-0ac1-4620-8bbd-cf36b35006d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082315291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1082315291 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2637275798 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1381604964 ps |
CPU time | 16.68 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-ca8be5de-f4b2-4eaa-ba0f-9473f08e095b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637275798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 637275798 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.314894553 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 504842565 ps |
CPU time | 4.98 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 221588 kb |
Host | smart-7954980e-41d7-406a-a805-c8af10e17841 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314894553 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.314894553 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2899814495 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 177017469 ps |
CPU time | 1.65 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-a8351b1f-88c2-4290-8ad4-45f4c7550673 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899814495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2899814495 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2088599933 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 16264776714 ps |
CPU time | 22.46 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-a5eeabd1-9e6d-434c-9da6-5bdff6140089 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088599933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2088599933 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3254880919 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2211451380 ps |
CPU time | 3.72 seconds |
Started | Jul 28 05:01:18 PM PDT 24 |
Finished | Jul 28 05:01:22 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-8edb0d55-7d74-41d1-a5e9-c667c54fed68 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254880919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 3254880919 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3836940782 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 764325465 ps |
CPU time | 1.21 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-484f0dea-99ca-4f70-97d9-0513b6435dc6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836940782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 3836940782 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2480306267 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 787449670 ps |
CPU time | 4.22 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-244fd906-bf93-4199-a369-e5b7a014a5b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480306267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2480306267 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.794990335 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1296273623 ps |
CPU time | 5.45 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-7a2b9691-f716-4ac6-8c3f-174921a5d0b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794990335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.794990335 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.937650107 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 877914155 ps |
CPU time | 10.9 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-ca00d409-6215-4346-9056-6545348ef32c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937650107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.937650107 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.254972535 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 471422612 ps |
CPU time | 3.94 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 217756 kb |
Host | smart-488a16fb-94cc-4a5d-a694-4ed7d68a5f0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254972535 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.254972535 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3074614638 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 117445948 ps |
CPU time | 1.55 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-010abc07-11e6-44ab-98d6-2cba7ba1b26c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074614638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3074614638 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4280064502 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 3690812987 ps |
CPU time | 10.23 seconds |
Started | Jul 28 05:00:59 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-1b2b3cd0-b97b-41da-b0c9-8da7e4ae4ef3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280064502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.4280064502 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4166489765 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 5018733264 ps |
CPU time | 4.52 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-85117764-ace9-4971-bc54-4af79ca74d6c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166489765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 4166489765 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.723764905 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 155168656 ps |
CPU time | 0.9 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-a20792ea-1269-4e49-b407-8a2873947ea5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723764905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.723764905 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.179212069 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 2567225605 ps |
CPU time | 4.6 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-8836420d-c6fa-41ca-abcb-e549409c3630 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179212069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.179212069 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1764433351 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 298389942 ps |
CPU time | 6.2 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-dbb04362-7e9d-4433-94df-386389e57196 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764433351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1764433351 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.409912263 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 4268493624 ps |
CPU time | 11.32 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:54 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-0d224f1d-c896-478c-9fdf-c0d8b795d7f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409912263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.409912263 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.512479438 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 577189932 ps |
CPU time | 3.89 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 219380 kb |
Host | smart-949ea414-116a-4118-9a68-d49fde4fcf44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512479438 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.512479438 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.827585093 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 226174073 ps |
CPU time | 1.53 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-d27d8ee4-b4d8-4920-9579-4e961a9fb544 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827585093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.827585093 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3487441784 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 3094582216 ps |
CPU time | 6.86 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:01:02 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-0065276d-e41f-4189-9900-e315679280d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487441784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.3487441784 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.848036293 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1574795262 ps |
CPU time | 3.1 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-8c495564-a47a-4204-b3a9-8752b4bba347 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848036293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.848036293 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3098709255 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 147125719 ps |
CPU time | 1.01 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-2f684784-8dd5-44b4-ac49-134a5baa7e50 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098709255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 3098709255 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1744692376 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 510297401 ps |
CPU time | 7.56 seconds |
Started | Jul 28 05:00:59 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-e5fe3d8e-a7cc-4014-898e-66ed48179512 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744692376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1744692376 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3210876624 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 161115504 ps |
CPU time | 5.73 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:00:57 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-d6f9ca31-f2ef-46b0-8d80-c529071e7c2b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210876624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3210876624 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3969942373 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 1207183520 ps |
CPU time | 10.5 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-28cc9b53-ce78-4c4f-aab8-317e6a31e2a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969942373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 969942373 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3396551741 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 608951097 ps |
CPU time | 3.85 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 221704 kb |
Host | smart-728d2447-2fc7-4b5c-94c2-44440db96eef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396551741 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3396551741 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3731310581 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 85518617 ps |
CPU time | 1.56 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-7922a949-2a12-4e39-8eef-6f3f46f722a4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731310581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3731310581 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.40743608 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 2564611146 ps |
CPU time | 7.76 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:31 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-ecaeee50-db27-43ab-9ded-0cf8a89192d8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40743608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.r v_dm_jtag_dmi_csr_bit_bash.40743608 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2349655314 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2069491056 ps |
CPU time | 2.97 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-64172c49-aa57-49a6-bf63-8c1849cd13af |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349655314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2349655314 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2837185078 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 271143136 ps |
CPU time | 1.06 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-32210493-2816-468c-a924-4b8e4c42057f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837185078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 2837185078 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1075402516 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 2996415153 ps |
CPU time | 4.45 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-59f9b935-5cfd-4d91-b2cc-2473d422306b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075402516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1075402516 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4192169651 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 263027621 ps |
CPU time | 3.5 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-da761cff-1dc1-40bb-9f82-8a9fa816ffb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192169651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4192169651 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2847327196 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 868362661 ps |
CPU time | 8.69 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-ed21c350-ca6b-4e85-bda4-ab34d72e7780 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847327196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 847327196 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.292919017 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 11242226447 ps |
CPU time | 31.93 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-2089f61f-48cf-45e6-8afa-407f973a21ff |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292919017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.292919017 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3815579623 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 10227466058 ps |
CPU time | 64.7 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:01:38 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-0795b352-8a1c-4eb1-b131-7779da83b0e7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815579623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3815579623 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.395320767 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 224175616 ps |
CPU time | 2.04 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:42 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-68349fd1-d4a2-4798-9231-b1d0be71bffe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395320767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.395320767 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1648309457 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 536543025 ps |
CPU time | 3.67 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:46 PM PDT 24 |
Peak memory | 221504 kb |
Host | smart-03543302-42b0-4975-99bc-cfc3623661f2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648309457 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1648309457 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1691318947 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 167119855 ps |
CPU time | 2 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:46 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-cf8d4dd2-459d-4814-ade6-ab4b538ab14a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691318947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1691318947 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2675906421 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 75462782191 ps |
CPU time | 199.57 seconds |
Started | Jul 28 05:00:32 PM PDT 24 |
Finished | Jul 28 05:03:52 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-37296ead-51df-434d-aaaa-149780086abc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675906421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2675906421 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3103008853 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 11150612175 ps |
CPU time | 8.39 seconds |
Started | Jul 28 05:00:32 PM PDT 24 |
Finished | Jul 28 05:00:41 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-8db53d28-1329-4f58-809b-b7a635c07e8f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103008853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.3103008853 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2709907639 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 1437213353 ps |
CPU time | 1.85 seconds |
Started | Jul 28 05:00:21 PM PDT 24 |
Finished | Jul 28 05:00:28 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-8f15d6b2-40aa-4538-a247-521d95f6b05d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709907639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2709907639 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4026587092 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1674311874 ps |
CPU time | 1.16 seconds |
Started | Jul 28 05:00:37 PM PDT 24 |
Finished | Jul 28 05:00:38 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-1899bce9-354a-44d1-9066-f33023e8eebe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026587092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4 026587092 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.763850040 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 220385044 ps |
CPU time | 0.82 seconds |
Started | Jul 28 05:00:29 PM PDT 24 |
Finished | Jul 28 05:00:30 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-d1b9ac41-f83f-48c0-8891-276fe52ca1e3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763850040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _aliasing.763850040 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1205769466 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 20934622907 ps |
CPU time | 17.01 seconds |
Started | Jul 28 05:00:35 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-f5607116-f141-43aa-8752-eb10ea1ac139 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205769466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1205769466 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.367634833 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 384198857 ps |
CPU time | 0.95 seconds |
Started | Jul 28 05:00:36 PM PDT 24 |
Finished | Jul 28 05:00:37 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-f64079e5-5df9-4e29-8fa5-78628495a558 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367634833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _hw_reset.367634833 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2756938393 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 291928340 ps |
CPU time | 0.86 seconds |
Started | Jul 28 05:00:27 PM PDT 24 |
Finished | Jul 28 05:00:28 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-da078212-09bc-45b6-84b5-0878693024c8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756938393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 756938393 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.4078030234 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 178925403 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:00:23 PM PDT 24 |
Finished | Jul 28 05:00:24 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-c01c788a-cd9b-47a2-a6e5-6b8939e34a8c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078030234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.4078030234 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3552788295 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 211767220 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:32 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-ff344ee6-efd5-4911-9f72-3181b445440c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552788295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3552788295 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1369621204 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 129254014 ps |
CPU time | 3.76 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-65cc75e2-0165-4e8b-9369-a8f160ca0da1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369621204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1369621204 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2423890813 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 160868009 ps |
CPU time | 3.68 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-b722bc2a-d520-49b8-bb80-0acbdba22aaa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423890813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2423890813 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2591744499 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 4020353680 ps |
CPU time | 74.05 seconds |
Started | Jul 28 05:00:38 PM PDT 24 |
Finished | Jul 28 05:01:52 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-b17399ab-8aa0-41e2-84c5-4ce26be7d7ad |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591744499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2591744499 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2602072530 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 2945569014 ps |
CPU time | 54.66 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:01:40 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-d81f4e1d-a4d4-4c8e-b80f-063d5aafb0b9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602072530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2602072530 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2121296842 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 221445057 ps |
CPU time | 1.83 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-0cc29873-e055-43a9-8177-099174d19831 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121296842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2121296842 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3588957588 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 216763487 ps |
CPU time | 2.23 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 214772 kb |
Host | smart-bb5c5c84-2631-4123-bf60-9e9bd6dc4760 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588957588 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3588957588 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3522486961 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 184098480 ps |
CPU time | 2.33 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-2243bcbe-4050-43e6-9d30-f73731a13898 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522486961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3522486961 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4255019912 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 87772114617 ps |
CPU time | 85.2 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:02:24 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-c2299197-b2e4-4c6f-ae09-0a7b199cb6e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255019912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.4255019912 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1032652484 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 8437538736 ps |
CPU time | 7.04 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-b6abf026-bc53-49f7-88fc-6fe03b2c575c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032652484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.1032652484 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3974386159 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2546377075 ps |
CPU time | 4.98 seconds |
Started | Jul 28 05:00:23 PM PDT 24 |
Finished | Jul 28 05:00:28 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-2319044a-fb7a-4391-bcaf-52f88a1a26c3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974386159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.3974386159 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2691928181 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 6005218784 ps |
CPU time | 10.08 seconds |
Started | Jul 28 05:00:32 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-bd17fd8e-d383-44f5-8488-6c4edc079ba4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691928181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 691928181 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3848400378 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 165160619 ps |
CPU time | 1.15 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:40 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-25b4a868-4f67-443e-8fa7-2e48ec50c325 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848400378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3848400378 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1934594372 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 20910247101 ps |
CPU time | 51.41 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:01:32 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-c43a7b92-694e-402d-b46c-87f55c3dd7c4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934594372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1934594372 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1435623734 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 658187317 ps |
CPU time | 1.17 seconds |
Started | Jul 28 05:00:50 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-57264d23-b3bb-4293-a2ee-0fc41c6acbd6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435623734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1435623734 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2562898551 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 129806299 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:41 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-3b72fa03-b2b5-4b9e-ab0d-cc1c0e3c30a0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562898551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 562898551 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3888617588 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 78138030 ps |
CPU time | 0.84 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:00:34 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-42cefa08-5422-4405-9e1d-0603409c0203 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888617588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.3888617588 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1214087407 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 91704112 ps |
CPU time | 0.88 seconds |
Started | Jul 28 05:00:48 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-bdd1a438-f3d7-4222-b256-999d295ed9dd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214087407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1214087407 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1419020485 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 413642522 ps |
CPU time | 3.99 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-8bf0f52f-990a-4efa-935b-28adc3ea8ee0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419020485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1419020485 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3120295418 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 45609933191 ps |
CPU time | 73.33 seconds |
Started | Jul 28 05:00:33 PM PDT 24 |
Finished | Jul 28 05:01:46 PM PDT 24 |
Peak memory | 221704 kb |
Host | smart-9a9b1fd2-0ffc-4610-81b1-23ec7c4267e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120295418 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3120295418 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.220490054 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 317726810 ps |
CPU time | 3.07 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-dd5c885e-6b6c-4fab-a787-2a12a5cdd483 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220490054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.220490054 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.887974345 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 753212314 ps |
CPU time | 10.68 seconds |
Started | Jul 28 05:00:48 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-bfc824c0-c402-4fd4-a6b0-cf48b2338fbc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887974345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.887974345 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2748995452 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2187905981 ps |
CPU time | 27.53 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-8306369a-9d3f-4716-8bd3-548c687f8e2a |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748995452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2748995452 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1386458898 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 2990952765 ps |
CPU time | 28.63 seconds |
Started | Jul 28 05:00:48 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-f23a8b83-3e09-4a20-a272-c11a8e3e46cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386458898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1386458898 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3268780903 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 419287156 ps |
CPU time | 3.17 seconds |
Started | Jul 28 05:00:38 PM PDT 24 |
Finished | Jul 28 05:00:42 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-f3ebede6-d3a0-4bad-9190-bbda6acfe095 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268780903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3268780903 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3458386134 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 715422692 ps |
CPU time | 3.86 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:46 PM PDT 24 |
Peak memory | 219344 kb |
Host | smart-441e2529-dcde-479d-8dbf-b8356d4d38cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458386134 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3458386134 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1469416729 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 69443773 ps |
CPU time | 2.21 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-53f74d27-4b62-4e45-8102-1c1617566538 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469416729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1469416729 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2466685391 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 200838674953 ps |
CPU time | 177.23 seconds |
Started | Jul 28 05:00:23 PM PDT 24 |
Finished | Jul 28 05:03:20 PM PDT 24 |
Peak memory | 209672 kb |
Host | smart-c92a1b78-9162-4470-a1da-63a2d1ebee34 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466685391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2466685391 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.121015283 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 4844134598 ps |
CPU time | 13.69 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-37d67d2c-b6e4-4795-aaa2-851aeeaaca83 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121015283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r v_dm_jtag_dmi_csr_bit_bash.121015283 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2450402820 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 3336393289 ps |
CPU time | 8.92 seconds |
Started | Jul 28 05:00:38 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-581d1e37-165d-4754-a388-b69f41f64f76 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450402820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2450402820 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2105161790 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2938721162 ps |
CPU time | 8.55 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-536ad922-f18f-4d12-9219-ee39216d30bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105161790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 105161790 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1265578789 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 564963709 ps |
CPU time | 1.36 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-0c5f2e99-4272-496d-a56c-e6b2097b4cf5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265578789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1265578789 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2122552022 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 21807396423 ps |
CPU time | 53.94 seconds |
Started | Jul 28 05:00:32 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-b559bc05-027e-4c07-8086-98c5b049fc9f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122552022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2122552022 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2446414615 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 599680980 ps |
CPU time | 2.1 seconds |
Started | Jul 28 05:00:31 PM PDT 24 |
Finished | Jul 28 05:00:33 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-976ee207-1031-4979-837d-15106de9ae1c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446414615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2446414615 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2082733574 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 600188720 ps |
CPU time | 1.11 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:40 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-6bd6f842-adb4-429c-97ce-38afe93ed3c6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082733574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 082733574 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2838906405 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 132772257 ps |
CPU time | 0.8 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-9ee45f0d-72c7-4462-9edc-20f95db3f3db |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838906405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.2838906405 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3205086456 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 45632144 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:00:38 PM PDT 24 |
Finished | Jul 28 05:00:39 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-b0082d5c-4343-4069-8bc7-b6b15dff65b8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205086456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3205086456 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2846346 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2243005026 ps |
CPU time | 7.9 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-fcf6f509-7e54-4c26-b4f7-d67ee781b970 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr _outstanding.2846346 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1791405502 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 17704160697 ps |
CPU time | 224.96 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:04:29 PM PDT 24 |
Peak memory | 215636 kb |
Host | smart-90814b1a-95e7-49ba-810e-ba7a5213e489 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791405502 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1791405502 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2090560822 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 245563014 ps |
CPU time | 2.78 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-ad752dea-6725-4c03-8953-9d3de0de490d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090560822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2090560822 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1325110447 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 1489511480 ps |
CPU time | 18.69 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-e3e4745a-eaaa-450f-a6b5-033e24a04294 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325110447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1325110447 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.100896684 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 233001021 ps |
CPU time | 4.92 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 221572 kb |
Host | smart-4223bd28-b58c-4bdb-b72e-a8e9a431c166 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100896684 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.100896684 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2814991081 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 65674940 ps |
CPU time | 2.18 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:42 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-65e88ca9-1c41-4335-9d33-e1ae3de6455f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814991081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2814991081 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.975159546 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 23609636749 ps |
CPU time | 59.45 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:01:43 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-d5710c10-c948-4263-af98-5ed1e627752c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975159546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r v_dm_jtag_dmi_csr_bit_bash.975159546 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2499804369 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 9620587163 ps |
CPU time | 8.83 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-09e629b3-8557-4f9d-a883-fdd2ecfe94e7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499804369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2 499804369 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1096481207 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 155766693 ps |
CPU time | 0.9 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-2ca64485-60d4-4327-8b94-90a9bfa86ce0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096481207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 096481207 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3223833022 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 416238215 ps |
CPU time | 4.7 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-97fb039b-4da6-4641-a7c2-b0417f38ee42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223833022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3223833022 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1818405053 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 28111647003 ps |
CPU time | 26.58 seconds |
Started | Jul 28 05:00:36 PM PDT 24 |
Finished | Jul 28 05:01:03 PM PDT 24 |
Peak memory | 221856 kb |
Host | smart-d24f2b85-6732-4006-b803-c5e83f78b02b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818405053 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1818405053 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4092596949 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 235935777 ps |
CPU time | 3.76 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-b2bdc5af-ceed-47aa-8aa3-368ae4b44594 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092596949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4092596949 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.9902656 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 73043593 ps |
CPU time | 2.74 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:52 PM PDT 24 |
Peak memory | 221700 kb |
Host | smart-edd270a2-125d-4b26-ab67-f92eb88d5dda |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9902656 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.9902656 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1561768833 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 326204847 ps |
CPU time | 1.38 seconds |
Started | Jul 28 05:00:53 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-3e24fe3e-05d0-4788-9f44-fa8525b39734 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561768833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1561768833 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3069144866 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 6532141799 ps |
CPU time | 9.78 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:59 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-cf7c5d65-7d24-4d2a-ae37-4dfab844bfda |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069144866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.3069144866 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3015233261 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 2804138162 ps |
CPU time | 4.73 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-ffbfb825-9f0f-44ea-82bb-be089211b2ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015233261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 015233261 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3255686359 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 401607326 ps |
CPU time | 1.04 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:00:47 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-c702aed3-bdc2-41cf-a240-ad04a850067c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255686359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 255686359 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3736862724 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 325476071 ps |
CPU time | 3.61 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-20157c65-6c0d-45cc-9ae9-bfccbdc2e852 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736862724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3736862724 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2796175976 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 108161877994 ps |
CPU time | 54.97 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:01:40 PM PDT 24 |
Peak memory | 221612 kb |
Host | smart-877707b9-b0fc-42d3-8970-ea4822930ebd |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796175976 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2796175976 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1491417420 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 461117197 ps |
CPU time | 2.54 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-2fb6b317-406c-4c70-aeb3-70af7f70ca64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491417420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1491417420 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.807029699 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 904251072 ps |
CPU time | 10.87 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:51 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-9572dcb8-3670-4a43-a700-59fab1b69a5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807029699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.807029699 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2910553096 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 357102101 ps |
CPU time | 3.69 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:48 PM PDT 24 |
Peak memory | 221584 kb |
Host | smart-20da3cc4-75df-4caa-b807-f6c671921710 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910553096 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2910553096 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2361671924 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 260604905 ps |
CPU time | 1.74 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-24d6b757-3a67-456d-be02-09756632d966 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361671924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2361671924 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4187812846 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 5365044657 ps |
CPU time | 9.27 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-b70ef47d-536f-4a61-868f-e68dbe2fc853 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187812846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.4187812846 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4241245378 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 4226381019 ps |
CPU time | 12.72 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:54 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-e6a8c60d-b267-4f47-a202-be56fe0afd5b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241245378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4 241245378 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3180293055 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 420705700 ps |
CPU time | 1.03 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:44 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-4a2c8e65-2864-4b43-86f2-cd4bf8cbceca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180293055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 180293055 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1161331885 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 481394119 ps |
CPU time | 7.63 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-d9e4e83f-221b-46f8-8c7c-109d7abb8b80 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161331885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.1161331885 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2097156909 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 51404516867 ps |
CPU time | 252.63 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:04:55 PM PDT 24 |
Peak memory | 222832 kb |
Host | smart-46cc64eb-2e51-428a-9a61-c9fca916667b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097156909 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2097156909 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3278448186 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 248567804 ps |
CPU time | 3.9 seconds |
Started | Jul 28 05:00:39 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-dfe4e851-86c3-4358-9532-e9cd0c2116dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278448186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3278448186 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3966602494 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 933271728 ps |
CPU time | 16.71 seconds |
Started | Jul 28 05:00:38 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 215580 kb |
Host | smart-35e9066f-5d0d-4c52-a08e-71b71286b58c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966602494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3966602494 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3644464605 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 346908019 ps |
CPU time | 4.11 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:02 PM PDT 24 |
Peak memory | 221556 kb |
Host | smart-78c4e07e-8b09-44ca-bbcb-fc850aa95590 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644464605 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3644464605 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.775811611 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 91405849 ps |
CPU time | 1.67 seconds |
Started | Jul 28 05:00:41 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-d63e48f8-7fc7-4c79-80f3-ddd599114894 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775811611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.775811611 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.858162614 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 73018599903 ps |
CPU time | 34.35 seconds |
Started | Jul 28 05:00:45 PM PDT 24 |
Finished | Jul 28 05:01:19 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-bba7cc5b-6930-4e36-b512-607e29660110 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858162614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r v_dm_jtag_dmi_csr_bit_bash.858162614 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4129664415 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 3307944775 ps |
CPU time | 5.6 seconds |
Started | Jul 28 05:00:44 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-7e0115ed-9b27-4baa-ae54-21b11431e9eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129664415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4 129664415 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2571755633 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 215378714 ps |
CPU time | 0.78 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:50 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-16f1df21-a8fd-4621-8ed9-59d15389a464 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571755633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 571755633 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.691726890 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 594238816 ps |
CPU time | 6.5 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:00:55 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-f3d3e23b-4d78-406d-8dc4-55244403ba11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691726890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c sr_outstanding.691726890 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1697826011 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 18552386452 ps |
CPU time | 20.7 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 219104 kb |
Host | smart-67f8b252-e400-4225-9f61-cf8ed3299eae |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697826011 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1697826011 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2847919907 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 231352027 ps |
CPU time | 2.45 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-b127ceba-7666-4303-89f7-4a561b5524ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847919907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2847919907 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2054611429 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 4544804238 ps |
CPU time | 20.58 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-a59b4dee-1244-4b81-b495-05c8c1424c9a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054611429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2054611429 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3532435498 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1086107191 ps |
CPU time | 2.24 seconds |
Started | Jul 28 05:00:47 PM PDT 24 |
Finished | Jul 28 05:00:49 PM PDT 24 |
Peak memory | 216640 kb |
Host | smart-3aa86e93-28b0-47b8-98a2-4282350101e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532435498 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3532435498 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1508465042 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 237711675 ps |
CPU time | 1.58 seconds |
Started | Jul 28 05:00:43 PM PDT 24 |
Finished | Jul 28 05:00:45 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-17b48a2b-4497-48bc-95dc-6958533fd596 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508465042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1508465042 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2811850905 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 61340202265 ps |
CPU time | 143.2 seconds |
Started | Jul 28 05:00:42 PM PDT 24 |
Finished | Jul 28 05:03:05 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-0d71ef58-5c4b-4c18-aed2-3485095665ad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811850905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2811850905 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.107482983 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 1207625459 ps |
CPU time | 4 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-44df653d-bc28-438b-8fa7-e7bfb7d10668 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107482983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.107482983 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1099011503 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 486473298 ps |
CPU time | 1.73 seconds |
Started | Jul 28 05:00:35 PM PDT 24 |
Finished | Jul 28 05:00:37 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-8a14320c-ad70-4d2e-8ece-a70ae97d4ef9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099011503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 099011503 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3948956500 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 250081844 ps |
CPU time | 3.36 seconds |
Started | Jul 28 05:00:40 PM PDT 24 |
Finished | Jul 28 05:00:43 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-617cfed8-e330-42d0-88fc-1da19fb0a4d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948956500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.3948956500 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1560451777 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 56228644412 ps |
CPU time | 97.35 seconds |
Started | Jul 28 05:00:48 PM PDT 24 |
Finished | Jul 28 05:02:26 PM PDT 24 |
Peak memory | 221656 kb |
Host | smart-6d44db40-cc6e-4983-bc54-5502814e8ed1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560451777 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1560451777 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.155910277 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 772504056 ps |
CPU time | 3.8 seconds |
Started | Jul 28 05:00:46 PM PDT 24 |
Finished | Jul 28 05:00:50 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-425cdca0-e72e-42aa-9ac7-9f5f5fd66e89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155910277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.155910277 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2255280576 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 6564454890 ps |
CPU time | 34.83 seconds |
Started | Jul 28 05:00:49 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 220876 kb |
Host | smart-a123ce1b-f370-42b2-9bc5-30eafc6e380c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255280576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2255280576 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2241250490 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 139614181 ps |
CPU time | 0.85 seconds |
Started | Jul 28 05:01:12 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-25f8be2c-c06b-45a6-95df-8f9aa6f66ac1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241250490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2241250490 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2425261418 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 33238929897 ps |
CPU time | 41.23 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:02:06 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-f694d553-862e-4727-8f14-f692b10e7097 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425261418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2425261418 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3929681821 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 1908298394 ps |
CPU time | 6.6 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:01:16 PM PDT 24 |
Peak memory | 213540 kb |
Host | smart-5c7c00b8-2562-48b1-bad2-0dc1b43f790c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929681821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3929681821 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.949861793 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 386299489 ps |
CPU time | 1.72 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-e4569e08-ebcc-42af-a9e2-1d4b42a4b5ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949861793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.949861793 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3720363063 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 184841692 ps |
CPU time | 0.99 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-e22c04a3-bd1a-478e-822e-8c9be66e1cef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720363063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3720363063 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.107396015 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 260953423 ps |
CPU time | 1.08 seconds |
Started | Jul 28 05:01:21 PM PDT 24 |
Finished | Jul 28 05:01:22 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-4338b096-1e42-4539-a6a8-ea781100cccb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107396015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.107396015 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.813866730 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 67756113 ps |
CPU time | 0.99 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:03 PM PDT 24 |
Peak memory | 215048 kb |
Host | smart-a5455918-2403-48a3-b26c-7c96ff10d0bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813866730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.813866730 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2569438824 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 9719500525 ps |
CPU time | 17.26 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-ec24f4c0-6a23-441a-81e1-b51b457bf351 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2569438824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2569438824 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1155389671 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1586014200 ps |
CPU time | 2.34 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-39b3a6b5-c64c-42de-aaf5-5837cd6e44bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155389671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1155389671 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.454357098 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 276637119 ps |
CPU time | 0.87 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-4b8a0890-0cbb-4226-9fc8-21f8f5d3a5db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454357098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.454357098 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4256991893 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 633645181 ps |
CPU time | 1.04 seconds |
Started | Jul 28 05:00:51 PM PDT 24 |
Finished | Jul 28 05:00:53 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-3ecbe1b6-7938-40f7-8d97-e382fa752600 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256991893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4256991893 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1769345372 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 854025067 ps |
CPU time | 1.05 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-430717ec-58b9-42d5-8a8d-78cebdd9f090 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769345372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1769345372 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1020037157 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 2278897740 ps |
CPU time | 6.89 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-0dddc548-d8d3-4253-859a-f9f4b8899d20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020037157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1020037157 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3317109627 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 187689531 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-e0db87f6-2f80-437e-b2bc-1c8f6624abdf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317109627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3317109627 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1367934118 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 5020862129 ps |
CPU time | 3.26 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-94b66541-53f2-454b-99c6-5afd66eb4ece |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1367934118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1367934118 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.250834889 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 750081655 ps |
CPU time | 1.64 seconds |
Started | Jul 28 05:00:56 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-0f191e90-0565-4852-9080-5fb1b92b8d07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250834889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.250834889 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1768074946 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 186609678 ps |
CPU time | 1.19 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:03 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-4f162898-7a23-4f3b-be52-4d3ee18eb977 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768074946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1768074946 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.532194878 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 5491308216 ps |
CPU time | 7.44 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-1560bbfb-f4fb-43cd-8096-6d1fe773af17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532194878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.532194878 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1049913376 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 5957122070 ps |
CPU time | 13.21 seconds |
Started | Jul 28 05:00:56 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-4067bc26-4b01-40ee-a7f9-467d2331a4c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049913376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1049913376 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.4052492447 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 658066210 ps |
CPU time | 1.68 seconds |
Started | Jul 28 05:00:56 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 228792 kb |
Host | smart-2a69fd37-e628-49b7-9cab-a9e5fac6ae0c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052492447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.4052492447 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.474241733 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 666834024 ps |
CPU time | 1.93 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-7ba5fde1-7ec8-4127-b6a6-9ff691028ada |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474241733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.474241733 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.601863148 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 13210352981 ps |
CPU time | 29.21 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:27 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-64324d31-f192-43c3-8072-9bc1b1886b92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601863148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.601863148 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.1597562216 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 337959277412 ps |
CPU time | 1257.64 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:21:59 PM PDT 24 |
Peak memory | 239500 kb |
Host | smart-10b3651a-3a95-4372-a155-bedf58b2e989 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597562216 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.1597562216 |
Directory | /workspace/0.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.3825236526 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 161024894 ps |
CPU time | 1.08 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:00:56 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-789b69f6-8ab8-4bc1-8983-2b0c955a471d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825236526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3825236526 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2298291841 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 105532457498 ps |
CPU time | 287.27 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:05:45 PM PDT 24 |
Peak memory | 217096 kb |
Host | smart-9808a0da-dd59-4dd7-8c1f-75652129be89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298291841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2298291841 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1774787879 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 4101744639 ps |
CPU time | 13.41 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-38916aaa-6240-4f90-80e7-e4f21af603d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774787879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1774787879 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.1744521497 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 272872404 ps |
CPU time | 1 seconds |
Started | Jul 28 05:00:52 PM PDT 24 |
Finished | Jul 28 05:00:54 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-677dde43-542a-4350-b07d-e63bb85e38e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744521497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1744521497 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.3703877422 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 211680977 ps |
CPU time | 0.81 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-ca66830c-9cd7-4408-9287-00fab9b79675 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703877422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3703877422 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.113715169 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 867280289 ps |
CPU time | 1.22 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-0cd86232-fe01-4cd5-99af-bc024de3626c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113715169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.113715169 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3279717712 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 148739613 ps |
CPU time | 0.97 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-725c96b6-2825-4798-914b-44e566011d18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279717712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3279717712 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3186913156 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 66942846 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-993e2d1a-0956-4d8a-bd27-f51c4c095e47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186913156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3186913156 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.134684252 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 65326944 ps |
CPU time | 0.92 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 215096 kb |
Host | smart-e2cb9140-4f8f-452c-9718-ed9c98413ccc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134684252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.134684252 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2333265705 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 3504636007 ps |
CPU time | 9.76 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:18 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-5fb5fc5b-b049-47f7-bd7c-fc2487f84a5b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2333265705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.2333265705 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.508168540 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 443401123 ps |
CPU time | 1.7 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:03 PM PDT 24 |
Peak memory | 204872 kb |
Host | smart-59a1ffb4-3a90-45bf-b978-b2d94375a5f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508168540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.508168540 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2502499717 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 524357717 ps |
CPU time | 1.42 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-cb814d4f-ed96-4ec4-b698-a0a1878705a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502499717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2502499717 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.3233743892 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 182455616 ps |
CPU time | 1.18 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:15 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-0130b339-d4a1-4a7d-a51e-5a6fbecb768f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233743892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3233743892 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2839749662 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 307775258 ps |
CPU time | 0.87 seconds |
Started | Jul 28 05:00:59 PM PDT 24 |
Finished | Jul 28 05:01:00 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-50e933a7-9f85-4b4d-8712-7e158bfcf084 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839749662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2839749662 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1073289234 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 517278301 ps |
CPU time | 1.09 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-0af9cb3f-be98-4187-8f80-32cded0f50a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1073289234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1073289234 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2323167213 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1773542803 ps |
CPU time | 1.39 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-b1d25a96-ef30-4b84-a38d-d5745f44a045 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323167213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2323167213 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.653338612 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 154987278 ps |
CPU time | 1.1 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-47408036-bf19-4e74-8512-e24f4b4667f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653338612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.653338612 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4239519084 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 505256688 ps |
CPU time | 1.11 seconds |
Started | Jul 28 05:01:16 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-ba90debf-dddd-4c9a-b741-a9356f205cd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239519084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4239519084 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1368322845 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 5022605166 ps |
CPU time | 13.89 seconds |
Started | Jul 28 05:00:55 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-9780e396-2b2e-4ebf-a109-baf58b10f222 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368322845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1368322845 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.2505970042 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 355602218 ps |
CPU time | 1.1 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 213100 kb |
Host | smart-6b7bc539-3bce-4ffe-9efa-b4f100ac8e3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505970042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2505970042 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.844479696 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 758502757 ps |
CPU time | 2.7 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-491b3495-593d-42a2-8003-9b65d73f2505 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844479696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.844479696 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1208595396 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 86238140 ps |
CPU time | 0.91 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-bcfb336b-42ab-4685-ae21-b2f6cc6fcc01 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208595396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1208595396 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.651124828 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 1263000396 ps |
CPU time | 3.92 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-f71d182c-66d2-450a-8ba9-d54697acd33d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651124828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.651124828 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.971429164 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 323514000 ps |
CPU time | 1.7 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 229456 kb |
Host | smart-4401fbbb-d2a3-4b6c-bc5b-784bad87eb07 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971429164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.971429164 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.2929052393 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 8367479832 ps |
CPU time | 15.64 seconds |
Started | Jul 28 05:01:11 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-c141b842-596b-49f4-8742-635850b9436a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929052393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2929052393 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2388448882 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 37872067988 ps |
CPU time | 154.84 seconds |
Started | Jul 28 05:01:12 PM PDT 24 |
Finished | Jul 28 05:03:47 PM PDT 24 |
Peak memory | 220856 kb |
Host | smart-1867d20f-ec14-43bb-ad6f-1d24c2bdbdaa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388448882 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2388448882 |
Directory | /workspace/1.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1846286846 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 103799115 ps |
CPU time | 0.74 seconds |
Started | Jul 28 05:01:16 PM PDT 24 |
Finished | Jul 28 05:01:16 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-95fa64fa-2853-4f3b-8d6a-277ff3dadebc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846286846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1846286846 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2077461043 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 46348522254 ps |
CPU time | 62.72 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:02:06 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-86c07559-3437-4533-8ba5-6f0f79e30a60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077461043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2077461043 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1113062718 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1544207994 ps |
CPU time | 3.11 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-c1880158-0e27-4dcb-9411-58ff3a3554b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113062718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1113062718 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3311040598 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 5345141703 ps |
CPU time | 14.64 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-409d1e72-1783-4b3a-9f9d-3cc444da43da |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3311040598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.3311040598 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.103293605 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1989468002 ps |
CPU time | 2.41 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-2d530e87-21b9-4bb5-96cb-9e6aac70d85f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103293605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.103293605 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.4173344111 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 3821552685 ps |
CPU time | 6.51 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-ee270094-6215-40e2-a790-f3ec5147c534 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173344111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4173344111 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1455374630 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 71469912 ps |
CPU time | 0.89 seconds |
Started | Jul 28 05:01:11 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-ed569a5b-30dd-4f04-9204-a0e3f119de97 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455374630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1455374630 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1068412594 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 3553119506 ps |
CPU time | 11.48 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 214880 kb |
Host | smart-b74cac3f-47d2-4ddd-bd0e-bb1b6972ee35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068412594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1068412594 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1846707119 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 7959459167 ps |
CPU time | 6.68 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-66de855f-c9d7-41ea-a683-78308b4a2c72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846707119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1846707119 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3940622068 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3237171644 ps |
CPU time | 8.4 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-a74e0f4d-0fac-41f7-a11a-e827c008ff40 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3940622068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3940622068 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2939355020 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 5839125621 ps |
CPU time | 5.2 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-665a5888-adb9-492f-8121-168513cc2937 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939355020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2939355020 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.2887374812 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 34729539 ps |
CPU time | 0.78 seconds |
Started | Jul 28 05:00:57 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-3e361e00-f46c-48c5-9b8a-ebb32f0256de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887374812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2887374812 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.690994002 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 10018601592 ps |
CPU time | 28.82 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:29 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-cc379e5a-68e8-443e-8d1b-8e6a998e5443 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690994002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.690994002 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2623898068 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 2533310565 ps |
CPU time | 2.51 seconds |
Started | Jul 28 05:01:15 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 221708 kb |
Host | smart-a3cdf71d-8ce9-4dba-88f8-fd13e09eb858 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623898068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2623898068 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.1758212856 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 7170877226 ps |
CPU time | 3.22 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 213672 kb |
Host | smart-ef0081f9-920f-4379-b16e-26a0da9bba6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758212856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1758212856 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1056149069 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 66901399 ps |
CPU time | 0.69 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-3187aef4-d417-4b01-9376-ea33c5e2054a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056149069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1056149069 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2916651014 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 5478146847 ps |
CPU time | 17.88 seconds |
Started | Jul 28 05:01:15 PM PDT 24 |
Finished | Jul 28 05:01:33 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-d5acee51-5018-4b96-a8da-5f9feabb0512 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916651014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2916651014 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2275620715 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 5910209972 ps |
CPU time | 3.95 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-a6bbcdcd-61fc-4d32-ab3f-5075914415d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275620715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2275620715 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3821084947 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 3918935887 ps |
CPU time | 11.06 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-b15714a7-6255-4c69-9ded-1a97582eae30 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3821084947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.3821084947 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.3076820084 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1684177098 ps |
CPU time | 3.07 seconds |
Started | Jul 28 05:01:17 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-83a91156-a195-4d99-adfe-d251121927a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3076820084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3076820084 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.657163565 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 4745788929 ps |
CPU time | 7.21 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-12ae8531-2e97-4a80-bc49-191f1b9d79fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657163565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.657163565 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.4273150094 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 80153083 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-fd2db22e-50b6-4f26-b8ce-02ae53fc9c1f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273150094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4273150094 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4067250226 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 5673360730 ps |
CPU time | 4.66 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:30 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-23b93a66-572a-4314-b479-8fa067f7bc0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067250226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4067250226 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1639266991 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 7291488052 ps |
CPU time | 12.18 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-49704b6e-b8bf-4573-b681-2a355113bebc |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1639266991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.1639266991 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.2442192303 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 4681235058 ps |
CPU time | 5.87 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-655e8356-0bd3-4f79-8ee9-50e02bb65137 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442192303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2442192303 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.3063323886 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 138602374 ps |
CPU time | 0.82 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-b3df98e5-587e-4768-8ba6-c833497cc6e6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063323886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3063323886 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.4284548986 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1484609421 ps |
CPU time | 1.45 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-18f55020-6ded-45c6-869a-db9537b22bd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284548986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4284548986 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2752699559 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 14553956639 ps |
CPU time | 24.25 seconds |
Started | Jul 28 05:01:12 PM PDT 24 |
Finished | Jul 28 05:01:37 PM PDT 24 |
Peak memory | 215432 kb |
Host | smart-09846a3e-9c4a-4cf5-ae7f-5c74b5cd0ce3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2752699559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.2752699559 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.582619018 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 7341320339 ps |
CPU time | 2.5 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:23 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-1f2fbcfc-fe58-453c-9297-919be492a068 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582619018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.582619018 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2937364568 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 132560768 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:32 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-c40323a2-b414-4bc3-91e0-4bd65bf295e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937364568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2937364568 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.811560787 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 5888923158 ps |
CPU time | 5.05 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:37 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-010c5738-ba10-4cee-8420-5875d2eadfed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811560787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.811560787 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.711481907 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 1219754957 ps |
CPU time | 2.17 seconds |
Started | Jul 28 05:01:21 PM PDT 24 |
Finished | Jul 28 05:01:23 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-375d58cb-c474-4d02-a914-cf20e67814ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711481907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.711481907 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1403925095 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 6500922708 ps |
CPU time | 17.75 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-7c4f8e39-24fc-4949-916f-f72f1bd75d27 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1403925095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.1403925095 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.276141155 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 2522917218 ps |
CPU time | 5.3 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-74392e7a-0668-4a74-8282-eb1a99e8bb2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276141155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.276141155 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.708714922 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 11011688812 ps |
CPU time | 3.7 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-52b021c9-842a-4b74-8c03-8f056f9bebba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708714922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.708714922 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.743241964 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 87489011 ps |
CPU time | 0.7 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-1913c7eb-abf8-4b5b-831c-c58815677d02 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743241964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.743241964 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3021868455 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 41854880858 ps |
CPU time | 41.04 seconds |
Started | Jul 28 05:01:16 PM PDT 24 |
Finished | Jul 28 05:01:57 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-4b571420-bf98-4239-9e3d-2d9157d732f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021868455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3021868455 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3993258672 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 4254393927 ps |
CPU time | 11.66 seconds |
Started | Jul 28 05:01:18 PM PDT 24 |
Finished | Jul 28 05:01:30 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-6dfaba18-efea-456f-ba3b-00cf134f8b79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993258672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3993258672 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4251992785 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 5535489994 ps |
CPU time | 2.58 seconds |
Started | Jul 28 05:01:35 PM PDT 24 |
Finished | Jul 28 05:01:38 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-d9b2f2d7-1f70-40ee-8ccb-74cd2cc76bdf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4251992785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.4251992785 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.1265028194 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 9862300334 ps |
CPU time | 28.64 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:42 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-943cb1bc-e758-4862-90f9-9eb558cf9bad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265028194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1265028194 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.1471239360 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 11985321200 ps |
CPU time | 10.68 seconds |
Started | Jul 28 05:01:18 PM PDT 24 |
Finished | Jul 28 05:01:29 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-97f4d31a-5ce4-4d85-ac32-c08b3b3167ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471239360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1471239360 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.912493419 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 43007050 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-62fc344c-715e-4542-a764-97738b898820 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912493419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.912493419 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4119465210 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 4325359028 ps |
CPU time | 6.79 seconds |
Started | Jul 28 05:01:11 PM PDT 24 |
Finished | Jul 28 05:01:18 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-86e0c072-d60f-4f30-904e-409547fc0724 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119465210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4119465210 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3967792266 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 7670006291 ps |
CPU time | 11.43 seconds |
Started | Jul 28 05:01:26 PM PDT 24 |
Finished | Jul 28 05:01:38 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-e28b5211-b8a8-471c-a50d-e4dbeacaa7b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967792266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3967792266 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3840887497 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 2093394339 ps |
CPU time | 6.47 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-b7077556-6430-4677-866d-342f833a9720 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3840887497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3840887497 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1616854608 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 3286979004 ps |
CPU time | 2.24 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:22 PM PDT 24 |
Peak memory | 205580 kb |
Host | smart-b5523cee-075d-4738-980d-a03e0ca8ec47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1616854608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1616854608 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.3957656750 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 4784325305 ps |
CPU time | 14.36 seconds |
Started | Jul 28 05:01:18 PM PDT 24 |
Finished | Jul 28 05:01:33 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-f6c38fdf-2816-477a-a128-440cc125eac2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957656750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3957656750 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.1998563601 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 69329640 ps |
CPU time | 0.8 seconds |
Started | Jul 28 05:01:36 PM PDT 24 |
Finished | Jul 28 05:01:37 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-e87dbc8b-c4e6-492d-98fb-decc4d7e7496 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998563601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1998563601 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2579756195 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 30428341799 ps |
CPU time | 48.2 seconds |
Started | Jul 28 05:01:22 PM PDT 24 |
Finished | Jul 28 05:02:10 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-2a8bfab4-d692-4f51-a979-3b555dee882d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579756195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2579756195 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2476469031 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 5075906265 ps |
CPU time | 4.37 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:29 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-b92e7210-3b8c-4dbd-bdca-090b7e971c46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476469031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2476469031 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2160460658 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 3928882720 ps |
CPU time | 3.43 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:18 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-a56bff83-b1cb-4108-a51a-5cb73be4b1ec |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2160460658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2160460658 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.947957553 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1173592551 ps |
CPU time | 1.14 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:10 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-40a0db83-fb9b-4bba-a46a-7a7df91d2101 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947957553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.947957553 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3330128808 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1853509127 ps |
CPU time | 3.02 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-59b30883-1411-4ad8-928f-fd0994d5ca7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330128808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3330128808 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1132546251 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 177882063 ps |
CPU time | 0.77 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-1063a642-6734-49a6-adbf-49b47d06caa2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132546251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1132546251 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3708823 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1474350462 ps |
CPU time | 2.11 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 214440 kb |
Host | smart-b955e7e9-92e7-492a-9860-f74a61fa5cda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3708823 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.328394511 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2770173327 ps |
CPU time | 8.34 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-8bf496cb-889f-47c0-a365-3a724a643165 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=328394511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.328394511 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2416752611 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 359291355 ps |
CPU time | 1.63 seconds |
Started | Jul 28 05:00:56 PM PDT 24 |
Finished | Jul 28 05:00:58 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-042a3f1a-c8ad-476c-acd6-684dc1e68f6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416752611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2416752611 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.4258501443 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 1299058295 ps |
CPU time | 1.89 seconds |
Started | Jul 28 05:00:59 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-9dd009a1-c0b4-4bf2-a93f-60c5a093bfbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258501443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4258501443 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.875081098 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 8560980260 ps |
CPU time | 17.61 seconds |
Started | Jul 28 05:00:54 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-b4294f27-460f-40cf-9a4a-74acca3299c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875081098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.875081098 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1435946241 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 35321948517 ps |
CPU time | 371.17 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:07:16 PM PDT 24 |
Peak memory | 229780 kb |
Host | smart-2cff84e7-094a-44df-b5f8-2fa895019201 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435946241 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1435946241 |
Directory | /workspace/2.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.2556617622 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 185102544 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-66a296fa-a1b0-455b-b4bc-0543a7bcc4d9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556617622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2556617622 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.1412865546 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 2646970484 ps |
CPU time | 4.55 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:19 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-d66ef514-d8ae-4568-9172-f392c4cedd4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412865546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1412865546 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.1715411651 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 39926658 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-89faff5e-1d54-4a2d-8ae9-5d6d21db62c1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715411651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1715411651 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.986148476 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 4129373930 ps |
CPU time | 12.68 seconds |
Started | Jul 28 05:01:34 PM PDT 24 |
Finished | Jul 28 05:01:47 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-d2c12a8c-c85a-4ad4-8857-676892d24197 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986148476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.986148476 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.3106419272 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 43825870 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:19 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-3ebf8b32-a385-4ff9-aea1-3a4e4e9eac1e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106419272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3106419272 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.2500678047 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 144877240 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:01:22 PM PDT 24 |
Finished | Jul 28 05:01:23 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-32a187e5-faaa-4465-a453-f0efa650c695 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500678047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2500678047 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.705413522 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 146519582 ps |
CPU time | 0.81 seconds |
Started | Jul 28 05:01:26 PM PDT 24 |
Finished | Jul 28 05:01:27 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-38c5dcc9-582c-43de-ad32-4456140b4efe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705413522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.705413522 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.4267396018 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 66318692 ps |
CPU time | 0.78 seconds |
Started | Jul 28 05:01:31 PM PDT 24 |
Finished | Jul 28 05:01:32 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-5efa8a91-27d8-4137-a6e5-ca12ebb57894 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267396018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4267396018 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.3954465294 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 50512396 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:21 PM PDT 24 |
Finished | Jul 28 05:01:22 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-8b465068-8664-4239-a575-da2c7c7d02de |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954465294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3954465294 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.508738090 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 70577002 ps |
CPU time | 0.81 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-c75f0a8b-199c-40e4-b27a-ad166b9cca64 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508738090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.508738090 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.572051836 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 6155723071 ps |
CPU time | 6.31 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:30 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-9c7ca492-a7e0-4a1e-9a3e-a66ae198147e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572051836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.572051836 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.3859318670 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 169778132 ps |
CPU time | 0.68 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:21 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-e5517df6-982a-451e-bcb6-8d5e7f78133f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859318670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3859318670 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.233622369 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1284989231 ps |
CPU time | 1.66 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-8361a24d-3e04-4836-bb9e-2c2d2667f45b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233622369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.233622369 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.768353150 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 233089341 ps |
CPU time | 0.74 seconds |
Started | Jul 28 05:01:35 PM PDT 24 |
Finished | Jul 28 05:01:35 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-03dbc680-1f15-4e6e-9fc5-202561950571 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768353150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.768353150 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3707963254 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 120111882 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-1992b7eb-75f6-4a32-8bf2-cddcaa6a831c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707963254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3707963254 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3524802009 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 9118123893 ps |
CPU time | 10.5 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-23369168-a687-4c95-b8d2-431b4f63d49c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524802009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3524802009 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.728620364 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 2508428866 ps |
CPU time | 3.73 seconds |
Started | Jul 28 05:01:11 PM PDT 24 |
Finished | Jul 28 05:01:15 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-a409e2c1-1676-4e8e-bfa1-6f8b2ce39399 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728620364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.728620364 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3846594657 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 1230975595 ps |
CPU time | 4.36 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:05 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-49d925ae-cfeb-4850-8be1-4a7d614392a9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3846594657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3846594657 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.3462614124 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 222164390 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:00 PM PDT 24 |
Finished | Jul 28 05:01:01 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-6e499f40-f929-4739-8063-7bfe085bb510 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462614124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3462614124 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1510161329 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1947181647 ps |
CPU time | 5.6 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:12 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-94a5a1ab-5a06-4825-ae19-505f2f31d6e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510161329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1510161329 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3790010678 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 214691516 ps |
CPU time | 1.32 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 228576 kb |
Host | smart-c7e9ed8d-6491-42c2-8e80-3df39acb6a8f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790010678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3790010678 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.374480709 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 46272592 ps |
CPU time | 0.74 seconds |
Started | Jul 28 05:01:44 PM PDT 24 |
Finished | Jul 28 05:01:45 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-5405f7e7-5f74-45a6-a670-e9ac67037606 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374480709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.374480709 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.3046060810 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 41913350 ps |
CPU time | 0.77 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-4ea09013-c7ab-47e7-97d2-2d512e865b6a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046060810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3046060810 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.3510403319 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 4316354363 ps |
CPU time | 7.46 seconds |
Started | Jul 28 05:01:37 PM PDT 24 |
Finished | Jul 28 05:01:44 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-60a7e835-396a-4a70-9db6-5097466ed821 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510403319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3510403319 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.1923622470 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 49606490 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-ce23c6d2-dcc1-4ae7-ae3c-ae4895fcc505 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923622470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1923622470 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.962489682 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 5396201436 ps |
CPU time | 14.38 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-9510ba0e-dac1-4168-9e68-dd6269ff5fe2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962489682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.962489682 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.887016042 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 38843841 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:33 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-1afc9943-0846-44e1-a0c1-13d2b88bc432 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887016042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.887016042 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.1607096352 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 33050213 ps |
CPU time | 0.77 seconds |
Started | Jul 28 05:01:27 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-f7f6f7c1-e001-4452-9138-31a9104051ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607096352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1607096352 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3058579360 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 3496523388 ps |
CPU time | 3.48 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 221576 kb |
Host | smart-9f242956-c7bf-4428-91c7-7b229d5cae53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058579360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3058579360 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.3579025249 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 87542449 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:15 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-8867622f-c697-4cff-82d1-29ac5b915669 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579025249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3579025249 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.3629216444 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 7716490576 ps |
CPU time | 10.29 seconds |
Started | Jul 28 05:01:12 PM PDT 24 |
Finished | Jul 28 05:01:22 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-32a7d241-bb70-41d0-b8a9-d2069b8d04ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629216444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3629216444 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2040885783 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 131599837 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:27 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-59d5a58c-5c49-40f3-81b4-1754bd0f60e2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040885783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2040885783 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.1110316090 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 9490379523 ps |
CPU time | 7.63 seconds |
Started | Jul 28 05:01:33 PM PDT 24 |
Finished | Jul 28 05:01:46 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-ec339d80-5602-4ce1-a28d-6d24d92025ea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110316090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1110316090 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3874018261 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 29351738 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:37 PM PDT 24 |
Finished | Jul 28 05:01:38 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-963814f9-5c6b-4722-825b-5b0a95228523 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874018261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3874018261 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.1817954078 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 12238815496 ps |
CPU time | 6.9 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:39 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-a6465e64-63cc-47f3-bb07-2184d5fad460 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817954078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1817954078 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1575434946 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 156661217 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:33 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-4be68c32-a65d-41fd-a5f5-69d6e3679a24 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575434946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1575434946 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.1423611812 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 8768529311 ps |
CPU time | 26.28 seconds |
Started | Jul 28 05:01:42 PM PDT 24 |
Finished | Jul 28 05:02:08 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-178eba64-e3dc-4820-b0a1-7de91d52330a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423611812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1423611812 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.990241816 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 39184639 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-ebb4a4a7-1ee0-4781-90e7-14ad2393ad73 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990241816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.990241816 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.4251855004 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 8579118105 ps |
CPU time | 12.9 seconds |
Started | Jul 28 05:01:21 PM PDT 24 |
Finished | Jul 28 05:01:34 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-d8eefd2b-d497-4aec-a2e1-d2c9987933da |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251855004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.4251855004 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.1244465314 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 68519099 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:02 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-1007cb7d-9181-42c3-ba04-7cd63e494323 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244465314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1244465314 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3321899928 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 27531424329 ps |
CPU time | 9.38 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-fa886b58-105c-472a-9094-544738de21d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321899928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3321899928 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2583680632 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 2226531995 ps |
CPU time | 2.67 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-e1e9fff7-b050-4cbe-a2af-da1508b7068e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2583680632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2583680632 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3438713693 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 10697341834 ps |
CPU time | 30.77 seconds |
Started | Jul 28 05:01:15 PM PDT 24 |
Finished | Jul 28 05:01:46 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-5832651b-f888-4b1e-93f1-dcb5705610bf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3438713693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3438713693 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1047993156 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 95769758 ps |
CPU time | 0.92 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-0c18404c-3f32-4f4d-857c-3da75daf22bd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1047993156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1047993156 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.668317171 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1841795962 ps |
CPU time | 2.82 seconds |
Started | Jul 28 05:01:31 PM PDT 24 |
Finished | Jul 28 05:01:34 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-6584db73-5049-4a04-aa4b-597a7330e48a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668317171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.668317171 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.2131616022 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 619590157 ps |
CPU time | 1.76 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:09 PM PDT 24 |
Peak memory | 229152 kb |
Host | smart-1435537f-e09b-4331-b2b1-bd41441102e9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131616022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2131616022 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.620545140 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 37201800 ps |
CPU time | 0.71 seconds |
Started | Jul 28 05:01:37 PM PDT 24 |
Finished | Jul 28 05:01:38 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-cef85cb0-3e84-4fa2-9a67-4990df812853 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620545140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.620545140 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3037467052 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 132018141 ps |
CPU time | 0.8 seconds |
Started | Jul 28 05:01:13 PM PDT 24 |
Finished | Jul 28 05:01:14 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-9bbac7be-6cad-4275-867b-bf506754e697 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037467052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3037467052 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.890076795 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 4398117150 ps |
CPU time | 4.19 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:29 PM PDT 24 |
Peak memory | 205404 kb |
Host | smart-568648dd-564c-4ee1-8396-2437efa73282 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890076795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.890076795 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.913583958 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 35813996 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:27 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-bdcbe6a4-9966-4e24-8d1b-60a1120bdfae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913583958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.913583958 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.1168165458 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 4878395050 ps |
CPU time | 13.42 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:39 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-9eb56647-55ad-462c-9e7e-9f84582619f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168165458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1168165458 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.497791123 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 76041879 ps |
CPU time | 0.76 seconds |
Started | Jul 28 05:01:44 PM PDT 24 |
Finished | Jul 28 05:01:45 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-22e3a134-7dcf-4a16-8806-8d8cc4205fcf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497791123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.497791123 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.3126252395 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 42513688 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:01:27 PM PDT 24 |
Finished | Jul 28 05:01:28 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-4e9b3b55-78ba-4b98-91ed-2bf186eeab3a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126252395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3126252395 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.3639439475 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 5088194287 ps |
CPU time | 14.88 seconds |
Started | Jul 28 05:01:35 PM PDT 24 |
Finished | Jul 28 05:01:50 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-a75a9b31-d23c-4488-90b5-4114204333e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639439475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3639439475 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.3896416760 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 160685459 ps |
CPU time | 1.11 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-a11474e5-2ea5-421f-a43d-fcbc7f9a47b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896416760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3896416760 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3943907518 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 78704487 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:24 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-b175dfb1-0d31-46d7-9629-679560c6f090 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943907518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3943907518 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.754888344 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 3669064024 ps |
CPU time | 3.96 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:18 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-c868651e-ae20-4070-aa32-13f1f244f9b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754888344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.754888344 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.2105676712 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 172518746 ps |
CPU time | 0.72 seconds |
Started | Jul 28 05:01:15 PM PDT 24 |
Finished | Jul 28 05:01:16 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-e5246a7a-119e-461f-a02d-e4f0328171dc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105676712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2105676712 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.3840141647 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 44410516 ps |
CPU time | 0.79 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-04ee6f70-0977-4305-9e5f-58e756b919fc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840141647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3840141647 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.661900651 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 20045029904 ps |
CPU time | 17.42 seconds |
Started | Jul 28 05:01:22 PM PDT 24 |
Finished | Jul 28 05:01:40 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-e66d6241-913d-46b3-8310-52ebba9e051e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661900651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.661900651 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.3334809368 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 57693736 ps |
CPU time | 0.81 seconds |
Started | Jul 28 05:01:08 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-ca153be8-745a-4e2d-8a65-e0b8f0c3e86a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334809368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3334809368 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.2390484128 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 14102820104 ps |
CPU time | 4.51 seconds |
Started | Jul 28 05:01:32 PM PDT 24 |
Finished | Jul 28 05:01:37 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-cb4e691a-1299-47fc-aa28-41707f1b45b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390484128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2390484128 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.72873280 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 120224713 ps |
CPU time | 0.99 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-9f809a7e-ede6-46c7-acc6-681946ed2b37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72873280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.72873280 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.128706494 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2848413156 ps |
CPU time | 5.32 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-997a7a55-dc9e-4039-9fc5-37ac0ab4f04b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128706494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.128706494 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3287705814 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 9260689525 ps |
CPU time | 7.4 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:01:18 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-3a67a5c4-6d1d-4f1d-acac-f481884be466 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3287705814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.3287705814 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2829618344 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 1935068305 ps |
CPU time | 1.3 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:26 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-0a5535ab-1ba0-4ef6-b69a-f6b0860c89d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829618344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2829618344 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.1617329979 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 4280033312 ps |
CPU time | 11.76 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:31 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-795fd0f0-3d45-4f8e-8b77-40df44a32bd0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617329979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1617329979 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.4043528223 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 62812210 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-09f0a1c4-ebe7-4984-8b54-a18b99eacf8e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043528223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4043528223 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3896864577 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 4392521099 ps |
CPU time | 14.6 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:20 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-631fee44-fd0e-4296-9f65-4eb872fc367a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896864577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3896864577 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3740867980 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 1185492861 ps |
CPU time | 4.65 seconds |
Started | Jul 28 05:01:25 PM PDT 24 |
Finished | Jul 28 05:01:30 PM PDT 24 |
Peak memory | 214580 kb |
Host | smart-9e74710d-ba6b-448e-8f2d-bd91b4102b98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740867980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3740867980 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2778310703 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 1108116539 ps |
CPU time | 1.87 seconds |
Started | Jul 28 05:01:01 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-cad58113-2ed0-4e0b-8aac-4a0a92b3298b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2778310703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2778310703 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2224803056 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 3666330628 ps |
CPU time | 5.53 seconds |
Started | Jul 28 05:01:02 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-0198229d-c234-4894-b0d4-ca6814407636 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224803056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2224803056 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.832121528 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 102872653 ps |
CPU time | 0.73 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:07 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-bbdfa226-357e-4e23-a730-aab4f8a3f232 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832121528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.832121528 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1095126953 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 13914745988 ps |
CPU time | 16.01 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:35 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-6aa2511b-ff90-4a01-a93f-87b5a121bd75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095126953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1095126953 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1795766462 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 4826914395 ps |
CPU time | 13.69 seconds |
Started | Jul 28 05:01:06 PM PDT 24 |
Finished | Jul 28 05:01:25 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-253ab5a0-c6f5-454c-b853-20ba9ba0baf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795766462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1795766462 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3780501137 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1680040315 ps |
CPU time | 5.75 seconds |
Started | Jul 28 05:01:12 PM PDT 24 |
Finished | Jul 28 05:01:23 PM PDT 24 |
Peak memory | 205572 kb |
Host | smart-ba792d30-852e-476b-a214-a825c29fd2f3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3780501137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.3780501137 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3692900162 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 5695513049 ps |
CPU time | 16.11 seconds |
Started | Jul 28 05:01:20 PM PDT 24 |
Finished | Jul 28 05:01:36 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-fc9cedba-834e-4c8d-a6df-51011e5013a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692900162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3692900162 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.1263195134 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 221771750630 ps |
CPU time | 1012.11 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:18:01 PM PDT 24 |
Peak memory | 232332 kb |
Host | smart-908176cc-ab7a-4d32-a2a5-f77a34feda54 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263195134 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.1263195134 |
Directory | /workspace/7.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.2828623062 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 247138856 ps |
CPU time | 0.69 seconds |
Started | Jul 28 05:01:23 PM PDT 24 |
Finished | Jul 28 05:01:24 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-f445926b-30de-4938-b8b3-f7388cd3c95d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828623062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2828623062 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1045167732 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 113611622161 ps |
CPU time | 65.05 seconds |
Started | Jul 28 05:01:10 PM PDT 24 |
Finished | Jul 28 05:02:16 PM PDT 24 |
Peak memory | 219996 kb |
Host | smart-7e81cc08-07d0-499d-80b5-5ed52a8d986a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045167732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1045167732 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2574820450 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 2113639027 ps |
CPU time | 3.83 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:13 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-983eab83-54e2-49c2-97bd-61650223add3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574820450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2574820450 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1367507022 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 2253317931 ps |
CPU time | 3 seconds |
Started | Jul 28 05:01:14 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 205316 kb |
Host | smart-1755995f-14fc-48d9-a08f-29c4a328ddce |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1367507022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.1367507022 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.1336782237 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 3259181325 ps |
CPU time | 3.26 seconds |
Started | Jul 28 05:01:05 PM PDT 24 |
Finished | Jul 28 05:01:08 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-0ca8e345-a70e-4942-8039-bb873e687305 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336782237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1336782237 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.1290760095 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 11589507281 ps |
CPU time | 9.73 seconds |
Started | Jul 28 05:01:07 PM PDT 24 |
Finished | Jul 28 05:01:17 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-39a89aa5-05a0-4605-8447-a562de3aa020 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290760095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1290760095 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1097368172 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 28737451994 ps |
CPU time | 402.88 seconds |
Started | Jul 28 05:01:04 PM PDT 24 |
Finished | Jul 28 05:07:52 PM PDT 24 |
Peak memory | 222652 kb |
Host | smart-4abc2372-4135-49ac-acdf-34e05de64748 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097368172 -assert nopost proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1097368172 |
Directory | /workspace/8.rv_dm_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.3699334981 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 106043873 ps |
CPU time | 0.75 seconds |
Started | Jul 28 05:01:03 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-689947ee-e0fb-4eec-be07-42126d1795d4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699334981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3699334981 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.17207117 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 62203881171 ps |
CPU time | 38.26 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:47 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-cd81a51b-4ec9-45ba-905d-d48d50f2aa13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17207117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.17207117 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1858430894 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2651678470 ps |
CPU time | 8.17 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:06 PM PDT 24 |
Peak memory | 213516 kb |
Host | smart-1878311d-1f8d-4ee8-b05e-99b7d8cac163 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858430894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1858430894 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2484184819 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 4874302947 ps |
CPU time | 15.92 seconds |
Started | Jul 28 05:01:19 PM PDT 24 |
Finished | Jul 28 05:01:35 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-57de42d8-c1da-4704-b763-74b162787495 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2484184819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2484184819 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.1720994125 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 930167441 ps |
CPU time | 1.66 seconds |
Started | Jul 28 05:00:58 PM PDT 24 |
Finished | Jul 28 05:01:04 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-80e1e73b-efb8-4699-b105-6d26ca21561d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720994125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1720994125 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.2867732072 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1765965149 ps |
CPU time | 2.1 seconds |
Started | Jul 28 05:01:09 PM PDT 24 |
Finished | Jul 28 05:01:11 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-33428935-a4ca-4e05-b9ec-d73496ad27f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867732072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2867732072 |
Directory | /workspace/9.rv_dm_stress_all/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |