Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	198529728	1496906	0	0
late_debug_enable_rd_A	198529728	110755	0	0
late_debug_enable_regwen_rd_A	198529728	97231	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198529728	1496906	0	0
T3	767560	148921	0	0
T4	262849	0	0	0
T5	372689	0	0	0
T7	0	138227	0	0
T8	0	117980	0	0
T12	0	187352	0	0
T17	0	138015	0	0
T19	105558	338037	0	0
T20	0	51473	0	0
T26	123667	0	0	0
T27	1761	0	0	0
T28	20635	0	0	0
T29	54170	0	0	0
T38	236736	0	0	0
T39	134362	0	0	0
T64	0	87890	0	0
T65	0	105061	0	0
T66	0	41481	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198529728	110755	0	0
T3	767560	51663	0	0
T4	262849	0	0	0
T5	372689	0	0	0
T19	105558	0	0	0
T20	0	9825	0	0
T26	123667	0	0	0
T27	1761	0	0	0
T28	20635	0	0	0
T29	54170	0	0	0
T38	236736	0	0	0
T39	134362	0	0	0
T64	0	15976	0	0
T65	0	17570	0	0
T66	0	7881	0	0
T71	0	40	0	0
T72	0	6	0	0
T75	0	32	0	0
T108	0	12	0	0
T109	0	214	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198529728	97231	0	0
T3	767560	45474	0	0
T4	262849	0	0	0
T5	372689	0	0	0
T19	105558	0	0	0
T20	0	8991	0	0
T26	123667	0	0	0
T27	1761	0	0	0
T28	20635	0	0	0
T29	54170	0	0	0
T38	236736	0	0	0
T39	134362	0	0	0
T64	0	14255	0	0
T65	0	15593	0	0
T66	0	6741	0	0
T68	0	8	0	0
T71	0	63	0	0
T72	0	7	0	0
T108	0	7	0	0
T109	0	139	0	0