Line Coverage for Module :
rv_dm
| Line No. | Total | Covered | Percent |
TOTAL | | 33 | 33 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 239 | 1 | 1 | 100.00 |
CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
CONT_ASSIGN | 288 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
ALWAYS | 320 | 11 | 11 | 100.00 |
CONT_ASSIGN | 345 | 1 | 1 | 100.00 |
CONT_ASSIGN | 432 | 1 | 1 | 100.00 |
CONT_ASSIGN | 438 | 1 | 1 | 100.00 |
CONT_ASSIGN | 440 | 1 | 1 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 523 | 1 | 1 | 100.00 |
CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
1 |
1 |
131 |
1 |
1 |
154 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
239 |
4 |
4 |
278 |
1 |
1 |
288 |
1 |
1 |
289 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
322 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
1 |
1 |
|
|
|
MISSING_ELSE |
331 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
334 |
1 |
1 |
|
|
|
MISSING_ELSE |
345 |
1 |
1 |
432 |
1 |
1 |
438 |
1 |
1 |
440 |
1 |
1 |
446 |
1 |
1 |
447 |
1 |
1 |
523 |
1 |
1 |
551 |
1 |
1 |
Cond Coverage for Module :
rv_dm
| Total | Covered | Percent |
Conditions | 47 | 36 | 76.60 |
Logical | 47 | 36 | 76.60 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 128
EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
-------1------- -------2------ ---------3--------- ---------4---------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | Covered | T26,T45,T46 |
LINE 131
SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
------------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T27,T43 |
1 | 0 | Covered | T2,T3,T27 |
1 | 1 | Covered | T2,T43,T44 |
LINE 289
EXPRESSION (ndmreset_req_qual & reset_req_en)
--------1-------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T19 |
1 | 1 | Covered | T1,T3,T4 |
LINE 325
EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
------1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 327
EXPRESSION (ndmreset_ack && ndmreset_pending_q)
------1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T19 |
LINE 331
EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
---------1-------- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T5 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T19 |
LINE 333
EXPRESSION (ndmreset_ack && lc_rst_pending_q)
------1----- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T19 |
LINE 345
EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
---------1-------- --------2------- --------3-------- ----------4--------- ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 1 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | 1 | Covered | T4,T19,T39 |
1 | 1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 1 | 0 | 1 | Covered | T1,T3,T19 |
1 | 1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | 1 | Covered | T1,T3,T19 |
LINE 440
EXPRESSION (debug_req & debug_req_en)
----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T19,T57 |
1 | 1 | Covered | T1,T3,T4 |
LINE 476
EXPRESSION (dmi_req_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
LINE 476
EXPRESSION (dmi_rsp_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 551
EXPRESSION (device_we || device_re)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T19 |
1 | 0 | Covered | T1,T3,T4 |
LINE 567
EXPRESSION (dmi_req_valid & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 567
EXPRESSION (dmi_rsp_ready & dmi_en)
------1------ ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T5 |
1 | 1 | Covered | T1,T2,T3 |
Toggle Coverage for Module :
rv_dm
| Total | Covered | Percent |
Totals |
98 |
80 |
81.63 |
Total Bits |
1140 |
1056 |
92.63 |
Total Bits 0->1 |
570 |
528 |
92.63 |
Total Bits 1->0 |
570 |
528 |
92.63 |
| | | |
Ports |
98 |
80 |
81.63 |
Port Bits |
1140 |
1056 |
92.63 |
Port Bits 0->1 |
570 |
528 |
92.63 |
Port Bits 1->0 |
570 |
528 |
92.63 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_lc_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
rst_lc_ni |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
next_dm_addr_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T3,T19,T57 |
Yes |
T3,T19,T57 |
INPUT |
lc_dft_en_i[3:0] |
No |
No |
|
No |
|
INPUT |
pinmux_hw_debug_en_i[3:0] |
Yes |
Yes |
T3,T19,T49 |
Yes |
T3,T19,T49 |
INPUT |
otp_dis_rv_dm_late_debug_i[7:0] |
Yes |
Yes |
T3,T19,T39 |
Yes |
T3,T4,T19 |
INPUT |
scanmode_i[3:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
scan_rst_ni |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
ndmreset_req_o |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
dmactive_o |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
debug_req_o |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
unavailable_i |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
regs_tl_d_i.d_ready |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T2,T3,T4 |
Yes |
T2,T3,T4 |
INPUT |
regs_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T3,T19,T37 |
Yes |
T3,T27,T19 |
INPUT |
regs_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T27,T37,T50 |
Yes |
T27,T50,T44 |
INPUT |
regs_tl_d_i.a_data[31:0] |
Yes |
Yes |
T2,T3,T27 |
Yes |
T2,T3,T27 |
INPUT |
regs_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T3,T27,T19 |
Yes |
T3,T27,T19 |
INPUT |
regs_tl_d_i.a_address[31:0] |
Yes |
Yes |
T3,T27,T19 |
Yes |
T3,T27,T19 |
INPUT |
regs_tl_d_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T5 |
Yes |
T2,T3,T5 |
INPUT |
regs_tl_d_i.a_size[1:0] |
Yes |
Yes |
T3,T27,T19 |
Yes |
T2,T3,T27 |
INPUT |
regs_tl_d_i.a_param[2:0] |
Yes |
Yes |
T27,T50,T44 |
Yes |
T27,T44,T34 |
INPUT |
regs_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
regs_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_d_o.d_error |
Yes |
Yes |
T3,T19,T8 |
Yes |
T3,T19,T8 |
OUTPUT |
regs_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T3,T19,T8 |
Yes |
T3,T19,T8 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,T3,*T5 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_data[31:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
regs_tl_d_o.d_size[1:0] |
Yes |
Yes |
T3,T27,T19 |
Yes |
T2,T3,T27 |
OUTPUT |
regs_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T3,*T19,*T8 |
Yes |
T3,T19,T8 |
OUTPUT |
regs_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
regs_tl_d_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
mem_tl_d_i.d_ready |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
mem_tl_d_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T3,T27 |
Yes |
T1,T3,T19 |
INPUT |
mem_tl_d_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T1,T3,T4 |
INPUT |
mem_tl_d_i.a_user.instr_type[3:0] |
Yes |
Yes |
T3,T19,T38 |
Yes |
T3,T19,T38 |
INPUT |
mem_tl_d_i.a_user.rsvd[4:0] |
Yes |
Yes |
T38,T49,T45 |
Yes |
T38,T49,T45 |
INPUT |
mem_tl_d_i.a_data[31:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T3,T27,T19 |
INPUT |
mem_tl_d_i.a_mask[3:0] |
Yes |
Yes |
T3,T19,T28 |
Yes |
T3,T19,T28 |
INPUT |
mem_tl_d_i.a_address[31:0] |
Yes |
Yes |
T3,T19,T38 |
Yes |
T3,T27,T19 |
INPUT |
mem_tl_d_i.a_source[7:0] |
Yes |
Yes |
T1,T3,T19 |
Yes |
T1,T3,T4 |
INPUT |
mem_tl_d_i.a_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
mem_tl_d_i.a_param[2:0] |
Yes |
Yes |
T38,T49,T45 |
Yes |
T38,T49,T45 |
INPUT |
mem_tl_d_i.a_opcode[2:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T19 |
INPUT |
mem_tl_d_i.a_valid |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
INPUT |
mem_tl_d_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
mem_tl_d_o.d_error |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T5 |
OUTPUT |
mem_tl_d_o.d_user.data_intg[6:0] |
Yes |
Yes |
T3,T19,T29 |
Yes |
T3,T19,T28 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
mem_tl_d_o.d_user.rsp_intg[6] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T3,T5 |
OUTPUT |
mem_tl_d_o.d_sink |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_source[7:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
mem_tl_d_o.d_size[1:0] |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
mem_tl_d_o.d_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T3,T5 |
OUTPUT |
mem_tl_d_o.d_opcode[2:1] |
No |
No |
|
No |
|
OUTPUT |
mem_tl_d_o.d_valid |
Yes |
Yes |
T1,T3,T4 |
Yes |
T1,T3,T4 |
OUTPUT |
sba_tl_h_o.d_ready |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.data_intg[6:0] |
Yes |
Yes |
T5,T10,T11 |
Yes |
T5,T10,T11 |
OUTPUT |
sba_tl_h_o.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[0] |
Yes |
Yes |
*T1,*T3,*T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.instr_type[2:1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_user.instr_type[3] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_user.rsvd[4:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_data[31:0] |
Yes |
Yes |
T5,T10,T11 |
Yes |
T5,T10,T11 |
OUTPUT |
sba_tl_h_o.a_mask[3:0] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_address[1:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_address[31:2] |
Yes |
Yes |
T5,T10,T11 |
Yes |
T5,T10,T11 |
OUTPUT |
sba_tl_h_o.a_source[7:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_size[1] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_param[2:0] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[0] |
Yes |
Yes |
*T5,*T10,*T11 |
Yes |
T5,T10,T11 |
OUTPUT |
sba_tl_h_o.a_opcode[1] |
No |
No |
|
No |
|
OUTPUT |
sba_tl_h_o.a_opcode[2] |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
OUTPUT |
sba_tl_h_o.a_valid |
Yes |
Yes |
T5,T10,T11 |
Yes |
T5,T10,T11 |
OUTPUT |
sba_tl_h_i.a_ready |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
sba_tl_h_i.d_error |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_user.rsp_intg[6:0] |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_data[31:0] |
Yes |
Yes |
T1,T5,T39 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_sink |
Yes |
Yes |
T1,T5,T10 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_source[7:0] |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_size[1:0] |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_param[2:0] |
Yes |
Yes |
T5,T4,T39 |
Yes |
T5,T4,T39 |
INPUT |
sba_tl_h_i.d_opcode[2:0] |
Yes |
Yes |
T1,T5,T4 |
Yes |
T1,T5,T4 |
INPUT |
sba_tl_h_i.d_valid |
Yes |
Yes |
T5,T10,T11 |
Yes |
T5,T10,T11 |
INPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T2,T26,T45 |
Yes |
T2,T26,T45 |
INPUT |
alert_rx_i[0].ping_n |
No |
No |
|
No |
|
INPUT |
alert_rx_i[0].ping_p |
No |
No |
|
No |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T2,T26,T45 |
Yes |
T2,T26,T45 |
OUTPUT |
jtag_i.tdi |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.trst_n |
Yes |
Yes |
T1,T3,T5 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tms |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_i.tck |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jtag_o.tdo_oe |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
jtag_o.tdo |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
rv_dm
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
IF |
320 |
7 |
7 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 320 if ((!rst_ni))
-2-: 325 if ((ndmreset_req && (!ndmreset_pending_q)))
-3-: 327 if ((ndmreset_ack && ndmreset_pending_q))
-4-: 331 if ((ndmreset_pending_q && lc_rst_asserted))
-5-: 333 if ((ndmreset_ack && lc_rst_pending_q))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T1,T3,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T1,T3,T19 |
0 |
0 |
0 |
- |
- |
Covered |
T1,T2,T3 |
0 |
- |
- |
1 |
- |
Covered |
T1,T3,T19 |
0 |
- |
- |
0 |
1 |
Covered |
T1,T3,T19 |
0 |
- |
- |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_dm
Assertion Details
DebugReqOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
DmactiveOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
70 |
0 |
0 |
T4 |
262849 |
0 |
0 |
0 |
T19 |
105558 |
0 |
0 |
0 |
T26 |
123667 |
20 |
0 |
0 |
T27 |
1761 |
0 |
0 |
0 |
T28 |
20635 |
0 |
0 |
0 |
T29 |
54170 |
0 |
0 |
0 |
T36 |
413509 |
0 |
0 |
0 |
T38 |
236736 |
0 |
0 |
0 |
T39 |
134362 |
0 |
0 |
0 |
T45 |
0 |
10 |
0 |
0 |
T46 |
0 |
10 |
0 |
0 |
T49 |
59791 |
0 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
10 |
0 |
0 |
FpvSecCmRomTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
0 |
0 |
0 |
FpvSecCmSbaTlLcGateFsm_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
0 |
0 |
0 |
JtagRspOTdoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11262350 |
11262205 |
0 |
0 |
T1 |
13551 |
13550 |
0 |
0 |
T2 |
240 |
240 |
0 |
0 |
T3 |
239729 |
239725 |
0 |
0 |
T4 |
8192 |
8192 |
0 |
0 |
T5 |
9730 |
9730 |
0 |
0 |
T19 |
243431 |
243430 |
0 |
0 |
T26 |
2850 |
2841 |
0 |
0 |
T27 |
445 |
445 |
0 |
0 |
T28 |
1352 |
1352 |
0 |
0 |
T29 |
1538 |
1538 |
0 |
0 |
JtagRspOTdoOeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
11262350 |
11262205 |
0 |
0 |
T1 |
13551 |
13550 |
0 |
0 |
T2 |
240 |
240 |
0 |
0 |
T3 |
239729 |
239725 |
0 |
0 |
T4 |
8192 |
8192 |
0 |
0 |
T5 |
9730 |
9730 |
0 |
0 |
T19 |
243431 |
243430 |
0 |
0 |
T26 |
2850 |
2841 |
0 |
0 |
T27 |
445 |
445 |
0 |
0 |
T28 |
1352 |
1352 |
0 |
0 |
T29 |
1538 |
1538 |
0 |
0 |
NdmresetOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
RvDmLcEnDebugVal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlMemAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlMemDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlRegsAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlRegsDValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlSbaAValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
TlSbaDReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
paramCheckNrHarts
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
248 |
248 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |