SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.35 | 100.00 | 76.60 | 92.63 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 248 | 248 | 0 | 0 |
OutputsKnown_A | 122592143 | 122539265 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 122592143 | 122537171 | 0 | 744 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 248 | 248 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 122592143 | 122539265 | 0 | 0 |
T1 | 70132 | 69901 | 0 | 0 |
T2 | 3217 | 3156 | 0 | 0 |
T3 | 767560 | 767404 | 0 | 0 |
T4 | 262849 | 262520 | 0 | 0 |
T5 | 372689 | 372333 | 0 | 0 |
T19 | 105558 | 105555 | 0 | 0 |
T26 | 123667 | 122285 | 0 | 0 |
T27 | 1761 | 1681 | 0 | 0 |
T28 | 20635 | 20585 | 0 | 0 |
T29 | 54170 | 54083 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 122592143 | 122537171 | 0 | 744 |
T1 | 70132 | 69889 | 0 | 3 |
T2 | 3217 | 3153 | 0 | 3 |
T3 | 767560 | 767402 | 0 | 3 |
T4 | 262849 | 262502 | 0 | 3 |
T5 | 372689 | 372318 | 0 | 3 |
T19 | 105558 | 105555 | 0 | 3 |
T26 | 123667 | 122222 | 0 | 3 |
T27 | 1761 | 1678 | 0 | 3 |
T28 | 20635 | 20582 | 0 | 3 |
T29 | 54170 | 54080 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |