Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
122592143 |
122539265 |
0 |
0 |
T1 |
70132 |
69901 |
0 |
0 |
T2 |
3217 |
3156 |
0 |
0 |
T3 |
767560 |
767404 |
0 |
0 |
T4 |
262849 |
262520 |
0 |
0 |
T5 |
372689 |
372333 |
0 |
0 |
T19 |
105558 |
105555 |
0 |
0 |
T26 |
123667 |
122285 |
0 |
0 |
T27 |
1761 |
1681 |
0 |
0 |
T28 |
20635 |
20585 |
0 |
0 |
T29 |
54170 |
54083 |
0 |
0 |