Unified Coverage Report :: Module :: tlul_adapter_host

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.tl_adapter_host_sba

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.14	100.00	100.00	75.71		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	100.00	100.00					100.00
u_rsp_chk	93.93	100.00	100.00	75.71			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	132	4	4	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	168	0	0
ALWAYS	178	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
96	1	1
116	1	1
118	1	1
119	1	1
120	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
141	1	1
145	1	1
149	1	1
153	1	1
168		unreachable
170		unreachable
171		unreachable
172		unreachable
173		unreachable
			==> MISSING_ELSE
178		unreachable
179		unreachable
181		unreachable

---

Cond Coverage for Module : tlul_adapter_host

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T5,T10,T11
1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T5,T10,T11
1	Covered	T1,T2,T3

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T5,T10,T11
1	Covered	T5,T10,T11

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T4
0	1	Covered	T5,T24,T61
1	0	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T24,T60
1	0	Covered	T5,T24,T60

---

Branch Coverage for Module : tlul_adapter_host

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	94	2	2	100.00
IF	132	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	94	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T24,T60
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	198529728	13929	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	198529728	13929	0	0
T4	262849	0	0	0
T5	372689	48	0	0
T10	0	116	0	0
T11	0	810	0	0
T19	105558	0	0	0
T22	0	3	0	0
T24	0	322	0	0
T26	123667	0	0	0
T27	1761	0	0	0
T28	20635	0	0	0
T29	54170	0	0	0
T36	413509	0	0	0
T38	236736	0	0	0
T39	134362	0	0	0
T50	0	89	0	0
T60	0	45	0	0
T61	0	24	0	0
T62	0	24	0	0
T63	0	38	0	0