Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	666865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

962089

1

T1

2

T3

5

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	590108	1			T1	3		T4	1		T5	8054
values[0x0]	330321	1			T3	6		T4	2		T5	12071
values[0x1]	708525	1			T1	4		T3	2		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	321566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1307388

1

T1

2

T3

6

T4

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5929	1			T5	227		T6	548		T9	523
valid_sources[0x01]	6018	1			T5	209		T6	569		T56	1
valid_sources[0x02]	6456	1			T5	228		T6	572		T140	1
valid_sources[0x03]	6993	1			T5	201		T6	550		T9	579
valid_sources[0x04]	6304	1			T5	247		T6	557		T140	1
valid_sources[0x05]	6181	1			T5	199		T6	507		T9	619
valid_sources[0x06]	6637	1			T5	226		T6	588		T9	634
valid_sources[0x07]	6313	1			T5	235		T6	592		T9	577
valid_sources[0x08]	6234	1			T5	216		T6	524		T141	14
valid_sources[0x09]	5947	1			T5	228		T31	2		T6	546
valid_sources[0x0a]	6151	1			T5	207		T6	571		T59	2
valid_sources[0x0b]	6401	1			T5	214		T6	540		T9	580
valid_sources[0x0c]	5839	1			T5	206		T6	555		T9	418
valid_sources[0x0d]	6471	1			T5	186		T6	565		T144	1
valid_sources[0x0e]	6241	1			T5	198		T6	574		T9	467
valid_sources[0x0f]	5979	1			T5	249		T16	1		T6	543
valid_sources[0x10]	6763	1			T5	212		T31	1		T6	562
valid_sources[0x11]	6533	1			T5	263		T6	516		T9	612
valid_sources[0x12]	7272	1			T5	168		T21	2		T6	534
valid_sources[0x13]	6492	1			T5	223		T6	530		T9	557
valid_sources[0x14]	6094	1			T5	214		T6	592		T9	515
valid_sources[0x15]	6611	1			T5	241		T6	605		T9	439
valid_sources[0x16]	5504	1			T5	249		T6	566		T33	1
valid_sources[0x17]	6639	1			T5	265		T6	563		T9	571
valid_sources[0x18]	7009	1			T5	223		T6	550		T9	427
valid_sources[0x19]	6537	1			T5	247		T6	571		T9	468
valid_sources[0x1a]	6624	1			T5	231		T21	2		T6	565
valid_sources[0x1b]	6108	1			T5	197		T6	520		T144	1
valid_sources[0x1c]	6765	1			T5	258		T6	525		T59	2
valid_sources[0x1d]	6594	1			T5	222		T6	531		T29	80
valid_sources[0x1e]	6532	1			T5	213		T21	1		T6	520
valid_sources[0x1f]	6646	1			T5	222		T6	544		T9	474
valid_sources[0x20]	5930	1			T5	243		T6	534		T9	426
valid_sources[0x21]	6778	1			T5	199		T6	574		T9	432
valid_sources[0x22]	6496	1			T5	256		T6	564		T9	435
valid_sources[0x23]	6246	1			T5	245		T6	558		T9	586
valid_sources[0x24]	6135	1			T1	1		T5	221		T6	595
valid_sources[0x25]	6845	1			T4	4		T5	231		T6	522
valid_sources[0x26]	6356	1			T5	225		T31	2		T6	573
valid_sources[0x27]	5885	1			T5	244		T6	573		T9	630
valid_sources[0x28]	6171	1			T5	206		T6	554		T9	505
valid_sources[0x29]	6181	1			T5	231		T6	536		T59	2
valid_sources[0x2a]	7317	1			T5	202		T21	1		T6	546
valid_sources[0x2b]	6729	1			T5	254		T31	1		T6	567
valid_sources[0x2c]	6974	1			T5	218		T6	524		T9	561
valid_sources[0x2d]	6537	1			T5	228		T27	1		T6	526
valid_sources[0x2e]	6302	1			T5	215		T31	1		T6	548
valid_sources[0x2f]	6404	1			T5	201		T6	557		T9	586
valid_sources[0x30]	6226	1			T1	1		T5	212		T6	588
valid_sources[0x31]	6571	1			T5	236		T6	533		T9	418
valid_sources[0x32]	5896	1			T5	225		T6	562		T9	482
valid_sources[0x33]	6639	1			T5	253		T30	9		T6	542
valid_sources[0x34]	6065	1			T5	238		T6	550		T111	3
valid_sources[0x35]	6844	1			T5	222		T6	571		T144	1
valid_sources[0x36]	5977	1			T5	216		T6	590		T135	1
valid_sources[0x37]	6073	1			T5	198		T27	1		T6	566
valid_sources[0x38]	6093	1			T5	197		T6	561		T34	1
valid_sources[0x39]	6694	1			T5	215		T6	525		T9	616
valid_sources[0x3a]	6691	1			T5	239		T6	544		T9	516
valid_sources[0x3b]	7096	1			T5	204		T6	572		T13	2
valid_sources[0x3c]	6207	1			T5	238		T6	582		T9	541
valid_sources[0x3d]	7046	1			T5	268		T6	542		T9	480
valid_sources[0x3e]	6606	1			T5	212		T6	562		T9	568
valid_sources[0x3f]	6017	1			T5	246		T6	600		T9	509
valid_sources[0x40]	6221	1			T5	196		T6	546		T144	1
valid_sources[0x41]	5793	1			T5	195		T6	528		T13	1
valid_sources[0x42]	6720	1			T5	215		T6	571		T9	655
valid_sources[0x43]	6316	1			T5	217		T31	1		T6	571
valid_sources[0x44]	6853	1			T5	217		T21	1		T6	532
valid_sources[0x45]	6667	1			T5	222		T6	532		T9	575
valid_sources[0x46]	6196	1			T5	232		T6	541		T9	545
valid_sources[0x47]	6010	1			T5	222		T6	558		T9	420
valid_sources[0x48]	5675	1			T5	230		T6	542		T144	1
valid_sources[0x49]	6508	1			T5	274		T6	567		T163	2
valid_sources[0x4a]	6152	1			T5	222		T27	1		T6	544
valid_sources[0x4b]	5961	1			T5	222		T6	568		T9	501
valid_sources[0x4c]	6528	1			T5	207		T36	3		T6	578
valid_sources[0x4d]	6945	1			T5	209		T6	532		T9	619
valid_sources[0x4e]	7081	1			T5	267		T6	546		T13	1
valid_sources[0x4f]	5915	1			T5	156		T6	587		T32	1
valid_sources[0x50]	6098	1			T5	244		T21	1		T6	599
valid_sources[0x51]	6261	1			T5	227		T6	551		T135	3
valid_sources[0x52]	6506	1			T5	204		T27	1		T6	570
valid_sources[0x53]	6464	1			T5	193		T6	524		T9	517
valid_sources[0x54]	6394	1			T5	244		T6	571		T37	6
valid_sources[0x55]	6914	1			T5	216		T21	1		T6	543
valid_sources[0x56]	6741	1			T5	197		T6	562		T144	1
valid_sources[0x57]	5793	1			T5	233		T6	554		T9	650
valid_sources[0x58]	6247	1			T5	213		T6	479		T33	1
valid_sources[0x59]	6476	1			T5	210		T21	1		T6	540
valid_sources[0x5a]	6251	1			T5	262		T6	542		T9	518
valid_sources[0x5b]	6166	1			T5	239		T6	577		T137	1
valid_sources[0x5c]	5923	1			T5	235		T31	1		T6	578
valid_sources[0x5d]	6351	1			T5	206		T6	544		T9	497
valid_sources[0x5e]	6486	1			T5	219		T6	540		T13	1
valid_sources[0x5f]	6896	1			T5	207		T6	561		T144	1
valid_sources[0x60]	6975	1			T5	208		T6	560		T9	464
valid_sources[0x61]	6358	1			T5	251		T6	559		T9	534
valid_sources[0x62]	6300	1			T5	269		T6	524		T9	599
valid_sources[0x63]	7068	1			T5	227		T6	566		T9	400
valid_sources[0x64]	6332	1			T5	225		T6	541		T9	496
valid_sources[0x65]	6475	1			T5	186		T27	1		T6	552
valid_sources[0x66]	5978	1			T5	219		T6	555		T33	1
valid_sources[0x67]	6616	1			T5	231		T6	521		T9	421
valid_sources[0x68]	6135	1			T5	258		T16	1		T6	543
valid_sources[0x69]	6527	1			T5	221		T6	547		T140	1
valid_sources[0x6a]	6436	1			T5	201		T6	574		T164	1
valid_sources[0x6b]	6775	1			T5	215		T31	1		T6	542
valid_sources[0x6c]	6418	1			T5	252		T6	549		T13	1
valid_sources[0x6d]	6546	1			T5	204		T6	543		T9	766
valid_sources[0x6e]	5754	1			T5	201		T6	551		T9	466
valid_sources[0x6f]	6103	1			T5	223		T27	1		T31	1
valid_sources[0x70]	6187	1			T5	180		T6	568		T9	651
valid_sources[0x71]	6798	1			T5	258		T6	546		T128	2
valid_sources[0x72]	6360	1			T5	222		T6	540		T9	582
valid_sources[0x73]	6274	1			T5	187		T6	552		T32	1
valid_sources[0x74]	6882	1			T5	219		T17	1		T16	1
valid_sources[0x75]	6736	1			T5	167		T6	528		T144	1
valid_sources[0x76]	6574	1			T5	215		T6	550		T9	491
valid_sources[0x77]	6740	1			T5	234		T6	540		T9	494
valid_sources[0x78]	5971	1			T5	245		T31	2		T6	551
valid_sources[0x79]	5600	1			T5	219		T6	548		T9	512
valid_sources[0x7a]	6578	1			T5	209		T21	1		T6	571
valid_sources[0x7b]	6482	1			T5	234		T36	2		T6	548
valid_sources[0x7c]	6704	1			T5	216		T6	592		T9	463
valid_sources[0x7d]	6070	1			T5	194		T6	552		T9	552
valid_sources[0x7e]	6120	1			T5	253		T31	3		T6	554
valid_sources[0x7f]	5900	1			T5	211		T6	527		T9	530
valid_sources[0x80]	6008	1			T5	215		T27	1		T6	518

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

388954

1

T1

2

T5

6960

T21

3

values[0x0]

all_enables

biggest_size

287349

1

T3

4

T4

1

T5

9371

values[0x1]

all_enables

biggest_size

285786

1

T3

1

T5

9782

T21

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

633581

1

T1

6

T2

10

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	171987	1			T5	11058		T6	25355		T9	24558
values[0x0]	239260	1			T1	4		T2	5		T3	3
values[0x1]	252475	1			T1	2		T2	5		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

647404

1

T1

6

T2

10

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2656	1			T5	167		T6	386		T165	1
valid_sources[0x01]	2478	1			T5	167		T6	432		T56	1
valid_sources[0x02]	2580	1			T5	137		T6	411		T130	2
valid_sources[0x03]	2643	1			T5	184		T6	390		T19	6
valid_sources[0x04]	2512	1			T5	207		T6	448		T65	3
valid_sources[0x05]	2432	1			T5	155		T6	384		T126	1
valid_sources[0x06]	2505	1			T5	189		T6	316		T13	1
valid_sources[0x07]	2607	1			T5	131		T21	1		T6	395
valid_sources[0x08]	2697	1			T5	168		T12	1		T6	388
valid_sources[0x09]	2628	1			T5	153		T6	429		T9	365
valid_sources[0x0a]	2517	1			T5	177		T6	388		T9	388
valid_sources[0x0b]	2666	1			T5	174		T6	430		T9	417
valid_sources[0x0c]	2655	1			T5	176		T6	400		T9	407
valid_sources[0x0d]	2556	1			T5	153		T6	400		T9	362
valid_sources[0x0e]	2418	1			T5	158		T6	350		T9	324
valid_sources[0x0f]	2455	1			T5	144		T6	375		T55	1
valid_sources[0x10]	2885	1			T5	147		T14	1		T6	379
valid_sources[0x11]	2768	1			T5	178		T6	410		T140	1
valid_sources[0x12]	2649	1			T5	186		T6	393		T9	397
valid_sources[0x13]	2529	1			T5	173		T6	386		T9	368
valid_sources[0x14]	2730	1			T5	137		T6	416		T9	404
valid_sources[0x15]	2641	1			T5	163		T6	383		T9	372
valid_sources[0x16]	2525	1			T5	158		T6	373		T9	425
valid_sources[0x17]	2526	1			T5	141		T6	422		T166	1
valid_sources[0x18]	2447	1			T1	6		T5	167		T6	402
valid_sources[0x19]	2692	1			T5	152		T6	406		T9	371
valid_sources[0x1a]	2539	1			T5	193		T6	366		T167	1
valid_sources[0x1b]	2480	1			T5	154		T6	345		T144	1
valid_sources[0x1c]	2894	1			T5	194		T6	397		T168	3
valid_sources[0x1d]	2444	1			T5	151		T6	384		T63	1
valid_sources[0x1e]	2655	1			T5	134		T6	422		T169	1
valid_sources[0x1f]	2726	1			T5	154		T6	388		T9	357
valid_sources[0x20]	2523	1			T5	185		T6	366		T170	4
valid_sources[0x21]	2546	1			T5	200		T36	4		T6	391
valid_sources[0x22]	2507	1			T5	162		T6	419		T9	331
valid_sources[0x23]	2623	1			T5	201		T6	427		T144	1
valid_sources[0x24]	2702	1			T5	177		T6	408		T9	408
valid_sources[0x25]	2537	1			T5	176		T6	396		T137	1
valid_sources[0x26]	2589	1			T5	181		T11	1		T6	429
valid_sources[0x27]	2571	1			T5	207		T6	363		T54	1
valid_sources[0x28]	2513	1			T5	174		T6	404		T9	408
valid_sources[0x29]	2490	1			T5	180		T6	374		T55	1
valid_sources[0x2a]	2742	1			T5	149		T6	383		T9	402
valid_sources[0x2b]	2504	1			T5	176		T6	396		T171	1
valid_sources[0x2c]	2752	1			T5	164		T6	409		T9	421
valid_sources[0x2d]	2590	1			T5	148		T6	341		T9	350
valid_sources[0x2e]	2636	1			T5	134		T6	344		T139	6
valid_sources[0x2f]	2243	1			T5	136		T6	353		T172	1
valid_sources[0x30]	2758	1			T5	179		T6	402		T9	397
valid_sources[0x31]	2664	1			T5	188		T6	374		T9	349
valid_sources[0x32]	2741	1			T5	167		T6	440		T173	1
valid_sources[0x33]	2728	1			T5	172		T6	396		T9	385
valid_sources[0x34]	2499	1			T5	139		T6	388		T130	1
valid_sources[0x35]	2621	1			T5	192		T21	1		T6	362
valid_sources[0x36]	2366	1			T5	188		T6	321		T61	8
valid_sources[0x37]	2423	1			T5	179		T16	4		T6	333
valid_sources[0x38]	2462	1			T5	141		T6	352		T9	396
valid_sources[0x39]	3024	1			T5	148		T6	390		T141	1
valid_sources[0x3a]	2485	1			T5	174		T6	346		T9	395
valid_sources[0x3b]	2383	1			T5	147		T6	376		T9	323
valid_sources[0x3c]	2749	1			T5	200		T6	332		T13	1
valid_sources[0x3d]	2607	1			T5	175		T6	384		T9	381
valid_sources[0x3e]	2499	1			T5	202		T36	2		T6	374
valid_sources[0x3f]	2652	1			T5	175		T6	417		T9	399
valid_sources[0x40]	2881	1			T5	181		T6	425		T9	370
valid_sources[0x41]	2582	1			T5	162		T6	348		T140	2
valid_sources[0x42]	2567	1			T5	149		T6	413		T164	1
valid_sources[0x43]	2786	1			T5	202		T6	387		T9	433
valid_sources[0x44]	2755	1			T5	194		T6	369		T9	376
valid_sources[0x45]	2745	1			T5	188		T21	1		T6	335
valid_sources[0x46]	2542	1			T5	139		T6	377		T9	369
valid_sources[0x47]	2465	1			T5	167		T6	400		T9	346
valid_sources[0x48]	2463	1			T5	199		T6	356		T23	2
valid_sources[0x49]	2533	1			T3	7		T5	146		T17	1
valid_sources[0x4a]	2435	1			T5	154		T6	416		T9	363
valid_sources[0x4b]	2704	1			T5	206		T6	388		T9	345
valid_sources[0x4c]	2648	1			T5	214		T6	402		T9	377
valid_sources[0x4d]	2683	1			T5	185		T6	386		T28	1
valid_sources[0x4e]	2634	1			T5	173		T6	348		T9	413
valid_sources[0x4f]	2469	1			T5	146		T6	387		T174	1
valid_sources[0x50]	2586	1			T5	181		T6	374		T167	1
valid_sources[0x51]	2569	1			T5	176		T6	380		T41	2
valid_sources[0x52]	2577	1			T5	142		T6	363		T9	341
valid_sources[0x53]	2490	1			T5	191		T6	345		T9	372
valid_sources[0x54]	2554	1			T5	156		T6	407		T9	377
valid_sources[0x55]	2351	1			T5	197		T31	1		T6	350
valid_sources[0x56]	2676	1			T5	126		T27	9		T6	455
valid_sources[0x57]	2566	1			T5	166		T6	411		T175	5
valid_sources[0x58]	2501	1			T5	170		T6	398		T66	7
valid_sources[0x59]	2623	1			T5	147		T6	371		T9	392
valid_sources[0x5a]	2804	1			T5	190		T6	377		T166	1
valid_sources[0x5b]	2708	1			T5	137		T6	376		T176	1
valid_sources[0x5c]	2622	1			T5	165		T6	412		T55	1
valid_sources[0x5d]	2537	1			T5	184		T6	378		T9	357
valid_sources[0x5e]	2565	1			T5	169		T6	412		T141	2
valid_sources[0x5f]	2734	1			T5	174		T11	4		T6	352
valid_sources[0x60]	2516	1			T5	150		T6	332		T59	1
valid_sources[0x61]	2598	1			T5	169		T6	380		T9	373
valid_sources[0x62]	2753	1			T5	212		T6	460		T167	1
valid_sources[0x63]	2682	1			T5	208		T6	433		T137	1
valid_sources[0x64]	2657	1			T2	2		T5	204		T6	341
valid_sources[0x65]	2612	1			T5	164		T6	370		T9	417
valid_sources[0x66]	2520	1			T5	124		T6	386		T126	1
valid_sources[0x67]	2574	1			T5	199		T6	353		T9	413
valid_sources[0x68]	2692	1			T5	166		T31	1		T6	441
valid_sources[0x69]	2698	1			T5	182		T6	356		T146	1
valid_sources[0x6a]	2741	1			T5	177		T31	1		T6	389
valid_sources[0x6b]	2516	1			T5	151		T6	376		T9	396
valid_sources[0x6c]	2622	1			T5	161		T6	397		T146	1
valid_sources[0x6d]	2493	1			T5	136		T6	377		T174	4
valid_sources[0x6e]	2605	1			T5	190		T6	450		T70	1
valid_sources[0x6f]	2326	1			T5	215		T6	333		T9	379
valid_sources[0x70]	2487	1			T5	190		T6	352		T9	409
valid_sources[0x71]	2806	1			T5	177		T21	3		T6	346
valid_sources[0x72]	3061	1			T5	154		T6	400		T167	1
valid_sources[0x73]	2735	1			T5	165		T6	432		T166	1
valid_sources[0x74]	2701	1			T2	3		T5	176		T6	327
valid_sources[0x75]	2617	1			T5	154		T6	388		T9	383
valid_sources[0x76]	2974	1			T5	147		T6	364		T23	2
valid_sources[0x77]	2671	1			T5	188		T6	422		T9	388
valid_sources[0x78]	2545	1			T5	151		T17	1		T6	416
valid_sources[0x79]	2815	1			T5	182		T6	408		T9	406
valid_sources[0x7a]	2519	1			T5	128		T20	3		T6	411
valid_sources[0x7b]	2575	1			T5	186		T6	429		T9	342
valid_sources[0x7c]	2639	1			T5	152		T18	1		T24	1
valid_sources[0x7d]	2492	1			T5	162		T6	395		T173	1
valid_sources[0x7e]	2371	1			T4	6		T5	174		T6	309
valid_sources[0x7f]	2711	1			T5	160		T6	430		T111	1
valid_sources[0x80]	2557	1			T5	171		T31	1		T6	397

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

160449

1

T5

10472

T6

23889

T9

23236

values[0x0]

all_enables

biggest_size

236544

1

T1

4

T2

5

T3

3

values[0x1]

all_enables

biggest_size

236588

1

T1

2

T2

5

T3

4