Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3617453

1

T1

5

T3

3

T4

3

full_word

1064927

1

T1

2

T3

5

T4

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4682080	1			T1	7		T3	8		T4	4
auto[TlIntgErrCmd]	98	1			T75	1		T77	4		T88	5
auto[TlIntgErrData]	105	1			T75	7		T77	10		T88	3
auto[TlIntgErrBoth]	97	1			T75	2		T77	6		T88	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714732

1

T1

3

T4

1

T5

15948

auto[1]

3967648

1

T1

4

T3

8

T4

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	313138	1			T1	1		T4	1		T5	8215
auto[TlIntgErrNone]	partial	auto[1]	3304034	1			T1	4		T3	3		T4	2
auto[TlIntgErrNone]	full_word	auto[0]	401458	1			T1	2		T5	7733		T21	3
auto[TlIntgErrNone]	full_word	auto[1]	663450	1			T3	5		T4	1		T5	24870
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T77	2		T88	2		T154	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T77	2		T88	3		T154	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T75	1		T154	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T151	1		T157	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T75	4		T77	5		T88	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T75	3		T77	2		T154	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T77	1		T154	1		T159	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T77	2		T152	1		T153	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T75	2		T77	5		T88	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T77	1		T88	1		T154	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T159	1		T158	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T160	1		T156	1		-	-