Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22394101 |
22392677 |
0 |
0 |
selKnown1 |
105481117 |
105479693 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22394101 |
22392677 |
0 |
0 |
T1 |
29017 |
29013 |
0 |
0 |
T2 |
311033 |
311029 |
0 |
0 |
T3 |
12094 |
12090 |
0 |
0 |
T4 |
23601 |
23597 |
0 |
0 |
T5 |
808996 |
808992 |
0 |
0 |
T11 |
35949 |
35945 |
0 |
0 |
T12 |
21055 |
21051 |
0 |
0 |
T17 |
0 |
10 |
0 |
0 |
T18 |
3257 |
3253 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
31860 |
31856 |
0 |
0 |
T24 |
434 |
430 |
0 |
0 |
T36 |
0 |
11 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105481117 |
105479693 |
0 |
0 |
T1 |
360085 |
360081 |
0 |
0 |
T2 |
437190 |
437187 |
0 |
0 |
T3 |
147308 |
147304 |
0 |
0 |
T4 |
232946 |
232942 |
0 |
0 |
T5 |
723962 |
723959 |
0 |
0 |
T11 |
489104 |
489100 |
0 |
0 |
T12 |
395082 |
395078 |
0 |
0 |
T17 |
0 |
8 |
0 |
0 |
T18 |
32976 |
32972 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
143312 |
143308 |
0 |
0 |
T24 |
2365 |
2361 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9129811 |
9129565 |
0 |
0 |
selKnown1 |
92217237 |
92216991 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9129811 |
9129565 |
0 |
0 |
T1 |
14502 |
14501 |
0 |
0 |
T2 |
155506 |
155505 |
0 |
0 |
T3 |
6041 |
6040 |
0 |
0 |
T4 |
11797 |
11796 |
0 |
0 |
T5 |
404490 |
404489 |
0 |
0 |
T11 |
17969 |
17968 |
0 |
0 |
T12 |
10526 |
10525 |
0 |
0 |
T18 |
1627 |
1626 |
0 |
0 |
T21 |
15926 |
15925 |
0 |
0 |
T24 |
216 |
215 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92217237 |
92216991 |
0 |
0 |
T1 |
345573 |
345572 |
0 |
0 |
T2 |
281664 |
281664 |
0 |
0 |
T3 |
141257 |
141256 |
0 |
0 |
T4 |
221143 |
221142 |
0 |
0 |
T5 |
319460 |
319460 |
0 |
0 |
T11 |
471125 |
471124 |
0 |
0 |
T12 |
384554 |
384553 |
0 |
0 |
T18 |
31347 |
31346 |
0 |
0 |
T21 |
127380 |
127379 |
0 |
0 |
T24 |
2147 |
2146 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
798 |
552 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
10 |
9 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
7 |
6 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
3 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
734 |
488 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
10 |
9 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
3 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
13261514 |
13261048 |
0 |
0 |
selKnown1 |
13261304 |
13260838 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13261514 |
13261048 |
0 |
0 |
T1 |
14503 |
14502 |
0 |
0 |
T2 |
155507 |
155506 |
0 |
0 |
T3 |
6041 |
6040 |
0 |
0 |
T4 |
11798 |
11797 |
0 |
0 |
T5 |
404490 |
404489 |
0 |
0 |
T11 |
17970 |
17969 |
0 |
0 |
T12 |
10527 |
10526 |
0 |
0 |
T18 |
1628 |
1627 |
0 |
0 |
T21 |
15927 |
15926 |
0 |
0 |
T24 |
216 |
215 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
13261304 |
13260838 |
0 |
0 |
T1 |
14502 |
14501 |
0 |
0 |
T2 |
155506 |
155505 |
0 |
0 |
T3 |
6041 |
6040 |
0 |
0 |
T4 |
11797 |
11796 |
0 |
0 |
T5 |
404490 |
404489 |
0 |
0 |
T11 |
17969 |
17968 |
0 |
0 |
T12 |
10526 |
10525 |
0 |
0 |
T18 |
1627 |
1626 |
0 |
0 |
T21 |
15926 |
15925 |
0 |
0 |
T24 |
216 |
215 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1978 |
1512 |
0 |
0 |
selKnown1 |
1842 |
1376 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1978 |
1512 |
0 |
0 |
T1 |
7 |
6 |
0 |
0 |
T2 |
10 |
9 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
9 |
8 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
6 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
4 |
3 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T36 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1842 |
1376 |
0 |
0 |
T1 |
5 |
4 |
0 |
0 |
T2 |
10 |
9 |
0 |
0 |
T3 |
5 |
4 |
0 |
0 |
T4 |
3 |
2 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T11 |
5 |
4 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
3 |
2 |
0 |
0 |
T24 |
1 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |