Line Coverage for Module :
tlul_lc_gate
| Line No. | Total | Covered | Percent |
TOTAL | | 51 | 51 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 144 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
ALWAYS | 153 | 6 | 6 | 100.00 |
ALWAYS | 164 | 28 | 28 | 100.00 |
ALWAYS | 230 | 10 | 10 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
85 |
1 |
1 |
144 |
3 |
3 |
149 |
1 |
1 |
150 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
171 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
|
|
|
MISSING_ELSE |
176 |
1 |
1 |
177 |
1 |
1 |
|
|
|
MISSING_ELSE |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
195 |
1 |
1 |
196 |
1 |
1 |
|
|
|
MISSING_ELSE |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
|
|
|
MISSING_ELSE |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
|
|
|
MISSING_ELSE |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
tlul_lc_gate
| Total | Covered | Percent |
Conditions | 18 | 16 | 88.89 |
Logical | 18 | 16 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T7,T1,T2 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T8,T25 |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T1,T2 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T1,T2 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T4,T5,T12 |
1 | Covered | T4,T8,T25 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T4,T5,T48 |
1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
tlul_lc_gate
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
7 |
7 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StActive |
196 |
Covered |
T1,T2,T3 |
StError |
184 |
Covered |
T7,T1,T2 |
StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StFlush |
184 |
Covered |
T4,T8,T25 |
StOutstanding |
174 |
Covered |
T4,T8,T25 |
transitions | Line No. | Covered | Tests |
StActive->StOutstanding |
174 |
Covered |
T4,T8,T25 |
StError->StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StErrorOutstanding->StActive |
211 |
Covered |
T1,T2,T3 |
StFlush->StActive |
196 |
Covered |
T4,T5,T6 |
StFlush->StError |
194 |
Covered |
T4,T8,T25 |
StOutstanding->StError |
184 |
Covered |
T4,T8,T25 |
StOutstanding->StFlush |
184 |
Covered |
T4,T8,T25 |
Branch Coverage for Module :
tlul_lc_gate
| Line No. | Total | Covered | Percent |
Branches |
|
24 |
23 |
95.83 |
IF |
144 |
2 |
2 |
100.00 |
IF |
153 |
4 |
4 |
100.00 |
CASE |
171 |
14 |
13 |
92.86 |
IF |
234 |
2 |
2 |
100.00 |
IF |
239 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 153 if ((!rst_ni))
-2-: 155 if ((a_ack && (!d_ack)))
-3-: 157 if ((d_ack && (!a_ack)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T1,T2 |
0 |
1 |
- |
Covered |
T7,T1,T2 |
0 |
0 |
1 |
Covered |
T7,T1,T2 |
0 |
0 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 171 case (state_q)
-2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-: 176 if ((outstanding_txn != '0))
-4-: 183 if ((outstanding_txn == '0))
-5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-: 195 if ((!flush_req_i))
-7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-: 210 if ((outstanding_txn == '0))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
StActive |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
StActive |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StActive |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StActive |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StOutstanding |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
StOutstanding |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T4,T5,T12 |
StFlush |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T4,T8,T25 |
StFlush |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T4,T5,T6 |
StFlush |
- |
- |
- |
0 |
0 |
- |
- |
Covered |
T4,T8,T25 |
StError |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T3 |
StError |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T7,T1,T2 |
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T5,T48 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 239 if (block_cmd)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T7,T1,T2 |
Assert Coverage for Module :
tlul_lc_gate
Assertion Details
OutStandingOvfl_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
183942040 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
183942040 |
183830068 |
0 |
0 |
T1 |
137980 |
137866 |
0 |
0 |
T2 |
235418 |
235226 |
0 |
0 |
T3 |
280680 |
280580 |
0 |
0 |
T4 |
766806 |
766478 |
0 |
0 |
T7 |
107162 |
107008 |
0 |
0 |
T8 |
9058 |
8938 |
0 |
0 |
T21 |
135792 |
134928 |
0 |
0 |
T25 |
7540 |
7396 |
0 |
0 |
T27 |
17770 |
17664 |
0 |
0 |
T28 |
4152 |
4028 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
| Line No. | Total | Covered | Percent |
TOTAL | | 51 | 44 | 86.27 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 144 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
ALWAYS | 153 | 6 | 6 | 100.00 |
ALWAYS | 164 | 28 | 21 | 75.00 |
ALWAYS | 230 | 10 | 10 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
85 |
1 |
1 |
144 |
3 |
3 |
149 |
1 |
1 |
150 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
171 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
|
|
|
MISSING_ELSE |
176 |
1 |
1 |
177 |
1 |
1 |
|
|
|
MISSING_ELSE |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
0 |
1 |
191 |
0 |
1 |
192 |
0 |
1 |
193 |
0 |
1 |
194 |
0 |
1 |
195 |
0 |
1 |
196 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
|
|
|
MISSING_ELSE |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
Exclude Annotation: VC_COV_UNR |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
|
|
|
MISSING_ELSE |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
| Total | Covered | Percent |
Conditions | 17 | 13 | 76.47 |
Logical | 17 | 13 | 76.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Covered | T1,T2,T46 |
1 | 1 | Covered | T7,T1,T2 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T7,T1,T2 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T1,T2 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T1,T2 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T4,T8,T25 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
5 |
4 |
80.00 |
(Not included in score) |
Transitions |
7 |
4 |
57.14 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StActive |
196 |
Covered |
T1,T2,T3 |
StError |
184 |
Covered |
T7,T1,T2 |
StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StFlush |
184 |
Not Covered |
|
StOutstanding |
174 |
Covered |
T4,T8,T25 |
transitions | Line No. | Covered | Tests |
StActive->StOutstanding |
174 |
Covered |
T4,T8,T25 |
StError->StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StErrorOutstanding->StActive |
211 |
Covered |
T1,T2,T3 |
StFlush->StActive |
196 |
Not Covered |
|
StFlush->StError |
194 |
Not Covered |
|
StOutstanding->StError |
184 |
Covered |
T4,T8,T25 |
StOutstanding->StFlush |
184 |
Not Covered |
|
Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
| Line No. | Total | Covered | Percent |
Branches |
|
22 |
18 |
81.82 |
IF |
144 |
2 |
2 |
100.00 |
IF |
153 |
4 |
4 |
100.00 |
CASE |
171 |
12 |
8 |
66.67 |
IF |
234 |
2 |
2 |
100.00 |
IF |
239 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 153 if ((!rst_ni))
-2-: 155 if ((a_ack && (!d_ack)))
-3-: 157 if ((d_ack && (!a_ack)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T1,T2 |
0 |
1 |
- |
Covered |
T7,T1,T2 |
0 |
0 |
1 |
Covered |
T7,T1,T2 |
0 |
0 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 171 case (state_q)
-2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-: 176 if ((outstanding_txn != '0))
-4-: 183 if ((outstanding_txn == '0))
-5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-: 195 if ((!flush_req_i))
-7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-: 210 if ((outstanding_txn == '0))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
StActive |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StActive |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StActive |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StActive |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StOutstanding |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StOutstanding |
- |
- |
0 |
- |
- |
- |
- |
Not Covered |
|
|
StFlush |
- |
- |
- |
1 |
- |
- |
- |
Not Covered |
|
|
StFlush |
- |
- |
- |
0 |
1 |
- |
- |
Not Covered |
|
|
StFlush |
- |
- |
- |
0 |
0 |
- |
- |
Excluded |
|
VC_COV_UNR |
StError |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T3 |
|
StError |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T7,T1,T2 |
|
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
0 |
Not Covered |
|
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 239 if (block_cmd)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T7,T1,T2 |
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Assertion Details
OutStandingOvfl_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91971020 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91971020 |
91915034 |
0 |
0 |
T1 |
68990 |
68933 |
0 |
0 |
T2 |
117709 |
117613 |
0 |
0 |
T3 |
140340 |
140290 |
0 |
0 |
T4 |
383403 |
383239 |
0 |
0 |
T7 |
53581 |
53504 |
0 |
0 |
T8 |
4529 |
4469 |
0 |
0 |
T21 |
67896 |
67464 |
0 |
0 |
T25 |
3770 |
3698 |
0 |
0 |
T27 |
8885 |
8832 |
0 |
0 |
T28 |
2076 |
2014 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
| Line No. | Total | Covered | Percent |
TOTAL | | 51 | 51 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
ALWAYS | 144 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
ALWAYS | 153 | 6 | 6 | 100.00 |
ALWAYS | 164 | 28 | 28 | 100.00 |
ALWAYS | 230 | 10 | 10 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
84 |
1 |
1 |
85 |
1 |
1 |
144 |
3 |
3 |
149 |
1 |
1 |
150 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
|
|
|
MISSING_ELSE |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
171 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
|
|
|
MISSING_ELSE |
176 |
1 |
1 |
177 |
1 |
1 |
|
|
|
MISSING_ELSE |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
195 |
1 |
1 |
196 |
1 |
1 |
|
|
|
MISSING_ELSE |
201 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
|
|
|
MISSING_ELSE |
208 |
1 |
1 |
209 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
Exclude Annotation: VC_COV_UNR |
|
|
|
Exclude Annotation: VC_COV_UNR |
230 |
1 |
1 |
231 |
1 |
1 |
232 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
|
|
|
MISSING_ELSE |
239 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
| Total | Covered | Percent |
Conditions | 16 | 16 | 100.00 |
Logical | 16 | 16 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 149
EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Covered | T4,T8,T25 |
1 | 1 | Covered | T4,T8,T25 |
LINE 150
EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T8,T25 |
1 | 0 | Covered | T7,T1,T2 |
1 | 1 | Covered | T4,T8,T25 |
LINE 155
EXPRESSION (a_ack && ((!d_ack)))
--1-- -----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T8,T25 |
LINE 157
EXPRESSION (d_ack && ((!a_ack)))
--1-- -----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T8,T25 |
LINE 176
EXPRESSION (outstanding_txn != '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T8,T25 |
LINE 183
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T4,T5,T12 |
1 | Covered | T4,T8,T25 |
LINE 210
EXPRESSION (outstanding_txn == '0)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T4,T5,T48 |
1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
7 |
6 |
85.71 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
StActive |
196 |
Covered |
T1,T2,T3 |
StError |
184 |
Covered |
T7,T1,T2 |
StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StFlush |
184 |
Covered |
T4,T8,T25 |
StOutstanding |
174 |
Covered |
T4,T8,T25 |
transitions | Line No. | Covered | Tests |
StActive->StOutstanding |
174 |
Covered |
T4,T8,T25 |
StError->StErrorOutstanding |
203 |
Covered |
T1,T2,T3 |
StErrorOutstanding->StActive |
211 |
Covered |
T1,T2,T3 |
StFlush->StActive |
196 |
Covered |
T4,T5,T6 |
StFlush->StError |
194 |
Covered |
T4,T8,T25 |
StOutstanding->StError |
184 |
Not Covered |
|
StOutstanding->StFlush |
184 |
Covered |
T4,T8,T25 |
Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
23 |
100.00 |
IF |
144 |
2 |
2 |
100.00 |
IF |
153 |
4 |
4 |
100.00 |
CASE |
171 |
13 |
13 |
100.00 |
IF |
234 |
2 |
2 |
100.00 |
IF |
239 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 153 if ((!rst_ni))
-2-: 155 if ((a_ack && (!d_ack)))
-3-: 157 if ((d_ack && (!a_ack)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T1,T2 |
0 |
1 |
- |
Covered |
T4,T8,T25 |
0 |
0 |
1 |
Covered |
T4,T8,T25 |
0 |
0 |
0 |
Covered |
T7,T1,T2 |
LineNo. Expression
-1-: 171 case (state_q)
-2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i))
-3-: 176 if ((outstanding_txn != '0))
-4-: 183 if ((outstanding_txn == '0))
-5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i))
-6-: 195 if ((!flush_req_i))
-7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i))
-8-: 210 if ((outstanding_txn == '0))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
StActive |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StActive |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StActive |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StActive |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
StOutstanding |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StOutstanding |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T4,T5,T12 |
|
StFlush |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T4,T8,T25 |
|
StFlush |
- |
- |
- |
0 |
1 |
- |
- |
Covered |
T4,T5,T6 |
|
StFlush |
- |
- |
- |
0 |
0 |
- |
- |
Covered |
T4,T8,T25 |
|
StError |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T2,T3 |
|
StError |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T7,T1,T2 |
|
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
StErrorOutstanding |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T4,T5,T48 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T1,T2 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 239 if (block_cmd)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T7,T1,T2 |
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Assertion Details
OutStandingOvfl_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91971020 |
0 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91971020 |
91915034 |
0 |
0 |
T1 |
68990 |
68933 |
0 |
0 |
T2 |
117709 |
117613 |
0 |
0 |
T3 |
140340 |
140290 |
0 |
0 |
T4 |
383403 |
383239 |
0 |
0 |
T7 |
53581 |
53504 |
0 |
0 |
T8 |
4529 |
4469 |
0 |
0 |
T21 |
67896 |
67464 |
0 |
0 |
T25 |
3770 |
3698 |
0 |
0 |
T27 |
8885 |
8832 |
0 |
0 |
T28 |
2076 |
2014 |
0 |
0 |