Module Definition
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Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
70.34 86.27 76.47 57.14 81.82 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.14 100.00 100.00 85.71 100.00 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1470 1470 0 0
OutputsKnown_A 551826120 551490204 0 0
gen_flops.OutputDelay_A 275913060 275739081 0 2205
gen_no_flops.OutputDelay_A 275913060 275745102 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1470 1470 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T21 6 6 0 0
T25 6 6 0 0
T27 6 6 0 0
T28 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 551826120 551490204 0 0
T1 413940 413598 0 0
T2 706254 705678 0 0
T3 842040 841740 0 0
T4 2300418 2299434 0 0
T7 321486 321024 0 0
T8 27174 26814 0 0
T21 407376 404784 0 0
T25 22620 22188 0 0
T27 53310 52992 0 0
T28 12456 12084 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 275913060 275739081 0 2205
T1 206970 206790 0 9
T2 353127 352830 0 9
T3 421020 420861 0 9
T4 1150209 1149711 0 9
T7 160743 160503 0 9
T8 13587 13398 0 9
T21 203688 202329 0 9
T25 11310 11085 0 9
T27 26655 26487 0 9
T28 6228 6033 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 275913060 275745102 0 0
T1 206970 206799 0 0
T2 353127 352839 0 0
T3 421020 420870 0 0
T4 1150209 1149717 0 0
T7 160743 160512 0 0
T8 13587 13407 0 0
T21 203688 202392 0 0
T25 11310 11094 0 0
T27 26655 26496 0 0
T28 6228 6042 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_flops.OutputDelay_A 91971020 91913027 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91913027 0 735
T1 68990 68930 0 3
T2 117709 117610 0 3
T3 140340 140287 0 3
T4 383403 383237 0 3
T7 53581 53501 0 3
T8 4529 4466 0 3
T21 67896 67443 0 3
T25 3770 3695 0 3
T27 8885 8829 0 3
T28 2076 2011 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_flops.OutputDelay_A 91971020 91913027 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91913027 0 735
T1 68990 68930 0 3
T2 117709 117610 0 3
T3 140340 140287 0 3
T4 383403 383237 0 3
T7 53581 53501 0 3
T8 4529 4466 0 3
T21 67896 67443 0 3
T25 3770 3695 0 3
T27 8885 8829 0 3
T28 2076 2011 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 5 5


Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_no_flops.OutputDelay_A 91971020 91915034 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 3 3


Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_flops.OutputDelay_A 91971020 91913027 0 735


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91913027 0 735
T1 68990 68930 0 3
T2 117709 117610 0 3
T3 140340 140287 0 3
T4 383403 383237 0 3
T7 53581 53501 0 3
T8 4529 4466 0 3
T21 67896 67443 0 3
T25 3770 3695 0 3
T27 8885 8829 0 3
T28 2076 2011 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_no_flops.OutputDelay_A 91971020 91915034 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 245 245 0 0
OutputsKnown_A 91971020 91915034 0 0
gen_no_flops.OutputDelay_A 91971020 91915034 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 245 245 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T21 1 1 0 0
T25 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 91971020 91915034 0 0
T1 68990 68933 0 0
T2 117709 117613 0 0
T3 140340 140290 0 0
T4 383403 383239 0 0
T7 53581 53504 0 0
T8 4529 4469 0 0
T21 67896 67464 0 0
T25 3770 3698 0 0
T27 8885 8832 0 0
T28 2076 2014 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%