Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	618788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

929251

1

T1

3

T4

5

T5

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611526	1			T1	1		T4	8		T5	10
values[0x0]	307112	1			T1	2		T6	12454		T22	4
values[0x1]	629401	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	312976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1235063

1

T1

3

T4

7

T5

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6109	1			T6	213		T41	2		T43	1
valid_sources[0x01]	6026	1			T6	252		T10	252		T127	1
valid_sources[0x02]	6715	1			T5	11		T6	255		T10	238
valid_sources[0x03]	5816	1			T6	229		T10	250		T8	398
valid_sources[0x04]	5770	1			T6	211		T141	1		T10	212
valid_sources[0x05]	5312	1			T6	233		T41	2		T62	3
valid_sources[0x06]	5945	1			T6	229		T10	222		T38	1
valid_sources[0x07]	6369	1			T6	249		T10	194		T8	354
valid_sources[0x08]	5763	1			T6	243		T40	1		T10	232
valid_sources[0x09]	6257	1			T6	224		T10	224		T38	1
valid_sources[0x0a]	5657	1			T6	239		T10	232		T38	1
valid_sources[0x0b]	5945	1			T6	220		T10	196		T127	1
valid_sources[0x0c]	5374	1			T6	225		T10	238		T8	396
valid_sources[0x0d]	6547	1			T6	254		T22	8		T37	2
valid_sources[0x0e]	5608	1			T6	233		T10	231		T8	388
valid_sources[0x0f]	5842	1			T6	207		T10	207		T8	348
valid_sources[0x10]	6188	1			T6	223		T10	239		T127	1
valid_sources[0x11]	5492	1			T6	240		T36	2		T10	255
valid_sources[0x12]	5974	1			T6	223		T141	1		T41	2
valid_sources[0x13]	6657	1			T6	213		T10	225		T162	4
valid_sources[0x14]	5622	1			T6	225		T141	3		T10	235
valid_sources[0x15]	6053	1			T6	237		T36	3		T141	1
valid_sources[0x16]	5673	1			T6	206		T10	223		T163	1
valid_sources[0x17]	6315	1			T6	240		T37	1		T10	205
valid_sources[0x18]	6789	1			T6	243		T10	242		T127	1
valid_sources[0x19]	5999	1			T6	215		T24	7		T10	246
valid_sources[0x1a]	6771	1			T6	216		T10	243		T38	2
valid_sources[0x1b]	5803	1			T2	1		T6	239		T37	1
valid_sources[0x1c]	5608	1			T6	215		T10	247		T38	1
valid_sources[0x1d]	6471	1			T6	244		T37	1		T10	227
valid_sources[0x1e]	6328	1			T6	214		T10	207		T8	413
valid_sources[0x1f]	5724	1			T6	248		T36	1		T141	2
valid_sources[0x20]	5978	1			T6	197		T141	1		T10	220
valid_sources[0x21]	5862	1			T6	238		T10	248		T8	360
valid_sources[0x22]	5471	1			T6	220		T141	1		T10	220
valid_sources[0x23]	6130	1			T6	229		T36	2		T10	238
valid_sources[0x24]	5471	1			T6	242		T10	229		T38	1
valid_sources[0x25]	6748	1			T6	259		T43	1		T10	248
valid_sources[0x26]	6583	1			T6	246		T141	1		T10	228
valid_sources[0x27]	6133	1			T6	223		T136	1		T43	1
valid_sources[0x28]	5935	1			T6	227		T10	210		T8	366
valid_sources[0x29]	6258	1			T6	234		T10	241		T127	2
valid_sources[0x2a]	7224	1			T6	253		T164	2		T10	217
valid_sources[0x2b]	6302	1			T6	212		T10	231		T38	2
valid_sources[0x2c]	5888	1			T6	206		T136	1		T10	226
valid_sources[0x2d]	6325	1			T6	243		T23	7		T10	237
valid_sources[0x2e]	5834	1			T6	236		T164	1		T10	237
valid_sources[0x2f]	6223	1			T6	233		T10	218		T8	354
valid_sources[0x30]	6167	1			T6	241		T10	240		T8	392
valid_sources[0x31]	7193	1			T6	216		T10	217		T127	1
valid_sources[0x32]	6217	1			T6	250		T37	1		T43	1
valid_sources[0x33]	6121	1			T6	224		T45	11		T141	1
valid_sources[0x34]	6488	1			T6	218		T10	210		T8	369
valid_sources[0x35]	6094	1			T6	225		T36	1		T9	42
valid_sources[0x36]	5906	1			T6	229		T10	223		T8	357
valid_sources[0x37]	5445	1			T6	223		T141	2		T10	221
valid_sources[0x38]	5719	1			T6	236		T10	214		T38	2
valid_sources[0x39]	5705	1			T6	222		T10	245		T165	4
valid_sources[0x3a]	5619	1			T6	236		T10	230		T38	1
valid_sources[0x3b]	6129	1			T6	221		T141	1		T10	211
valid_sources[0x3c]	5650	1			T6	249		T10	244		T8	360
valid_sources[0x3d]	6071	1			T6	214		T42	7		T10	206
valid_sources[0x3e]	6311	1			T6	219		T10	214		T8	393
valid_sources[0x3f]	5925	1			T6	208		T10	218		T8	392
valid_sources[0x40]	5945	1			T6	205		T10	219		T8	406
valid_sources[0x41]	5660	1			T6	261		T10	217		T162	2
valid_sources[0x42]	6129	1			T6	226		T166	1		T10	239
valid_sources[0x43]	6245	1			T6	209		T14	1		T10	247
valid_sources[0x44]	5987	1			T6	229		T164	4		T10	222
valid_sources[0x45]	5874	1			T6	248		T40	1		T141	1
valid_sources[0x46]	6102	1			T6	205		T62	1		T10	220
valid_sources[0x47]	6195	1			T6	221		T10	209		T38	1
valid_sources[0x48]	5937	1			T6	233		T36	1		T37	1
valid_sources[0x49]	6157	1			T6	212		T10	218		T38	2
valid_sources[0x4a]	5937	1			T6	214		T37	1		T10	226
valid_sources[0x4b]	5680	1			T6	238		T10	227		T8	378
valid_sources[0x4c]	6495	1			T6	215		T37	2		T62	1
valid_sources[0x4d]	6021	1			T6	217		T62	1		T10	252
valid_sources[0x4e]	6019	1			T6	225		T14	1		T10	231
valid_sources[0x4f]	6275	1			T6	235		T43	1		T10	206
valid_sources[0x50]	6111	1			T6	214		T43	1		T10	209
valid_sources[0x51]	6098	1			T6	217		T10	204		T8	395
valid_sources[0x52]	5569	1			T6	250		T129	20		T10	217
valid_sources[0x53]	6691	1			T6	241		T10	227		T8	397
valid_sources[0x54]	6786	1			T6	229		T10	212		T38	1
valid_sources[0x55]	5932	1			T6	234		T10	226		T8	385
valid_sources[0x56]	6530	1			T6	254		T10	242		T38	2
valid_sources[0x57]	6021	1			T6	215		T36	1		T10	220
valid_sources[0x58]	5997	1			T6	216		T167	2		T10	214
valid_sources[0x59]	6142	1			T6	210		T7	13		T10	240
valid_sources[0x5a]	6076	1			T6	226		T10	222		T38	1
valid_sources[0x5b]	5825	1			T6	213		T15	3		T141	1
valid_sources[0x5c]	5906	1			T6	219		T10	249		T8	366
valid_sources[0x5d]	5796	1			T6	225		T10	211		T8	365
valid_sources[0x5e]	6149	1			T6	234		T167	1		T141	3
valid_sources[0x5f]	5963	1			T6	219		T41	3		T10	216
valid_sources[0x60]	6348	1			T6	245		T37	1		T141	1
valid_sources[0x61]	6356	1			T6	229		T10	243		T38	1
valid_sources[0x62]	6445	1			T6	237		T10	203		T8	394
valid_sources[0x63]	5708	1			T6	216		T10	221		T8	344
valid_sources[0x64]	6680	1			T4	1		T6	224		T167	4
valid_sources[0x65]	6347	1			T6	231		T36	1		T10	191
valid_sources[0x66]	6047	1			T6	219		T14	3		T10	223
valid_sources[0x67]	5814	1			T6	222		T10	211		T8	348
valid_sources[0x68]	5597	1			T6	239		T141	2		T10	233
valid_sources[0x69]	5771	1			T6	217		T10	209		T163	1
valid_sources[0x6a]	6220	1			T6	217		T40	1		T141	1
valid_sources[0x6b]	6116	1			T6	232		T10	244		T8	348
valid_sources[0x6c]	6036	1			T6	214		T10	197		T8	364
valid_sources[0x6d]	5754	1			T6	213		T10	214		T38	1
valid_sources[0x6e]	6438	1			T6	238		T10	256		T38	1
valid_sources[0x6f]	5535	1			T6	221		T10	241		T131	1
valid_sources[0x70]	6189	1			T6	219		T10	218		T8	345
valid_sources[0x71]	5499	1			T6	218		T10	192		T131	1
valid_sources[0x72]	5902	1			T6	203		T10	247		T38	1
valid_sources[0x73]	6192	1			T6	225		T10	249		T8	391
valid_sources[0x74]	5425	1			T6	219		T10	232		T38	1
valid_sources[0x75]	5448	1			T6	227		T10	204		T8	351
valid_sources[0x76]	5669	1			T6	247		T10	260		T127	1
valid_sources[0x77]	5969	1			T6	242		T10	250		T8	379
valid_sources[0x78]	5831	1			T6	240		T10	257		T8	403
valid_sources[0x79]	5928	1			T6	212		T10	232		T131	2
valid_sources[0x7a]	6443	1			T6	228		T10	187		T8	364
valid_sources[0x7b]	5852	1			T6	279		T10	225		T8	370
valid_sources[0x7c]	5830	1			T6	237		T10	230		T8	415
valid_sources[0x7d]	5976	1			T4	1		T6	248		T10	220
valid_sources[0x7e]	5988	1			T6	255		T10	244		T127	1
valid_sources[0x7f]	6220	1			T6	234		T10	238		T8	368
valid_sources[0x80]	6143	1			T6	244		T10	216		T38	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

389473

1

T1

1

T4

5

T5

3

values[0x0]

all_enables

biggest_size

270414

1

T1

2

T6

9829

T22

3

values[0x1]

all_enables

biggest_size

269364

1

T6

9894

T26

1

T22

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

540742

1

T1

9

T2

1

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147827	1			T6	10294		T10	10237		T8	17401
values[0x0]	204103	1			T1	3		T3	4		T31	5
values[0x1]	215638	1			T1	6		T2	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14808	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

552760

1

T1

9

T2

1

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2006	1			T6	224		T10	164		T8	254
valid_sources[0x01]	2550	1			T6	62		T70	1		T10	146
valid_sources[0x02]	1881	1			T6	110		T10	139		T8	246
valid_sources[0x03]	1779	1			T6	5		T129	1		T10	136
valid_sources[0x04]	2110	1			T6	8		T129	1		T10	178
valid_sources[0x05]	2136	1			T6	124		T10	167		T8	298
valid_sources[0x06]	1927	1			T6	23		T14	1		T10	176
valid_sources[0x07]	2137	1			T6	67		T168	1		T10	176
valid_sources[0x08]	2178	1			T6	330		T169	1		T41	1
valid_sources[0x09]	2466	1			T6	145		T24	1		T10	150
valid_sources[0x0a]	2250	1			T6	101		T130	5		T10	147
valid_sources[0x0b]	1930	1			T6	165		T10	169		T8	314
valid_sources[0x0c]	2438	1			T6	111		T10	156		T8	272
valid_sources[0x0d]	2248	1			T6	132		T28	1		T10	163
valid_sources[0x0e]	2141	1			T6	148		T33	1		T10	153
valid_sources[0x0f]	1750	1			T6	1		T125	2		T10	159
valid_sources[0x10]	2058	1			T6	87		T73	1		T10	155
valid_sources[0x11]	2384	1			T6	339		T11	2		T73	1
valid_sources[0x12]	2574	1			T6	300		T36	1		T10	158
valid_sources[0x13]	2137	1			T6	166		T170	3		T10	180
valid_sources[0x14]	1939	1			T6	87		T10	172		T8	226
valid_sources[0x15]	2086	1			T6	57		T10	158		T8	333
valid_sources[0x16]	2467	1			T6	346		T10	154		T8	310
valid_sources[0x17]	1892	1			T6	67		T28	2		T10	121
valid_sources[0x18]	1877	1			T6	77		T40	1		T133	1
valid_sources[0x19]	1944	1			T6	78		T10	167		T163	1
valid_sources[0x1a]	1869	1			T6	4		T36	1		T10	192
valid_sources[0x1b]	2873	1			T6	303		T10	183		T171	1
valid_sources[0x1c]	1861	1			T6	91		T27	6		T141	1
valid_sources[0x1d]	2207	1			T32	13		T6	263		T10	155
valid_sources[0x1e]	2090	1			T6	112		T10	151		T8	289
valid_sources[0x1f]	2163	1			T6	186		T73	1		T10	154
valid_sources[0x20]	2205	1			T6	83		T10	175		T131	9
valid_sources[0x21]	2010	1			T6	118		T10	161		T8	283
valid_sources[0x22]	2020	1			T6	153		T10	187		T8	361
valid_sources[0x23]	2065	1			T6	4		T10	156		T8	295
valid_sources[0x24]	2205	1			T6	10		T141	1		T10	183
valid_sources[0x25]	2069	1			T6	10		T164	1		T10	193
valid_sources[0x26]	2560	1			T6	302		T10	147		T8	263
valid_sources[0x27]	1747	1			T5	1		T6	5		T71	1
valid_sources[0x28]	2511	1			T6	547		T13	1		T9	1
valid_sources[0x29]	2641	1			T6	254		T172	3		T10	131
valid_sources[0x2a]	2015	1			T6	220		T10	170		T8	328
valid_sources[0x2b]	1914	1			T6	276		T43	5		T10	139
valid_sources[0x2c]	1815	1			T6	84		T10	175		T8	175
valid_sources[0x2d]	1835	1			T6	9		T41	1		T10	141
valid_sources[0x2e]	2162	1			T1	9		T6	13		T10	145
valid_sources[0x2f]	1920	1			T6	107		T170	2		T10	156
valid_sources[0x30]	2082	1			T6	2		T10	145		T8	295
valid_sources[0x31]	2451	1			T6	161		T10	142		T8	317
valid_sources[0x32]	2668	1			T6	395		T10	129		T8	203
valid_sources[0x33]	2325	1			T4	1		T6	536		T10	153
valid_sources[0x34]	2137	1			T6	97		T68	2		T10	154
valid_sources[0x35]	1885	1			T6	55		T126	9		T10	145
valid_sources[0x36]	2342	1			T6	297		T10	157		T163	1
valid_sources[0x37]	2151	1			T6	142		T167	1		T10	175
valid_sources[0x38]	2456	1			T6	80		T10	169		T8	231
valid_sources[0x39]	1925	1			T3	1		T6	9		T10	157
valid_sources[0x3a]	2989	1			T6	552		T173	1		T10	179
valid_sources[0x3b]	2023	1			T6	118		T73	1		T174	1
valid_sources[0x3c]	2362	1			T6	265		T14	1		T10	171
valid_sources[0x3d]	2152	1			T6	104		T10	164		T8	241
valid_sources[0x3e]	2764	1			T6	235		T44	1		T133	3
valid_sources[0x3f]	2428	1			T6	269		T22	2		T10	148
valid_sources[0x40]	2416	1			T6	13		T10	144		T8	253
valid_sources[0x41]	2480	1			T6	309		T10	167		T8	217
valid_sources[0x42]	2888	1			T6	251		T28	1		T10	135
valid_sources[0x43]	2191	1			T6	84		T49	2		T141	2
valid_sources[0x44]	2199	1			T6	66		T13	1		T10	173
valid_sources[0x45]	2251	1			T6	35		T136	6		T10	177
valid_sources[0x46]	2417	1			T6	92		T10	135		T8	251
valid_sources[0x47]	2598	1			T6	94		T10	164		T175	1
valid_sources[0x48]	2331	1			T6	128		T68	1		T28	1
valid_sources[0x49]	2261	1			T6	62		T10	174		T175	1
valid_sources[0x4a]	2150	1			T6	6		T10	137		T8	421
valid_sources[0x4b]	2408	1			T6	639		T44	2		T10	157
valid_sources[0x4c]	2319	1			T6	141		T10	150		T8	453
valid_sources[0x4d]	2076	1			T3	9		T6	6		T33	1
valid_sources[0x4e]	1908	1			T6	114		T143	1		T10	138
valid_sources[0x4f]	2020	1			T6	168		T22	1		T129	1
valid_sources[0x50]	2155	1			T6	237		T29	6		T10	151
valid_sources[0x51]	2367	1			T6	394		T10	170		T176	1
valid_sources[0x52]	2955	1			T6	310		T10	187		T8	196
valid_sources[0x53]	2112	1			T2	1		T6	95		T10	154
valid_sources[0x54]	2003	1			T6	213		T13	1		T10	171
valid_sources[0x55]	2336	1			T6	283		T10	144		T8	294
valid_sources[0x56]	2421	1			T6	347		T10	139		T8	229
valid_sources[0x57]	2005	1			T6	144		T10	131		T8	265
valid_sources[0x58]	2163	1			T6	97		T10	156		T177	1
valid_sources[0x59]	1909	1			T6	148		T10	170		T8	214
valid_sources[0x5a]	2547	1			T6	291		T10	154		T8	356
valid_sources[0x5b]	2403	1			T6	82		T10	134		T165	1
valid_sources[0x5c]	2321	1			T6	83		T10	160		T8	321
valid_sources[0x5d]	2415	1			T6	3		T7	10		T10	164
valid_sources[0x5e]	1913	1			T6	55		T42	1		T173	1
valid_sources[0x5f]	2089	1			T6	100		T169	1		T10	163
valid_sources[0x60]	2739	1			T6	634		T44	1		T10	160
valid_sources[0x61]	2305	1			T6	169		T178	3		T10	171
valid_sources[0x62]	2259	1			T6	237		T167	1		T10	178
valid_sources[0x63]	2455	1			T6	299		T169	1		T143	1
valid_sources[0x64]	2464	1			T6	342		T50	1		T23	1
valid_sources[0x65]	2172	1			T6	2		T10	167		T171	1
valid_sources[0x66]	2869	1			T6	129		T13	1		T10	157
valid_sources[0x67]	2386	1			T6	126		T68	1		T10	144
valid_sources[0x68]	2845	1			T6	64		T10	154		T8	277
valid_sources[0x69]	1853	1			T6	36		T10	164		T8	242
valid_sources[0x6a]	1882	1			T6	16		T15	4		T143	1
valid_sources[0x6b]	2990	1			T6	222		T73	1		T10	164
valid_sources[0x6c]	2256	1			T6	209		T10	163		T8	268
valid_sources[0x6d]	2891	1			T6	270		T169	1		T10	185
valid_sources[0x6e]	2059	1			T6	99		T10	158		T8	217
valid_sources[0x6f]	2498	1			T6	288		T169	1		T10	177
valid_sources[0x70]	2095	1			T6	259		T169	1		T10	165
valid_sources[0x71]	2363	1			T6	155		T10	146		T8	230
valid_sources[0x72]	1972	1			T6	200		T10	145		T8	182
valid_sources[0x73]	2733	1			T6	98		T135	1		T10	160
valid_sources[0x74]	2042	1			T6	5		T13	1		T179	1
valid_sources[0x75]	2024	1			T6	160		T10	176		T8	222
valid_sources[0x76]	2161	1			T6	259		T12	3		T44	1
valid_sources[0x77]	2416	1			T6	249		T22	1		T49	1
valid_sources[0x78]	2791	1			T6	340		T10	196		T180	1
valid_sources[0x79]	1986	1			T6	119		T167	1		T10	166
valid_sources[0x7a]	2088	1			T6	3		T143	1		T173	1
valid_sources[0x7b]	1860	1			T6	46		T10	149		T181	1
valid_sources[0x7c]	2131	1			T6	162		T30	1		T10	130
valid_sources[0x7d]	1926	1			T6	148		T10	186		T8	278
valid_sources[0x7e]	2190	1			T6	167		T10	166		T8	311
valid_sources[0x7f]	2930	1			T6	689		T10	151		T8	265
valid_sources[0x80]	1670	1			T6	16		T10	173		T176	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

136819

1

T6

9727

T10

9652

T8

16472

values[0x0]

all_enables

biggest_size

201787

1

T1

3

T31

3

T32

3

values[0x1]

all_enables

biggest_size

202136

1

T1

6

T2

1

T4

1