Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3159392

1

T1

1

T2

1

T4

4

full_word

1020100

1

T1

3

T4

5

T5

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4179192	1			T1	4		T2	1		T4	9
auto[TlIntgErrCmd]	110	1			T117	2		T115	5		T118	3
auto[TlIntgErrData]	94	1			T117	4		T115	2		T118	5
auto[TlIntgErrBoth]	96	1			T117	4		T115	3		T118	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721570

1

T1

1

T4

8

T5

10

auto[1]

3457922

1

T1

3

T2

1

T4

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	320908	1			T4	3		T5	7		T6	9133
auto[TlIntgErrNone]	partial	auto[1]	2838209	1			T1	1		T2	1		T4	1
auto[TlIntgErrNone]	full_word	auto[0]	400533	1			T1	1		T4	5		T5	3
auto[TlIntgErrNone]	full_word	auto[1]	619542	1			T1	2		T6	25602		T26	1
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T115	1		T118	2		T152	2
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T117	1		T115	3		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T117	1		T115	1		T152	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T153	1		T155	1		T156	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T117	2		T118	3		T152	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T117	1		T115	1		T118	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T115	1		T157	1		T158	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T117	1		T153	1		T151	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T117	1		T154	2		T148	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T117	2		T115	3		T118	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T154	1		T157	1		T159	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T117	1		T149	1		T157	1