Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153477783 |
744046 |
0 |
0 |
T6 |
302141 |
52080 |
0 |
0 |
T8 |
0 |
91438 |
0 |
0 |
T10 |
0 |
54689 |
0 |
0 |
T11 |
122813 |
0 |
0 |
0 |
T12 |
46905 |
0 |
0 |
0 |
T20 |
0 |
81787 |
0 |
0 |
T21 |
0 |
86387 |
0 |
0 |
T22 |
364844 |
0 |
0 |
0 |
T26 |
12740 |
0 |
0 |
0 |
T33 |
5704 |
0 |
0 |
0 |
T49 |
29160 |
0 |
0 |
0 |
T54 |
2729 |
0 |
0 |
0 |
T55 |
13389 |
0 |
0 |
0 |
T57 |
0 |
911 |
0 |
0 |
T64 |
10938 |
0 |
0 |
0 |
T74 |
0 |
215546 |
0 |
0 |
T75 |
0 |
86337 |
0 |
0 |
T76 |
0 |
32 |
0 |
0 |
T77 |
0 |
276 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153477783 |
113663 |
0 |
0 |
T6 |
302141 |
17931 |
0 |
0 |
T10 |
0 |
17764 |
0 |
0 |
T11 |
122813 |
0 |
0 |
0 |
T12 |
46905 |
0 |
0 |
0 |
T21 |
0 |
27751 |
0 |
0 |
T22 |
364844 |
0 |
0 |
0 |
T26 |
12740 |
0 |
0 |
0 |
T33 |
5704 |
0 |
0 |
0 |
T49 |
29160 |
0 |
0 |
0 |
T54 |
2729 |
0 |
0 |
0 |
T55 |
13389 |
0 |
0 |
0 |
T64 |
10938 |
0 |
0 |
0 |
T74 |
0 |
39475 |
0 |
0 |
T76 |
0 |
15 |
0 |
0 |
T78 |
0 |
5 |
0 |
0 |
T112 |
0 |
115 |
0 |
0 |
T113 |
0 |
202 |
0 |
0 |
T114 |
0 |
13 |
0 |
0 |
T115 |
0 |
18 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153477783 |
97731 |
0 |
0 |
T6 |
302141 |
15337 |
0 |
0 |
T10 |
0 |
15044 |
0 |
0 |
T11 |
122813 |
0 |
0 |
0 |
T12 |
46905 |
0 |
0 |
0 |
T21 |
0 |
23498 |
0 |
0 |
T22 |
364844 |
0 |
0 |
0 |
T26 |
12740 |
0 |
0 |
0 |
T33 |
5704 |
0 |
0 |
0 |
T49 |
29160 |
0 |
0 |
0 |
T54 |
2729 |
0 |
0 |
0 |
T55 |
13389 |
0 |
0 |
0 |
T64 |
10938 |
0 |
0 |
0 |
T74 |
0 |
34015 |
0 |
0 |
T76 |
0 |
19 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T112 |
0 |
119 |
0 |
0 |
T113 |
0 |
210 |
0 |
0 |
T114 |
0 |
13 |
0 |
0 |
T115 |
0 |
23 |
0 |
0 |