SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 93706788 | 93651362 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93651362 | 0 | 735 |
T1 | 55786 | 55601 | 0 | 3 |
T2 | 5246 | 5160 | 0 | 3 |
T3 | 6851 | 6770 | 0 | 3 |
T4 | 9086 | 9013 | 0 | 3 |
T5 | 14032 | 13966 | 0 | 3 |
T6 | 302141 | 302007 | 0 | 3 |
T11 | 122813 | 122467 | 0 | 3 |
T31 | 3335 | 3282 | 0 | 3 |
T32 | 2441 | 2382 | 0 | 3 |
T33 | 5704 | 5634 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |