Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dmi_jtag
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.56 94.32 90.57 75.00 82.35

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.dap 85.56 94.32 90.57 75.00 82.35



Module Instance : tb.dut.dap

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.56 94.32 90.57 75.00 82.35


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.46 98.36 86.58 67.31 95.05 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.16 100.00 85.71 97.60 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_dmi_cdc 86.38 100.00 78.85 100.00 66.67
i_dmi_jtag_tap 91.18 100.00 90.91 65.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : dmi_jtag
Line No.TotalCoveredPercent
TOTAL888394.32
CONT_ASSIGN6511100.00
ALWAYS7277100.00
ALWAYS9433100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS141494489.80
CONT_ASSIGN26011100.00
ALWAYS2631212100.00
ALWAYS2871111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
72 1 1
73 1 1
74 1 1
75 1 1
MISSING_ELSE
MISSING_ELSE
88 1 1
89 2 2
MISSING_ELSE
MISSING_ELSE
94 1 1
95 1 1
97 1 1
130 1 1
131 1 1
132 1 1
133 1 1
141 1 1
142 1 1
144 1 1
145 1 1
146 1 1
147 1 1
149 1 1
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
157 1 1
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
MISSING_ELSE
MISSING_ELSE
174 1 1
175 1 1
176 1 1
==> MISSING_ELSE
182 1 1
183 1 1
185 1 1
188 0 1
189 0 1
192 1 1
193 1 1
199 1 1
MISSING_ELSE
204 1 1
206 1 1
207 1 1
==> MISSING_ELSE
213 1 1
214 1 1
215 0 1
216 1 1
219 1 1
MISSING_ELSE
MISSING_ELSE
233 1 1
234 0 1
MISSING_ELSE
240 1 1
241 1 1
MISSING_ELSE
244 1 1
245 1 1
MISSING_ELSE
248 1 1
249 0 1
MISSING_ELSE
253 1 1
254 1 1
MISSING_ELSE
260 1 1
263 1 1
264 1 1
265 1 1
267 1 1
268 1 1
269 1 1
270 1 1
272 1 1
273 1 1
MISSING_ELSE
MISSING_ELSE
MISSING_ELSE
278 1 1
279 1 1
280 1 1
MISSING_ELSE
MISSING_ELSE
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
292 1 1
294 1 1
295 1 1
296 1 1
297 1 1
298 1 1


Cond Coverage for Module : dmi_jtag
TotalCoveredPercent
Conditions534890.57
Logical534890.57
Non-Logical00
Event00

 LINE       65
 EXPRESSION (jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset))
             -------1------    ------------------------2-----------------------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T6,T14
10CoveredT1,T2,T4

 LINE       65
 SUB-EXPRESSION (dtmcs_select && update && dtmcs_q.dmihardreset)
                 ------1-----    ---2--    ----------3---------
-1--2--3-StatusTests
011CoveredT1,T6,T14
101CoveredT1,T6,T22
110CoveredT1,T6,T22
111CoveredT1,T6,T14

 LINE       133
 EXPRESSION ((state_q == Write) ? DTM_WRITE : DTM_READ)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       133
 SUB-EXPRESSION (state_q == Write)
                ---------1--------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       160
 EXPRESSION (dmi_select && update && (error_q == DMINoError))
             -----1----    ---2--    -----------3-----------
-1--2--3-StatusTests
011CoveredT1,T6,T22
101CoveredT1,T2,T4
110CoveredT6,T22,T14
111CoveredT1,T2,T4

 LINE       160
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT6,T22,T14
1CoveredT1,T2,T4

 LINE       164
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_READ)
            ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       166
 EXPRESSION (dtm_op_e'(dmi.op) == DTM_WRITE)
            ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       233
 EXPRESSION (update && (state_q != Idle))
             ---1--    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11Not Covered

 LINE       233
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       240
 EXPRESSION (capture && (state_q inside {Read, WaitReadValid}))
             ---1---    -------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT50,T10,T51

 LINE       244
 EXPRESSION (error_dmi_busy && (error_q == DMINoError))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11CoveredT6,T22,T14

 LINE       244
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT6,T22,T14
1CoveredT1,T2,T4

 LINE       248
 EXPRESSION (error_dmi_op_failed && (error_q == DMINoError))
             ---------1---------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       248
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT6,T22,T14
1CoveredT1,T2,T4

 LINE       253
 EXPRESSION (update && dtmcs_q.dmireset && dtmcs_select)
             ---1--    --------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T6,T22
101CoveredT1,T6,T36
110CoveredT6,T22,T14
111CoveredT6,T22,T14

 LINE       269
 EXPRESSION ((error_q == DMINoError) && ((!error_dmi_busy)))
             -----------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT6,T22,T14
10CoveredT50,T10,T51
11CoveredT1,T2,T4

 LINE       269
 SUB-EXPRESSION (error_q == DMINoError)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       272
 EXPRESSION ((error_q == DMIBusy) || error_dmi_busy)
             ----------1---------    -------2------
-1--2-StatusTests
00Not Covered
01CoveredT50,T10,T51
10CoveredT6,T22,T14

 LINE       272
 SUB-EXPRESSION (error_q == DMIBusy)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT6,T22,T14

FSM Coverage for Module : dmi_jtag
Summary for FSM :: error_q
TotalCoveredPercent
States 3 2 66.67 (Not included in score)
Transitions 4 2 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: error_q
statesLine No.CoveredTests
DMIBusy 245 Covered T6,T22,T14
DMINoError 292 Covered T1,T2,T4
DMIOPFailed 249 Not Covered


transitionsLine No.CoveredTests
DMIBusy->DMINoError 292 Covered T6,T22,T14
DMINoError->DMIBusy 245 Covered T6,T22,T14
DMINoError->DMIOPFailed 249 Not Covered
DMIOPFailed->DMINoError 292 Not Covered


Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 7 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Idle 289 Covered T1,T2,T4
Read 165 Covered T1,T2,T4
WaitReadValid 176 Covered T1,T2,T4
WaitWriteValid 207 Covered T1,T2,T4
Write 167 Covered T1,T2,T4


transitionsLine No.CoveredTests
Idle->Read 165 Covered T1,T2,T4
Idle->Write 167 Covered T1,T2,T4
Read->Idle 289 Covered T50,T51
Read->WaitReadValid 176 Covered T1,T2,T4
WaitReadValid->Idle 289 Covered T1,T2,T4
WaitWriteValid->Idle 289 Covered T1,T2,T4
Write->Idle 289 Not Covered
Write->WaitWriteValid 207 Covered T1,T2,T4



Branch Coverage for Module : dmi_jtag
Line No.TotalCoveredPercent
Branches 51 42 82.35
TERNARY 133 2 2 100.00
IF 73 3 3 100.00
IF 88 3 3 100.00
IF 94 2 2 100.00
IF 151 30 21 70.00
IF 264 9 9 100.00
IF 287 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 133 ((state_q == Write)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 73 if (capture) -2-: 74 if (dtmcs_select)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T4


LineNo. Expression -1-: 88 if (shift) -2-: 89 if (dtmcs_select)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T4
1 0 Covered T1,T2,T4
0 - Covered T1,T2,T4


LineNo. Expression -1-: 94 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4


LineNo. Expression -1-: 151 if (dmi_clear) -2-: 157 case (state_q) -3-: 160 if (((dmi_select && update) && (error_q == DMINoError))) -4-: 164 if ((dtm_op_e'(dmi.op) == DTM_READ)) -5-: 166 if ((dtm_op_e'(dmi.op) == DTM_WRITE)) -6-: 175 if (dmi_req_ready) -7-: 182 if (dmi_resp_valid) -8-: 183 case (dmi_resp.resp) -9-: 206 if (dmi_req_ready) -10-: 213 if (dmi_resp_valid) -11-: 214 case (dmi_resp.resp) -12-: 225 if (dmi_resp_valid) -13-: 233 if ((update && (state_q != Idle))) -14-: 240 if ((capture && (state_q inside {Read, WaitReadValid}))) -15-: 244 if ((error_dmi_busy && (error_q == DMINoError))) -16-: 248 if ((error_dmi_op_failed && (error_q == DMINoError))) -17-: 253 if (((update && dtmcs_q.dmireset) && dtmcs_select))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
1 - - - - - - - - - - - - - - - - Covered T1,T2,T4
0 Idle 1 1 - - - - - - - - - - - - - Covered T1,T2,T4
0 Idle 1 0 1 - - - - - - - - - - - - Covered T1,T2,T4
0 Idle 1 0 0 - - - - - - - - - - - - Covered T1,T2,T4
0 Idle 0 - - - - - - - - - - - - - - Covered T1,T2,T4
0 Read - - - 1 - - - - - - - - - - - Covered T1,T2,T4
0 Read - - - 0 - - - - - - - - - - - Not Covered
0 WaitReadValid - - - - 1 DTM_SUCCESS - - - - - - - - - Covered T1,T2,T4
0 WaitReadValid - - - - 1 DTM_ERR - - - - - - - - - Not Covered
0 WaitReadValid - - - - 1 DTM_BUSY - - - - - - - - - Covered T6,T7,T9
0 WaitReadValid - - - - 1 default - - - - - - - - - Not Covered
0 WaitReadValid - - - - 0 - - - - - - - - - - Covered T1,T2,T4
0 Write - - - - - - 1 - - - - - - - - Covered T1,T2,T4
0 Write - - - - - - 0 - - - - - - - - Not Covered
0 WaitWriteValid - - - - - - - 1 DTM_ERR - - - - - - Not Covered
0 WaitWriteValid - - - - - - - 1 DTM_BUSY - - - - - - Covered T6,T22,T14
0 WaitWriteValid - - - - - - - 1 default - - - - - - Covered T1,T2,T4
0 WaitWriteValid - - - - - - - 0 - - - - - - - Covered T1,T2,T4
0 default - - - - - - - - - 1 - - - - - Not Covered
0 default - - - - - - - - - 0 - - - - - Not Covered
0 - - - - - - - - - - - 1 - - - - Not Covered
0 - - - - - - - - - - - 0 - - - - Covered T1,T2,T4
0 - - - - - - - - - - - - 1 - - - Covered T50,T10,T51
0 - - - - - - - - - - - - 0 - - - Covered T1,T2,T4
0 - - - - - - - - - - - - - 1 - - Covered T6,T22,T14
0 - - - - - - - - - - - - - 0 - - Covered T1,T2,T4
0 - - - - - - - - - - - - - - 1 - Not Covered
0 - - - - - - - - - - - - - - 0 - Covered T1,T2,T4
0 - - - - - - - - - - - - - - - 1 Covered T6,T22,T14
0 - - - - - - - - - - - - - - - 0 Covered T1,T2,T4


LineNo. Expression -1-: 264 if (dmi_clear) -2-: 267 if (capture) -3-: 268 if (dmi_select) -4-: 269 if (((error_q == DMINoError) && (!error_dmi_busy))) -5-: 272 if (((error_q == DMIBusy) || error_dmi_busy)) -6-: 278 if (shift) -7-: 279 if (dmi_select)

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T1,T2,T4
0 1 1 1 - - - Covered T1,T2,T4
0 1 1 0 1 - - Covered T1,T2,T4
0 1 1 0 0 - - Covered T1,T2,T4
0 1 0 - - - - Covered T1,T2,T4
0 0 - - - - - Covered T1,T2,T4
0 - - - - 1 1 Covered T1,T2,T4
0 - - - - 1 0 Covered T1,T2,T4
0 - - - - 0 - Covered T1,T2,T4


LineNo. Expression -1-: 287 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%