Unified Coverage Report :: Module :: dm_mem

Module : dm_mem

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.50	87.89	64.52		83.33	86.25

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_mem	82.52	89.30	68.97		83.33	88.46

---

Module Instance : tb.dut.u_dm_top.i_dm_mem

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.52	89.30	68.97		83.33	88.46

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.08	89.69	70.00		83.33	89.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_dm_top

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rom_snd_scratch.i_debug_rom	100.00	100.00	100.00			100.00

Line Coverage for Module : dm_mem

	Line No.	Total	Covered	Percent
TOTAL		190	167	87.89
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
ALWAYS	148	37	37	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	239	48	46	95.83
ROUTINE	375	1	1	100.00
ALWAYS	388	15	14	93.33
ALWAYS	411	3	3	100.00
CONT_ASSIGN	418	1	1	100.00
ALWAYS	422	54	34	62.96
CONT_ASSIGN	557	1	1	100.00
ALWAYS	587	9	9	100.00
ALWAYS	601	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
120	1	1
121	1	1
122	1	1
124	1	1
125	1	1
126	1	1
127	1	1
135	1	1
136	1	1
137	1	1
138	1	1
141	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	1	1
161	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
170	1	1
			MISSING_ELSE
176	1	1
177	1	1
179	1	1
180	1	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
193	1	1
194	1	1
196	1	1
197	1	1
			MISSING_ELSE
206	1	1
207	1	1
208	1	1
			MISSING_ELSE
211	1	1
212	1	1
213	1	1
			MISSING_ELSE
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
231	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
247	1	1
248	1	1
249	1	1
250	1	1
253	1	1
254	1	1
			MISSING_ELSE
257	1	1
259	1	1
260	1	1
262	1	1
263	1	1
266	1	1
270	1	1
272	1	1
275	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
285	0	1
286	0	1
			==> MISSING_ELSE
289	1	1
			==> MISSING_ELSE
			MISSING_ELSE
301	1	1
305	1	1
306	1	1
			MISSING_ELSE
310	1	1
313	1	1
315	1	1
318	1	1
			MISSING_ELSE
324	1	1
334	1	1
341	1	1
347	1	1
349	1	1
			MISSING_ELSE
351	1	1
356	1	1
			MISSING_ELSE
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
369	1	1
375	1	1
388	1	1
389	1	1
390	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
404	1	1
405	0	1
			MISSING_ELSE
			MISSING_ELSE
411	1	1
412	1	1
414	1	1
418	1	1
422	1	1
425	1	1
427	1	1
429	1	1
430	1	1
431	1	1
432	1	1
433	1	1
434	1	1
435	1	1
436	1	1
437	1	1
440	1	1
445	1	1
447	1	1
449	1	1
450	0	1
451	0	1
454	1	1
457	0	1
459	0	1
461	0	1
463	0	1
465	1	1
467	0	1
468	0	1
471	0	1
478	1	1
480	1	1
482	1	1
484	1	1
486	1	1
488	1	1
492	1	1
493	0	1
494	0	1
497	1	1
500	0	1
502	0	1
504	0	1
506	0	1
508	1	1
510	0	1
511	0	1
514	0	1
521	1	1
523	1	1
525	1	1
527	1	1
529	1	1
533	0	1
534	0	1
			MISSING_ELSE
541	1	1
543	1	1
			MISSING_ELSE
557	1	1
587	1	1
588	1	1
589	1	1
590	1	1
591	1	1
593	1	1
594	1	1
595	1	1
596	1	1
601	1	1
602	1	1
603	1	1
605	1	1
606	1	1

---

Cond Coverage for Module : dm_mem

	Total	Covered	Percent
Conditions	62	40	64.52
Logical	62	40	64.52
Non-Logical	0	0
Event	0	0

 LINE       158
 EXPRESSION (cmd_valid_i && halted_q_aligned[hartsel] && ((!unsupported_command)))
             -----1-----    ------------2------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T34,T35
1	1	0	Covered	T6,T26,T22
1	1	1	Covered	T5,T6,T22

 LINE       168
 EXPRESSION (resumereq_aligned[hartsel] && ((!resuming_q_aligned[hartsel])) && ((!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel])
             -------------1------------    ----------------2---------------    --------------3--------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T6,T22,T24
1	0	1	1	Not Covered
1	1	0	1	Covered	T6,T36,T37
1	1	1	0	Covered	T6,T22,T24
1	1	1	1	Covered	T6,T22,T24

 LINE       206
 EXPRESSION (unsupported_command && cmd_valid_i)
             ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Covered	T6,T26,T22
1	1	Covered	T6,T26,T22

 LINE       226
 EXPRESSION (fwd_rom_q ? rom_rdata : rdata_q)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T38,T39

 LINE       231
 EXPRESSION (word_enable32_q ? word_mux[32+:32] : word_mux[0+:32])
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       280
 EXPRESSION ((addr_i[(DbgAddressBits - 1):2] - DataBaseAddr[(DbgAddressBits - 1):2]) == dc)
            ---------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T1,T6,T30
1	Covered	T1,T6,T30

 LINE       313
 EXPRESSION ((cmd_i.cmdtype == AccessRegister) && ((!ac_ar.transfer)) && ac_ar.postexec)
             ----------------1----------------    ---------2---------    -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T40,T41
1	1	0	Covered	T6,T42,T43
1	1	1	Covered	T37,T7,T44

 LINE       313
 SUB-EXPRESSION (cmd_i.cmdtype == AccessRegister)
                ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T6,T22,T24

 LINE       347
 EXPRESSION (({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0}))
            ----------------------------------------------------------------------1---------------------------------------------------------------------

-1-	Status	Tests
0	Covered	T6,T10,T8
1	Covered	T6,T22,T24

 LINE       445
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ac_ar.write)
             --------------1--------------    -------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T42,T7
1	1	0	Covered	T22,T24,T41
1	1	1	Covered	T5,T45,T14

 LINE       449
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T5,T45,T14
1	Not Covered

 LINE       454
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       454
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------

-1-	Status	Tests
0	Covered	T5,T45,T14
1	Not Covered

 LINE       486
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ((!ac_ar.write)))
             --------------1--------------    -------2------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T22,T24,T41

 LINE       492
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T22,T24,T41
1	Not Covered

 LINE       497
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       497
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------

-1-	Status	Tests
0	Covered	T22,T24,T41
1	Not Covered

 LINE       529
 EXPRESSION ((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1))
             ---------------1--------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (ac_ar.aarpostincrement == 1'b1)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       541
 EXPRESSION (ac_ar.postexec && ((!unsupported_command)))
             -------1------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T37,T14,T7

 LINE       605
 EXPRESSION (SelectableHarts & halted_d)
             -------1-------   ----2---

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T1,T2,T4

 LINE       606
 EXPRESSION (SelectableHarts & resuming_d)
             -------1-------   -----2----

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T6,T22,T24

---

FSM Coverage for Module : dm_mem

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CmdExecuting	180	Covered	T6,T22,T24
Go	160	Covered	T5,T6,T22
Idle	188	Covered	T1,T2,T4
Resume	170	Covered	T6,T22,T24

transitions	Line No.	Covered	Tests
CmdExecuting->Idle	197	Covered	T6,T22,T24
Go->CmdExecuting	180	Covered	T6,T22,T24
Go->Idle	218	Not Covered
Idle->Go	160	Covered	T5,T6,T22
Idle->Resume	170	Covered	T6,T22,T24
Resume->Idle	188	Covered	T6,T22,T24

---

Branch Coverage for Module : dm_mem

	Line No.	Total	Covered	Percent
Branches		80	69	86.25
TERNARY	226	2	2	100.00
TERNARY	231	2	2	100.00
CASE	155	12	11	91.67
IF	206	2	2	100.00
IF	211	2	2	100.00
IF	216	2	2	100.00
IF	253	2	2	100.00
IF	257	19	19	100.00
IF	363	2	2	100.00
IF	389	14	13	92.86
IF	411	2	2	100.00
CASE	440	15	6	40.00
IF	587	2	2	100.00
IF	601	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	226	(fwd_rom_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	231	(word_enable32_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	155	case (state_q)
-2-:	158	if (((cmd_valid_i && halted_q_aligned[hartsel]) && (!unsupported_command)))
-3-:	161	if (cmd_valid_i)
-4-:	168	if ((((resumereq_aligned[hartsel] && (!resuming_q_aligned[hartsel])) && (!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel]))
-5-:	179	if (going)
-6-:	187	if (resuming_q_aligned[hartsel])
-7-:	196	if (halted_aligned[hartsel])

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
Idle	1	-	-	-	-	-	Covered	T5,T6,T22
Idle	0	1	-	-	-	-	Covered	T6,T26,T22
Idle	0	0	-	-	-	-	Covered	T1,T2,T4
Idle	-	-	1	-	-	-	Covered	T6,T22,T24
Idle	-	-	0	-	-	-	Covered	T1,T2,T4
Go	-	-	-	1	-	-	Covered	T6,T22,T24
Go	-	-	-	0	-	-	Covered	T5,T6,T22
Resume	-	-	-	-	1	-	Covered	T6,T22,T24
Resume	-	-	-	-	0	-	Covered	T6,T22,T24
CmdExecuting	-	-	-	-	-	1	Covered	T6,T22,T24
CmdExecuting	-	-	-	-	-	0	Covered	T6,T22,T24
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	206	if ((unsupported_command && cmd_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T26,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	211	if (exception)

Branches:

-1-	Status	Tests
1	Covered	T16,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	216	if (ndmreset_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	253	if (clear_resumeack_i)

Branches:

-1-	Status	Tests
1	Covered	T6,T22,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	257	if (req_i)
-2-:	259	if (we_i)
-3-:	260	case (addr_i[(DbgAddressBits - 1):0])
-4-:	301	case (addr_i[(DbgAddressBits - 1):0])
-5-:	305	if (resumereq_wdata_aligned[wdata_hartsel])
-6-:	310	if (cmdbusy_o)
-7-:	313	if ((((cmd_i.cmdtype == AccessRegister) && (!ac_ar.transfer)) && ac_ar.postexec))
-8-:	347	if ((({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0})))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	1	HaltedAddr	-	-	-	-	-	Covered	T1,T2,T4
1	1	GoingAddr	-	-	-	-	-	Covered	T6,T22,T24
1	1	ResumingAddr	-	-	-	-	-	Covered	T6,T22,T24
1	1	ExceptionAddr	-	-	-	-	-	Covered	T16,T17
1	1	DataBaseAddr DataEndAddr	-	-	-	-	-	Covered	T1,T6,T30
1	1	default	-	-	-	-	-	Covered	T6,T10,T8
1	0	-	WhereToAddr	1	-	-	-	Covered	T6,T10,T21
1	0	-	WhereToAddr	0	-	-	-	Covered	T6,T22,T24
1	0	-	WhereToAddr	-	1	1	-	Covered	T37,T7,T44
1	0	-	WhereToAddr	-	1	0	-	Covered	T6,T22,T24
1	0	-	WhereToAddr	-	0	-	-	Covered	T6,T10,T8
1	0	-	DataBaseAddr DataEndAddr	-	-	-	-	Covered	T1,T6,T30
1	0	-	ProgBufBaseAddr ProgBufEndAddr	-	-	-	-	Covered	T4,T6,T10
1	0	-	AbstractCmdBaseAddr AbstractCmdEndAddr	-	-	-	-	Covered	T5,T45
1	0	-	FlagsBaseAddr FlagsEndAddr	-	-	-	1	Covered	T6,T22,T24
1	0	-	FlagsBaseAddr FlagsEndAddr	-	-	-	0	Covered	T6,T10,T8
1	0	-	RomBaseAddr RomEndAddr	-	-	-	-	Covered	T38,T39
1	0	-	default	-	-	-	-	Covered	T6,T10,T8
0	-	-	-	-	-	-	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	363	if (ndmreset_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	389	if (req_i)
-2-:	390	case (addr_i[(DbgAddressBits - 1):0])
-3-:	404	if ((addr_i[($clog2(BeWidth) - 1):0] != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	WhereToAddr	-	Covered	T6,T22,T24
1	HaltedAddr	-	Covered	T1,T2,T4
1	GoingAddr	-	Covered	T6,T22,T24
1	ResumingAddr	-	Covered	T6,T22,T24
1	ExceptionAddr	-	Covered	T6,T10,T8
1	DataBaseAddr DataEndAddr	-	Covered	T1,T6,T30
1	ProgBufBaseAddr ProgBufEndAddr	-	Covered	T4,T6,T10
1	AbstractCmdBaseAddr AbstractCmdEndAddr	-	Covered	T5,T6,T45
1	FlagsBaseAddr FlagsEndAddr	-	Covered	T6,T22,T24
1	RomBaseAddr RomEndAddr	-	Covered	T6,T10,T38
1	default	-	Covered	T6,T10,T8
1	-	1	Not Covered
1	-	0	Covered	T1,T2,T4
0	-	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	411	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	440	case (cmd_i.cmdtype)
-2-:	445	if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && ac_ar.write))
-3-:	449	if ((ac_ar.regno[15:14] != '0))
-4-:	454	if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10)))
-5-:	465	if (ac_ar.regno[12])
-6-:	467	if (ac_ar.regno[5])
-7-:	486	if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && (!ac_ar.write)))
-8-:	492	if ((ac_ar.regno[15:14] != '0))
-9-:	497	if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10)))
-10-:	508	if (ac_ar.regno[12])
-11-:	510	if (ac_ar.regno[5])
-12-:	529	if (((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1)))
-13-:	541	if ((ac_ar.postexec && (!unsupported_command)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
AccessRegister	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	1	-	-	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	1	1	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	1	0	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	0	-	-	-	-	-	-	-	-	Covered	T5,T45,T14
AccessRegister	0	-	-	-	-	1	1	-	-	-	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	1	-	-	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	1	1	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	1	0	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	0	-	-	-	Covered	T22,T24,T41
AccessRegister	0	-	-	-	-	0	-	-	-	-	1	-	Not Covered
AccessRegister	0	-	-	-	-	0	-	-	-	-	0	-	Covered	T1,T2,T4
AccessRegister	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T37,T14,T7
AccessRegister	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T26,T22

	LineNo.	Expression
-1-:	587	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	601	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Line Coverage for Instance : tb.dut.u_dm_top.i_dm_mem

	Line No.	Total	Covered	Percent
TOTAL		187	167	89.30
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
ALWAYS	148	37	37	100.00
CONT_ASSIGN	226	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
ALWAYS	239	46	46	100.00
ROUTINE	375	1	1	100.00
ALWAYS	388	14	14	100.00
ALWAYS	411	3	3	100.00
CONT_ASSIGN	418	1	1	100.00
ALWAYS	422	54	34	62.96
CONT_ASSIGN	557	1	1	100.00
ALWAYS	587	9	9	100.00
ALWAYS	601	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
120	1	1
121	1	1
122	1	1
124	1	1
125	1	1
126	1	1
127	1	1
135	1	1
136	1	1
137	1	1
138	1	1
141	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
155	1	1
157	1	1
158	1	1
160	1	1
161	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
170	1	1
			MISSING_ELSE
176	1	1
177	1	1
179	1	1
180	1	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
188	1	1
			MISSING_ELSE
193	1	1
194	1	1
196	1	1
197	1	1
			MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
206	1	1
207	1	1
208	1	1
			MISSING_ELSE
211	1	1
212	1	1
213	1	1
			MISSING_ELSE
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
231	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
247	1	1
248	1	1
249	1	1
250	1	1
253	1	1
254	1	1
			MISSING_ELSE
257	1	1
259	1	1
260	1	1
262	1	1
263	1	1
266	1	1
270	1	1
272	1	1
275	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
285		excluded
			Exclude Annotation: VC_COV_UNR
286		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
289	1	1
			==> MISSING_ELSE
			MISSING_ELSE
301	1	1
305	1	1
306	1	1
			MISSING_ELSE
310	1	1
313	1	1
315	1	1
318	1	1
			MISSING_ELSE
324	1	1
334	1	1
341	1	1
347	1	1
349	1	1
			MISSING_ELSE
351	1	1
356	1	1
			MISSING_ELSE
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
369	1	1
375	1	1
388	1	1
389	1	1
390	1	1
391	1	1
392	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
398	1	1
399	1	1
400	1	1
404	1	1
405		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
			MISSING_ELSE
411	1	1
412	1	1
414	1	1
418	1	1
422	1	1
425	1	1
427	1	1
429	1	1
430	1	1
431	1	1
432	1	1
433	1	1
434	1	1
435	1	1
436	1	1
437	1	1
440	1	1
445	1	1
447	1	1
449	1	1
450	0	1
451	0	1
454	1	1
457	0	1
459	0	1
461	0	1
463	0	1
465	1	1
467	0	1
468	0	1
471	0	1
478	1	1
480	1	1
482	1	1
484	1	1
486	1	1
488	1	1
492	1	1
493	0	1
494	0	1
497	1	1
500	0	1
502	0	1
504	0	1
506	0	1
508	1	1
510	0	1
511	0	1
514	0	1
521	1	1
523	1	1
525	1	1
527	1	1
529	1	1
533	0	1
534	0	1
			MISSING_ELSE
541	1	1
543	1	1
			MISSING_ELSE
557	1	1
587	1	1
588	1	1
589	1	1
590	1	1
591	1	1
593	1	1
594	1	1
595	1	1
596	1	1
601	1	1
602	1	1
603	1	1
605	1	1
606	1	1

---

Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_mem

	Total	Covered	Percent
Conditions	58	40	68.97
Logical	58	40	68.97
Non-Logical	0	0
Event	0	0

 LINE       158
 EXPRESSION (cmd_valid_i && halted_q_aligned[hartsel] && ((!unsupported_command)))
             -----1-----    ------------2------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T34,T35
1	1	0	Covered	T6,T26,T22
1	1	1	Covered	T5,T6,T22

 LINE       168
 EXPRESSION (resumereq_aligned[hartsel] && ((!resuming_q_aligned[hartsel])) && ((!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel])
             -------------1------------    ----------------2---------------    --------------3--------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T6,T22,T24
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Covered	T6,T36,T37
1	1	1	0	Covered	T6,T22,T24
1	1	1	1	Covered	T6,T22,T24

 LINE       206
 EXPRESSION (unsupported_command && cmd_valid_i)
             ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T22
1	0	Covered	T6,T26,T22
1	1	Covered	T6,T26,T22

 LINE       226
 EXPRESSION (fwd_rom_q ? rom_rdata : rdata_q)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T38,T39

 LINE       231
 EXPRESSION (word_enable32_q ? word_mux[32+:32] : word_mux[0+:32])
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T5,T6

 LINE       280
 EXPRESSION ((addr_i[(DbgAddressBits - 1):2] - DataBaseAddr[(DbgAddressBits - 1):2]) == dc)
            ---------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T1,T6,T30
1	Covered	T1,T6,T30

 LINE       313
 EXPRESSION ((cmd_i.cmdtype == AccessRegister) && ((!ac_ar.transfer)) && ac_ar.postexec)
             ----------------1----------------    ---------2---------    -------3------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		Cannot have running command other than AccessRegister
1	0	1	Covered	T14,T40,T41
1	1	0	Covered	T6,T42,T43
1	1	1	Covered	T37,T7,T44

 LINE       313
 SUB-EXPRESSION (cmd_i.cmdtype == AccessRegister)
                ----------------1----------------

-1-	Status	Tests
0	Excluded
1	Covered	T6,T22,T24

 LINE       347
 EXPRESSION (({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0}))
            ----------------------------------------------------------------------1---------------------------------------------------------------------

-1-	Status	Tests
0	Covered	T6,T10,T8
1	Covered	T6,T22,T24

 LINE       445
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ac_ar.write)
             --------------1--------------    -------2------    -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T42,T7
1	1	0	Covered	T22,T24,T41
1	1	1	Covered	T5,T45,T14

 LINE       449
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T5,T45,T14
1	Not Covered

 LINE       454
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       454
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------

-1-	Status	Tests
0	Covered	T5,T45,T14
1	Not Covered

 LINE       486
 EXPRESSION ((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer && ((!ac_ar.write)))
             --------------1--------------    -------2------    --------3-------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T22,T24,T41

 LINE       492
 EXPRESSION (ac_ar.regno[15:14] != '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T22,T24,T41
1	Not Covered

 LINE       497
 EXPRESSION (HasSndScratch && ac_ar.regno[12] && ((!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10))
             ------1------    -------2-------    ---------3---------    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       497
 SUB-EXPRESSION (ac_ar.regno[4:0] == 5'd10)
                -------------1-------------

-1-	Status	Tests
0	Covered	T22,T24,T41
1	Not Covered

 LINE       529
 EXPRESSION ((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1))
             ---------------1--------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (ac_ar.aarpostincrement == 1'b1)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Not Covered

 LINE       541
 EXPRESSION (ac_ar.postexec && ((!unsupported_command)))
             -------1------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T37,T14,T7

 LINE       605
 EXPRESSION (SelectableHarts & halted_d)
             -------1-------   ----2---

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T1,T2,T4

 LINE       606
 EXPRESSION (SelectableHarts & resuming_d)
             -------1-------   -----2----

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T6,T22,T24

---

FSM Coverage for Instance : tb.dut.u_dm_top.i_dm_mem

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CmdExecuting	180	Covered	T6,T22,T24
Go	160	Covered	T5,T6,T22
Idle	188	Covered	T1,T2,T4
Resume	170	Covered	T6,T22,T24

transitions	Line No.	Covered	Tests
CmdExecuting->Idle	197	Covered	T6,T22,T24
Go->CmdExecuting	180	Covered	T6,T22,T24
Go->Idle	218	Not Covered
Idle->Go	160	Covered	T5,T6,T22
Idle->Resume	170	Covered	T6,T22,T24
Resume->Idle	188	Covered	T6,T22,T24

---

Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_mem

	Line No.	Total	Covered	Percent
Branches		78	69	88.46
TERNARY	226	2	2	100.00
TERNARY	231	2	2	100.00
CASE	155	11	11	100.00
IF	206	2	2	100.00
IF	211	2	2	100.00
IF	216	2	2	100.00
IF	253	2	2	100.00
IF	257	19	19	100.00
IF	363	2	2	100.00
IF	389	13	13	100.00
IF	411	2	2	100.00
CASE	440	15	6	40.00
IF	587	2	2	100.00
IF	601	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_mem.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	226	(fwd_rom_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	231	(word_enable32_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	155	case (state_q)
-2-:	158	if (((cmd_valid_i && halted_q_aligned[hartsel]) && (!unsupported_command)))
-3-:	161	if (cmd_valid_i)
-4-:	168	if ((((resumereq_aligned[hartsel] && (!resuming_q_aligned[hartsel])) && (!haltreq_aligned[hartsel])) && halted_q_aligned[hartsel]))
-5-:	179	if (going)
-6-:	187	if (resuming_q_aligned[hartsel])
-7-:	196	if (halted_aligned[hartsel])

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests	Exclude Annotation
Idle	1	-	-	-	-	-	Covered	T5,T6,T22
Idle	0	1	-	-	-	-	Covered	T6,T26,T22
Idle	0	0	-	-	-	-	Covered	T1,T2,T4
Idle	-	-	1	-	-	-	Covered	T6,T22,T24
Idle	-	-	0	-	-	-	Covered	T1,T2,T4
Go	-	-	-	1	-	-	Covered	T6,T22,T24
Go	-	-	-	0	-	-	Covered	T5,T6,T22
Resume	-	-	-	-	1	-	Covered	T6,T22,T24
Resume	-	-	-	-	0	-	Covered	T6,T22,T24
CmdExecuting	-	-	-	-	-	1	Covered	T6,T22,T24
CmdExecuting	-	-	-	-	-	0	Covered	T6,T22,T24
default	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	206	if ((unsupported_command && cmd_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T6,T26,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	211	if (exception)

Branches:

-1-	Status	Tests
1	Covered	T16,T17
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	216	if (ndmreset_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	253	if (clear_resumeack_i)

Branches:

-1-	Status	Tests
1	Covered	T6,T22,T24
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	257	if (req_i)
-2-:	259	if (we_i)
-3-:	260	case (addr_i[(DbgAddressBits - 1):0])
-4-:	301	case (addr_i[(DbgAddressBits - 1):0])
-5-:	305	if (resumereq_wdata_aligned[wdata_hartsel])
-6-:	310	if (cmdbusy_o)
-7-:	313	if ((((cmd_i.cmdtype == AccessRegister) && (!ac_ar.transfer)) && ac_ar.postexec))
-8-:	347	if ((({addr_i[(DbgAddressBits - 1):3], 3'b0} - FlagsBaseAddr[(DbgAddressBits - 1):0]) == (12'(hartsel) & {{(DbgAddressBits - 3) {1'b1}}, 3'b0})))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	1	HaltedAddr	-	-	-	-	-	Covered	T1,T2,T4
1	1	GoingAddr	-	-	-	-	-	Covered	T6,T22,T24
1	1	ResumingAddr	-	-	-	-	-	Covered	T6,T22,T24
1	1	ExceptionAddr	-	-	-	-	-	Covered	T16,T17
1	1	DataBaseAddr DataEndAddr	-	-	-	-	-	Covered	T1,T6,T30
1	1	default	-	-	-	-	-	Covered	T6,T10,T8
1	0	-	WhereToAddr	1	-	-	-	Covered	T6,T10,T21
1	0	-	WhereToAddr	0	-	-	-	Covered	T6,T22,T24
1	0	-	WhereToAddr	-	1	1	-	Covered	T37,T7,T44
1	0	-	WhereToAddr	-	1	0	-	Covered	T6,T22,T24
1	0	-	WhereToAddr	-	0	-	-	Covered	T6,T10,T8
1	0	-	DataBaseAddr DataEndAddr	-	-	-	-	Covered	T1,T6,T30
1	0	-	ProgBufBaseAddr ProgBufEndAddr	-	-	-	-	Covered	T4,T6,T10
1	0	-	AbstractCmdBaseAddr AbstractCmdEndAddr	-	-	-	-	Covered	T5,T45
1	0	-	FlagsBaseAddr FlagsEndAddr	-	-	-	1	Covered	T6,T22,T24
1	0	-	FlagsBaseAddr FlagsEndAddr	-	-	-	0	Covered	T6,T10,T8
1	0	-	RomBaseAddr RomEndAddr	-	-	-	-	Covered	T38,T39
1	0	-	default	-	-	-	-	Covered	T6,T10,T8
0	-	-	-	-	-	-	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	363	if (ndmreset_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T22
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	389	if (req_i)
-2-:	390	case (addr_i[(DbgAddressBits - 1):0])
-3-:	404	if ((addr_i[($clog2(BeWidth) - 1):0] != '0))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	WhereToAddr	-	Covered	T6,T22,T24
1	HaltedAddr	-	Covered	T1,T2,T4
1	GoingAddr	-	Covered	T6,T22,T24
1	ResumingAddr	-	Covered	T6,T22,T24
1	ExceptionAddr	-	Covered	T6,T10,T8
1	DataBaseAddr DataEndAddr	-	Covered	T1,T6,T30
1	ProgBufBaseAddr ProgBufEndAddr	-	Covered	T4,T6,T10
1	AbstractCmdBaseAddr AbstractCmdEndAddr	-	Covered	T5,T6,T45
1	FlagsBaseAddr FlagsEndAddr	-	Covered	T6,T22,T24
1	RomBaseAddr RomEndAddr	-	Covered	T6,T10,T38
1	default	-	Covered	T6,T10,T8
1	-	1	Excluded		VC_COV_UNR
1	-	0	Covered	T1,T2,T4
0	-	-	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	411	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	440	case (cmd_i.cmdtype)
-2-:	445	if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && ac_ar.write))
-3-:	449	if ((ac_ar.regno[15:14] != '0))
-4-:	454	if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10)))
-5-:	465	if (ac_ar.regno[12])
-6-:	467	if (ac_ar.regno[5])
-7-:	486	if ((((32'(ac_ar.aarsize) < MaxAar) && ac_ar.transfer) && (!ac_ar.write)))
-8-:	492	if ((ac_ar.regno[15:14] != '0))
-9-:	497	if ((((HasSndScratch && ac_ar.regno[12]) && (!ac_ar.regno[5])) && (ac_ar.regno[4:0] == 5'd10)))
-10-:	508	if (ac_ar.regno[12])
-11-:	510	if (ac_ar.regno[5])
-12-:	529	if (((32'(ac_ar.aarsize) >= MaxAar) || (ac_ar.aarpostincrement == 1'b1)))
-13-:	541	if ((ac_ar.postexec && (!unsupported_command)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
AccessRegister	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	1	-	-	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	1	1	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	1	0	-	-	-	-	-	-	-	Not Covered
AccessRegister	1	0	0	0	-	-	-	-	-	-	-	-	Covered	T5,T45,T14
AccessRegister	0	-	-	-	-	1	1	-	-	-	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	1	-	-	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	1	1	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	1	0	-	-	Not Covered
AccessRegister	0	-	-	-	-	1	0	0	0	-	-	-	Covered	T22,T24,T41
AccessRegister	0	-	-	-	-	0	-	-	-	-	1	-	Not Covered
AccessRegister	0	-	-	-	-	0	-	-	-	-	0	-	Covered	T1,T2,T4
AccessRegister	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T37,T14,T7
AccessRegister	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T26,T22

	LineNo.	Expression
-1-:	587	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	601	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4