Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9633374 9631954 0 0
selKnown1 100147644 100146224 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9633374 9631954 0 0
T1 22133 22129 0 0
T2 1230 1226 0 0
T3 356 352 0 0
T4 2486 2482 0 0
T5 1096 1092 0 0
T6 186337 186333 0 0
T11 22168 22164 0 0
T12 0 4 0 0
T13 0 12 0 0
T22 0 8 0 0
T27 0 10 0 0
T31 278 274 0 0
T32 250 246 0 0
T33 312 308 0 0
T36 0 10 0 0
T46 0 40 0 0
T49 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 100147644 100146224 0 0
T1 66854 66850 0 0
T2 5862 5858 0 0
T3 7030 7026 0 0
T4 10330 10326 0 0
T5 14581 14577 0 0
T6 395314 395311 0 0
T11 133902 133898 0 0
T12 0 4 0 0
T13 0 12 0 0
T22 0 6 0 0
T27 0 10 0 0
T31 3475 3471 0 0
T32 2567 2563 0 0
T33 5861 5857 0 0
T36 0 8 0 0
T46 0 40 0 0
T49 0 2 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 3192330 3192085 0 0
selKnown1 93706788 93706543 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 3192330 3192085 0 0
T1 11062 11061 0 0
T2 614 613 0 0
T3 177 176 0 0
T4 1242 1241 0 0
T5 547 546 0 0
T6 93151 93150 0 0
T11 11079 11078 0 0
T31 138 137 0 0
T32 124 123 0 0
T33 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 93706788 93706543 0 0
T1 55786 55785 0 0
T2 5246 5245 0 0
T3 6851 6850 0 0
T4 9086 9085 0 0
T5 14032 14031 0 0
T6 302141 302141 0 0
T11 122813 122812 0 0
T31 3335 3334 0 0
T32 2441 2440 0 0
T33 5704 5703 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 820 575 0 0
selKnown1 763 518 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 820 575 0 0
T1 4 3 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 16 15 0 0
T11 5 4 0 0
T12 0 2 0 0
T13 0 6 0 0
T22 0 4 0 0
T27 0 5 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T36 0 5 0 0
T46 0 20 0 0
T49 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 763 518 0 0
T1 3 2 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 11 10 0 0
T11 5 4 0 0
T12 0 2 0 0
T13 0 6 0 0
T22 0 3 0 0
T27 0 5 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T36 0 4 0 0
T46 0 20 0 0
T49 0 1 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6438227 6437762 0 0
selKnown1 6438227 6437762 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6438227 6437762 0 0
T1 11062 11061 0 0
T2 614 613 0 0
T3 177 176 0 0
T4 1242 1241 0 0
T5 547 546 0 0
T6 93151 93150 0 0
T11 11079 11078 0 0
T31 138 137 0 0
T32 124 123 0 0
T33 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6438227 6437762 0 0
T1 11062 11061 0 0
T2 614 613 0 0
T3 177 176 0 0
T4 1242 1241 0 0
T5 547 546 0 0
T6 93151 93150 0 0
T11 11079 11078 0 0
T31 138 137 0 0
T32 124 123 0 0
T33 155 154 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1997 1532 0 0
selKnown1 1866 1401 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1997 1532 0 0
T1 5 4 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 19 18 0 0
T11 5 4 0 0
T12 0 2 0 0
T13 0 6 0 0
T22 0 4 0 0
T27 0 5 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T36 0 5 0 0
T46 0 20 0 0
T49 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1866 1401 0 0
T1 3 2 0 0
T2 1 0 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 1 0 0 0
T6 11 10 0 0
T11 5 4 0 0
T12 0 2 0 0
T13 0 6 0 0
T22 0 3 0 0
T27 0 5 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 1 0 0 0
T36 0 4 0 0
T46 0 20 0 0
T49 0 1 0 0

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