SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.00 | 100.00 | 100.00 | 100.00 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1470 | 1470 | 0 | 0 |
OutputsKnown_A | 562240728 | 561921906 | 0 | 0 |
gen_flops.OutputDelay_A | 281120364 | 280954086 | 0 | 2205 |
gen_no_flops.OutputDelay_A | 281120364 | 280960953 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1470 | 1470 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T6 | 6 | 6 | 0 | 0 |
T11 | 6 | 6 | 0 | 0 |
T31 | 6 | 6 | 0 | 0 |
T32 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 562240728 | 561921906 | 0 | 0 |
T1 | 334716 | 333660 | 0 | 0 |
T2 | 31476 | 30978 | 0 | 0 |
T3 | 41106 | 40638 | 0 | 0 |
T4 | 54516 | 54096 | 0 | 0 |
T5 | 84192 | 83814 | 0 | 0 |
T6 | 1812846 | 1812066 | 0 | 0 |
T11 | 736878 | 734892 | 0 | 0 |
T31 | 20010 | 19710 | 0 | 0 |
T32 | 14646 | 14310 | 0 | 0 |
T33 | 34224 | 33822 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281120364 | 280954086 | 0 | 2205 |
T1 | 167358 | 166803 | 0 | 9 |
T2 | 15738 | 15480 | 0 | 9 |
T3 | 20553 | 20310 | 0 | 9 |
T4 | 27258 | 27039 | 0 | 9 |
T5 | 42096 | 41898 | 0 | 9 |
T6 | 906423 | 906021 | 0 | 9 |
T11 | 368439 | 367401 | 0 | 9 |
T31 | 10005 | 9846 | 0 | 9 |
T32 | 7323 | 7146 | 0 | 9 |
T33 | 17112 | 16902 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281120364 | 280960953 | 0 | 0 |
T1 | 167358 | 166830 | 0 | 0 |
T2 | 15738 | 15489 | 0 | 0 |
T3 | 20553 | 20319 | 0 | 0 |
T4 | 27258 | 27048 | 0 | 0 |
T5 | 42096 | 41907 | 0 | 0 |
T6 | 906423 | 906033 | 0 | 0 |
T11 | 368439 | 367446 | 0 | 0 |
T31 | 10005 | 9855 | 0 | 0 |
T32 | 7323 | 7155 | 0 | 0 |
T33 | 17112 | 16911 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_flops.OutputDelay_A | 93706788 | 93651362 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93651362 | 0 | 735 |
T1 | 55786 | 55601 | 0 | 3 |
T2 | 5246 | 5160 | 0 | 3 |
T3 | 6851 | 6770 | 0 | 3 |
T4 | 9086 | 9013 | 0 | 3 |
T5 | 14032 | 13966 | 0 | 3 |
T6 | 302141 | 302007 | 0 | 3 |
T11 | 122813 | 122467 | 0 | 3 |
T31 | 3335 | 3282 | 0 | 3 |
T32 | 2441 | 2382 | 0 | 3 |
T33 | 5704 | 5634 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_flops.OutputDelay_A | 93706788 | 93651362 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93651362 | 0 | 735 |
T1 | 55786 | 55601 | 0 | 3 |
T2 | 5246 | 5160 | 0 | 3 |
T3 | 6851 | 6770 | 0 | 3 |
T4 | 9086 | 9013 | 0 | 3 |
T5 | 14032 | 13966 | 0 | 3 |
T6 | 302141 | 302007 | 0 | 3 |
T11 | 122813 | 122467 | 0 | 3 |
T31 | 3335 | 3282 | 0 | 3 |
T32 | 2441 | 2382 | 0 | 3 |
T33 | 5704 | 5634 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_no_flops.OutputDelay_A | 93706788 | 93653651 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_flops.OutputDelay_A | 93706788 | 93651362 | 0 | 735 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93651362 | 0 | 735 |
T1 | 55786 | 55601 | 0 | 3 |
T2 | 5246 | 5160 | 0 | 3 |
T3 | 6851 | 6770 | 0 | 3 |
T4 | 9086 | 9013 | 0 | 3 |
T5 | 14032 | 13966 | 0 | 3 |
T6 | 302141 | 302007 | 0 | 3 |
T11 | 122813 | 122467 | 0 | 3 |
T31 | 3335 | 3282 | 0 | 3 |
T32 | 2441 | 2382 | 0 | 3 |
T33 | 5704 | 5634 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_no_flops.OutputDelay_A | 93706788 | 93653651 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 245 | 245 | 0 | 0 |
OutputsKnown_A | 93706788 | 93653651 | 0 | 0 |
gen_no_flops.OutputDelay_A | 93706788 | 93653651 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 245 | 245 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 93706788 | 93653651 | 0 | 0 |
T1 | 55786 | 55610 | 0 | 0 |
T2 | 5246 | 5163 | 0 | 0 |
T3 | 6851 | 6773 | 0 | 0 |
T4 | 9086 | 9016 | 0 | 0 |
T5 | 14032 | 13969 | 0 | 0 |
T6 | 302141 | 302011 | 0 | 0 |
T11 | 122813 | 122482 | 0 | 0 |
T31 | 3335 | 3285 | 0 | 0 |
T32 | 2441 | 2385 | 0 | 0 |
T33 | 5704 | 5637 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |