Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00
tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	100.00	87.50			100.00		i_cdc_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_rz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	100.00	66.67			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.78	100.00	93.33			100.00		i_cdc_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_rz_hs_protocol.req_sync	100.00	100.00				100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Not Covered

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	5	5	100.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T4
LoSt	0	-	Covered	T1,T2,T4
HiSt	-	1	Covered	T1,T2,T4
HiSt	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
LoSt	1	1	-	Covered	T1,T2,T4
LoSt	1	0	-	Covered	T1,T2,T4
LoSt	0	-	-	Covered	T1,T2,T4
HiSt	-	-	1	Covered	T1,T2,T4
HiSt	-	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	159916010	106356	0	0
SyncReqAckHoldReq	159916010	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	159916010	106356	0	0
T1	66848	176	0	0
T2	5860	10	0	0
T3	7028	2	0	0
T4	10328	22	0	0
T5	14579	10	0	0
T6	395292	1548	0	0
T11	133892	196	0	0
T31	3473	2	0	0
T32	2565	2	0	0
T33	5859	2	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	159916010	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	5	5	100.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T4
LoSt	0	-	Covered	T1,T2,T4
HiSt	-	1	Covered	T1,T2,T4
HiSt	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
LoSt	1	1	-	Covered	T1,T2,T4
LoSt	1	0	-	Covered	T1,T2,T4
LoSt	0	-	-	Covered	T1,T2,T4
HiSt	-	-	1	Covered	T1,T2,T4
HiSt	-	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	153477783	53178	0	0
SyncReqAckHoldReq	6438227	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	153477783	53178	0	0
T1	55786	88	0	0
T2	5246	5	0	0
T3	6851	1	0	0
T4	9086	11	0	0
T5	14032	5	0	0
T6	302141	774	0	0
T11	122813	98	0	0
T31	3335	1	0	0
T32	2441	1	0	0
T33	5704	1	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	6438227	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		27	27	100.00
CONT_ASSIGN	55	0	0
ALWAYS	75	10	10	100.00
ALWAYS	117	3	3	100.00
ALWAYS	126	11	11	100.00
ALWAYS	169	3	3	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
77	1	1
79	1	1
83	1	1
84	1	1
			MISSING_ELSE
88	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
126	1	1
127	1	1
128	1	1
130	1	1
132	1	1
134	1	1
137	1	1
138	1	1
			==> MISSING_ELSE
			MISSING_ELSE
143	1	1
145	1	1
146	1	1
			MISSING_ELSE
169	1	1
170	1	1
172	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	79	4	4	100.00
IF	117	2	2	100.00
CASE	130	4	4	100.00
IF	169	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	79	case (gen_rz_hs_protocol.src_fsm_q)
-2-:	83	if (((!gen_rz_hs_protocol.src_ack) && src_req_i))
-3-:	93	if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:

-1-	-2-	-3-	Status	Tests
LoSt	1	-	Covered	T1,T2,T4
LoSt	0	-	Covered	T1,T2,T4
HiSt	-	1	Covered	T1,T2,T4
HiSt	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	117	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	130	case (gen_rz_hs_protocol.dst_fsm_q)
-2-:	132	if (gen_rz_hs_protocol.dst_req)
-3-:	137	if (dst_ack_i)
-4-:	145	if ((!gen_rz_hs_protocol.dst_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
LoSt	1	1	-	Covered	T1,T2,T4
LoSt	1	0	-	Excluded		VC_COV_UNR
LoSt	0	-	-	Covered	T1,T2,T4
HiSt	-	-	1	Covered	T1,T2,T4
HiSt	-	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	169	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	6438227	53178	0	0
SyncReqAckHoldReq	153477783	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	6438227	53178	0	0
T1	11062	88	0	0
T2	614	5	0	0
T3	177	1	0	0
T4	1242	11	0	0
T5	547	5	0	0
T6	93151	774	0	0
T11	11079	98	0	0
T31	138	1	0	0
T32	124	1	0	0
T33	155	1	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	153477783	0	0	0