Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	60.77			60.77
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.77			60.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.77			60.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T4,*T3	Yes	T1,T2,T4	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
data_o[56:0]	Yes	Yes	T1,T4,T3	Yes	T1,T2,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T31,T6	Yes	T2,T3,T31	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T31	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	158	60.77
Total Bits 0->1	130	79	60.77
Total Bits 1->0	130	79	60.77

Ports	4	3	75.00
Port Bits	260	158	60.77
Port Bits 0->1	130	79	60.77
Port Bits 1->0	130	79	60.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	*T3,*T11,*T12	Yes	T11,T12,T49	INPUT
data_i[56:6]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T11,T12,T46	Yes	T3,T11,T54	INPUT
data_o[56:0]	Yes	Yes	T3,T11,T12	Yes	T11,T12,T49	OUTPUT
syndrome_o[6:0]	Yes	Yes	T11,T12,T46	Yes	T3,T11,T54	OUTPUT
err_o[1:0]	Yes	Yes	T12,T49,T46	Yes	T12,T49,T46	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T31,T6,*T33	Yes	T31,T6,T33	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T31	INPUT
data_o[56:0]	Yes	Yes	T31,T6,T33	Yes	T31,T6,T33	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T31,T55	Yes	T2,T31,T33	OUTPUT
err_o[1:0]	Yes	Yes	T2,T31,T33	Yes	T2,T31,T33	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T2,T4	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	INPUT
data_o[56:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T6,T26,T46	Yes	T31,T6,T26	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T4	Yes	T1,T6,T26	OUTPUT

*Tests covering at least one bit in the range