Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	600969	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

921210

1

T1

4

T2

7

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	607027	1			T1	3		T2	4		T4	3
values[0x0]	302462	1			T1	9		T2	5		T3	1
values[0x1]	612690	1			T1	11		T2	17		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1215991

1

T1

7

T2

9

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5885	1			T9	106		T20	445		T134	1
valid_sources[0x01]	5582	1			T9	89		T20	453		T33	875
valid_sources[0x02]	5380	1			T9	88		T60	2		T20	435
valid_sources[0x03]	5754	1			T6	3		T9	101		T20	421
valid_sources[0x04]	5836	1			T4	1		T9	108		T20	452
valid_sources[0x05]	5759	1			T9	101		T20	441		T33	1049
valid_sources[0x06]	7940	1			T1	1		T9	92		T20	452
valid_sources[0x07]	5469	1			T5	2		T9	100		T20	397
valid_sources[0x08]	5401	1			T9	100		T20	458		T33	850
valid_sources[0x09]	5261	1			T9	110		T20	460		T33	900
valid_sources[0x0a]	5629	1			T9	110		T20	481		T119	1
valid_sources[0x0b]	5415	1			T9	105		T20	437		T33	923
valid_sources[0x0c]	6206	1			T9	110		T20	449		T33	946
valid_sources[0x0d]	5980	1			T9	89		T20	490		T33	906
valid_sources[0x0e]	5450	1			T9	102		T20	408		T33	985
valid_sources[0x0f]	7310	1			T9	118		T72	1		T20	464
valid_sources[0x10]	5777	1			T1	1		T9	111		T7	2
valid_sources[0x11]	5529	1			T9	84		T20	425		T33	887
valid_sources[0x12]	7269	1			T9	86		T20	432		T33	919
valid_sources[0x13]	5638	1			T9	103		T20	446		T37	1
valid_sources[0x14]	5633	1			T9	94		T7	2		T20	418
valid_sources[0x15]	5538	1			T6	1		T9	96		T72	1
valid_sources[0x16]	5521	1			T9	103		T20	409		T33	958
valid_sources[0x17]	5936	1			T9	103		T20	463		T33	885
valid_sources[0x18]	5762	1			T28	9		T9	103		T20	438
valid_sources[0x19]	5758	1			T9	93		T20	429		T33	971
valid_sources[0x1a]	5502	1			T9	106		T20	432		T33	883
valid_sources[0x1b]	6595	1			T9	97		T20	441		T21	3
valid_sources[0x1c]	5466	1			T5	1		T9	100		T20	444
valid_sources[0x1d]	5923	1			T5	1		T9	102		T20	473
valid_sources[0x1e]	5673	1			T9	107		T20	466		T31	80
valid_sources[0x1f]	5371	1			T9	92		T20	416		T33	906
valid_sources[0x20]	6734	1			T9	104		T20	467		T33	914
valid_sources[0x21]	6192	1			T9	98		T72	1		T20	381
valid_sources[0x22]	5789	1			T9	104		T20	419		T33	882
valid_sources[0x23]	5564	1			T9	101		T20	428		T161	1
valid_sources[0x24]	5570	1			T9	113		T20	440		T33	945
valid_sources[0x25]	5782	1			T9	103		T15	1		T20	412
valid_sources[0x26]	5637	1			T9	98		T20	473		T162	4
valid_sources[0x27]	5818	1			T9	106		T20	438		T33	976
valid_sources[0x28]	5628	1			T9	97		T20	452		T33	847
valid_sources[0x29]	10801	1			T9	112		T20	421		T146	2
valid_sources[0x2a]	5689	1			T9	128		T20	504		T33	848
valid_sources[0x2b]	5714	1			T9	96		T34	1		T20	426
valid_sources[0x2c]	5543	1			T9	92		T20	461		T33	890
valid_sources[0x2d]	6151	1			T2	3		T9	82		T20	440
valid_sources[0x2e]	5485	1			T9	99		T20	440		T33	847
valid_sources[0x2f]	5730	1			T9	89		T20	435		T33	998
valid_sources[0x30]	5628	1			T9	102		T20	472		T33	923
valid_sources[0x31]	5703	1			T9	105		T20	453		T134	1
valid_sources[0x32]	5666	1			T9	92		T7	4		T20	399
valid_sources[0x33]	5503	1			T9	92		T20	444		T33	936
valid_sources[0x34]	6069	1			T9	109		T20	447		T33	924
valid_sources[0x35]	5702	1			T9	111		T20	402		T130	1
valid_sources[0x36]	5875	1			T5	1		T9	101		T20	452
valid_sources[0x37]	8292	1			T9	98		T20	410		T37	1
valid_sources[0x38]	6040	1			T9	102		T20	450		T33	944
valid_sources[0x39]	5868	1			T9	80		T20	456		T134	1
valid_sources[0x3a]	5666	1			T9	99		T20	447		T33	959
valid_sources[0x3b]	6070	1			T9	109		T20	427		T33	1016
valid_sources[0x3c]	5791	1			T5	1		T9	104		T20	458
valid_sources[0x3d]	5485	1			T9	98		T20	431		T33	924
valid_sources[0x3e]	6281	1			T9	106		T15	5		T20	429
valid_sources[0x3f]	5644	1			T1	1		T9	93		T20	421
valid_sources[0x40]	5629	1			T9	88		T20	461		T33	943
valid_sources[0x41]	5601	1			T9	85		T20	440		T23	1
valid_sources[0x42]	5989	1			T9	84		T20	445		T33	1004
valid_sources[0x43]	5570	1			T5	1		T9	105		T20	451
valid_sources[0x44]	6005	1			T9	89		T20	453		T33	956
valid_sources[0x45]	5353	1			T9	89		T20	415		T163	2
valid_sources[0x46]	5847	1			T2	3		T9	86		T20	422
valid_sources[0x47]	5484	1			T9	100		T20	435		T33	919
valid_sources[0x48]	5691	1			T1	2		T9	103		T46	4
valid_sources[0x49]	5773	1			T5	1		T9	99		T20	430
valid_sources[0x4a]	5490	1			T9	88		T20	447		T134	1
valid_sources[0x4b]	5428	1			T5	1		T9	92		T20	444
valid_sources[0x4c]	5711	1			T4	1		T9	83		T20	397
valid_sources[0x4d]	5603	1			T9	86		T20	466		T37	2
valid_sources[0x4e]	5449	1			T9	86		T20	423		T161	1
valid_sources[0x4f]	5437	1			T9	100		T20	416		T33	930
valid_sources[0x50]	5975	1			T9	119		T20	422		T33	882
valid_sources[0x51]	5723	1			T9	100		T72	1		T20	431
valid_sources[0x52]	5425	1			T9	103		T20	440		T33	936
valid_sources[0x53]	5863	1			T9	95		T20	448		T33	904
valid_sources[0x54]	5611	1			T9	103		T15	2		T20	446
valid_sources[0x55]	5634	1			T4	1		T9	102		T20	457
valid_sources[0x56]	5770	1			T9	99		T20	439		T161	1
valid_sources[0x57]	6038	1			T9	97		T20	443		T33	988
valid_sources[0x58]	5576	1			T5	1		T9	108		T20	449
valid_sources[0x59]	6132	1			T9	114		T20	472		T37	2
valid_sources[0x5a]	6343	1			T9	114		T20	452		T33	971
valid_sources[0x5b]	5765	1			T5	1		T9	101		T20	463
valid_sources[0x5c]	5464	1			T9	100		T20	470		T33	914
valid_sources[0x5d]	5180	1			T9	107		T132	3		T20	453
valid_sources[0x5e]	6804	1			T9	91		T20	472		T33	937
valid_sources[0x5f]	5983	1			T9	93		T20	438		T33	881
valid_sources[0x60]	6196	1			T9	95		T20	448		T33	875
valid_sources[0x61]	5911	1			T9	102		T20	485		T119	2
valid_sources[0x62]	5859	1			T9	96		T20	445		T33	907
valid_sources[0x63]	5379	1			T9	98		T20	440		T33	932
valid_sources[0x64]	5445	1			T9	91		T20	473		T33	922
valid_sources[0x65]	5823	1			T9	108		T20	429		T33	960
valid_sources[0x66]	5686	1			T1	2		T9	119		T15	1
valid_sources[0x67]	6059	1			T9	103		T20	420		T33	921
valid_sources[0x68]	5878	1			T9	113		T20	454		T146	2
valid_sources[0x69]	5583	1			T9	93		T20	443		T33	878
valid_sources[0x6a]	5574	1			T9	124		T34	1		T20	403
valid_sources[0x6b]	5760	1			T9	92		T20	456		T130	1
valid_sources[0x6c]	5706	1			T9	101		T15	1		T20	462
valid_sources[0x6d]	5344	1			T9	94		T20	455		T134	1
valid_sources[0x6e]	5719	1			T9	94		T15	1		T20	477
valid_sources[0x6f]	5457	1			T9	106		T20	440		T33	952
valid_sources[0x70]	6093	1			T9	101		T20	435		T163	1
valid_sources[0x71]	5695	1			T9	96		T20	435		T134	1
valid_sources[0x72]	5994	1			T9	96		T20	405		T33	952
valid_sources[0x73]	5614	1			T9	89		T46	4		T20	428
valid_sources[0x74]	5805	1			T9	109		T20	461		T33	900
valid_sources[0x75]	5718	1			T1	1		T6	2		T9	101
valid_sources[0x76]	5914	1			T9	94		T61	2		T20	451
valid_sources[0x77]	5610	1			T2	3		T9	112		T20	437
valid_sources[0x78]	5406	1			T9	89		T46	2		T20	487
valid_sources[0x79]	5653	1			T9	102		T20	426		T33	898
valid_sources[0x7a]	5713	1			T9	93		T20	407		T33	990
valid_sources[0x7b]	5989	1			T6	3		T9	96		T20	445
valid_sources[0x7c]	5757	1			T9	94		T20	470		T33	951
valid_sources[0x7d]	5969	1			T9	89		T20	472		T130	2
valid_sources[0x7e]	5503	1			T6	1		T9	107		T20	448
valid_sources[0x7f]	5776	1			T1	2		T5	1		T9	108
valid_sources[0x80]	5560	1			T9	103		T46	2		T20	427

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

386953

1

T1

3

T2

2

T4

1

values[0x0]

all_enables

biggest_size

266924

1

T1

1

T2

2

T3

1

values[0x1]

all_enables

biggest_size

267333

1

T2

3

T6

1

T9

4820

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24624	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

510163

1

T1

7

T2

8

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137862	1			T9	4442		T20	20214		T33	43677
values[0x0]	192801	1			T1	4		T2	6		T29	1
values[0x1]	204124	1			T1	3		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13494	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

521293

1

T1

7

T2

8

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2176	1			T9	64		T20	320		T33	711
valid_sources[0x01]	1841	1			T9	59		T20	287		T116	1
valid_sources[0x02]	2147	1			T9	51		T20	321		T33	699
valid_sources[0x03]	2010	1			T9	49		T20	315		T33	739
valid_sources[0x04]	2081	1			T9	62		T20	317		T33	723
valid_sources[0x05]	1945	1			T9	63		T20	313		T33	793
valid_sources[0x06]	1942	1			T9	69		T20	326		T33	653
valid_sources[0x07]	2112	1			T9	68		T20	319		T33	683
valid_sources[0x08]	1896	1			T9	63		T20	339		T33	497
valid_sources[0x09]	2097	1			T9	79		T20	285		T33	655
valid_sources[0x0a]	2298	1			T9	76		T73	1		T20	320
valid_sources[0x0b]	2252	1			T9	73		T20	319		T164	4
valid_sources[0x0c]	2229	1			T9	66		T39	1		T20	279
valid_sources[0x0d]	2025	1			T9	63		T20	329		T130	7
valid_sources[0x0e]	2027	1			T13	1		T9	71		T20	319
valid_sources[0x0f]	2256	1			T9	65		T20	263		T33	810
valid_sources[0x10]	2181	1			T9	65		T20	322		T165	4
valid_sources[0x11]	2933	1			T9	51		T20	306		T33	671
valid_sources[0x12]	2188	1			T9	70		T20	321		T166	1
valid_sources[0x13]	2045	1			T9	61		T20	288		T33	716
valid_sources[0x14]	2046	1			T9	70		T20	272		T33	614
valid_sources[0x15]	1845	1			T13	3		T9	69		T15	1
valid_sources[0x16]	1976	1			T9	56		T20	301		T33	596
valid_sources[0x17]	1935	1			T9	67		T20	334		T33	501
valid_sources[0x18]	2159	1			T9	69		T20	282		T21	1
valid_sources[0x19]	2010	1			T9	81		T20	344		T21	1
valid_sources[0x1a]	2168	1			T1	2		T9	90		T20	289
valid_sources[0x1b]	1899	1			T9	75		T57	1		T20	284
valid_sources[0x1c]	1921	1			T9	76		T20	311		T33	504
valid_sources[0x1d]	2003	1			T9	83		T20	294		T33	743
valid_sources[0x1e]	2240	1			T9	61		T20	264		T33	560
valid_sources[0x1f]	2105	1			T9	68		T20	303		T33	702
valid_sources[0x20]	2385	1			T9	56		T30	1		T20	315
valid_sources[0x21]	2360	1			T9	59		T65	1		T20	315
valid_sources[0x22]	1671	1			T9	62		T20	324		T33	459
valid_sources[0x23]	1972	1			T9	62		T20	303		T128	1
valid_sources[0x24]	2018	1			T9	74		T20	322		T167	2
valid_sources[0x25]	2502	1			T9	63		T20	287		T33	1017
valid_sources[0x26]	1983	1			T9	67		T20	328		T168	2
valid_sources[0x27]	2365	1			T9	71		T20	353		T33	633
valid_sources[0x28]	1989	1			T9	53		T20	309		T169	1
valid_sources[0x29]	1898	1			T9	64		T20	323		T33	616
valid_sources[0x2a]	2015	1			T9	66		T20	259		T170	2
valid_sources[0x2b]	2074	1			T9	62		T20	292		T33	664
valid_sources[0x2c]	2368	1			T9	64		T20	290		T171	1
valid_sources[0x2d]	2282	1			T9	70		T20	321		T33	772
valid_sources[0x2e]	1890	1			T9	64		T20	316		T33	591
valid_sources[0x2f]	2249	1			T9	52		T20	328		T33	696
valid_sources[0x30]	2187	1			T9	67		T20	330		T172	1
valid_sources[0x31]	2094	1			T9	61		T20	310		T33	645
valid_sources[0x32]	2046	1			T5	1		T9	74		T72	1
valid_sources[0x33]	1732	1			T9	75		T20	289		T161	2
valid_sources[0x34]	1910	1			T9	69		T20	300		T146	1
valid_sources[0x35]	1820	1			T9	44		T20	322		T33	602
valid_sources[0x36]	1976	1			T9	57		T20	312		T33	479
valid_sources[0x37]	2377	1			T9	63		T20	344		T167	1
valid_sources[0x38]	2319	1			T9	67		T20	285		T172	5
valid_sources[0x39]	2101	1			T9	71		T20	314		T33	684
valid_sources[0x3a]	2221	1			T9	67		T65	1		T20	305
valid_sources[0x3b]	1740	1			T9	71		T20	306		T33	553
valid_sources[0x3c]	2008	1			T9	72		T20	288		T33	601
valid_sources[0x3d]	2079	1			T9	53		T20	330		T33	678
valid_sources[0x3e]	2212	1			T9	62		T20	295		T116	1
valid_sources[0x3f]	2612	1			T9	67		T15	1		T20	306
valid_sources[0x40]	1695	1			T9	75		T20	295		T146	1
valid_sources[0x41]	2289	1			T9	62		T20	294		T33	612
valid_sources[0x42]	2213	1			T9	66		T20	281		T169	2
valid_sources[0x43]	1973	1			T9	78		T20	307		T33	646
valid_sources[0x44]	2267	1			T9	65		T39	1		T46	1
valid_sources[0x45]	2327	1			T9	79		T20	293		T33	845
valid_sources[0x46]	1862	1			T9	57		T7	1		T20	306
valid_sources[0x47]	1775	1			T9	76		T20	314		T33	484
valid_sources[0x48]	2026	1			T9	79		T20	326		T162	1
valid_sources[0x49]	2266	1			T9	70		T20	335		T33	767
valid_sources[0x4a]	2083	1			T9	74		T48	1		T20	342
valid_sources[0x4b]	2033	1			T9	69		T20	315		T33	753
valid_sources[0x4c]	2208	1			T4	1		T9	63		T20	319
valid_sources[0x4d]	2250	1			T9	68		T24	2		T20	306
valid_sources[0x4e]	2212	1			T13	1		T9	58		T20	301
valid_sources[0x4f]	2185	1			T2	1		T9	58		T7	2
valid_sources[0x50]	1812	1			T9	80		T20	309		T33	483
valid_sources[0x51]	2107	1			T9	66		T20	325		T33	762
valid_sources[0x52]	1939	1			T9	84		T20	257		T33	787
valid_sources[0x53]	2118	1			T28	1		T9	45		T57	1
valid_sources[0x54]	1965	1			T9	78		T20	321		T116	1
valid_sources[0x55]	2058	1			T9	77		T62	3		T57	1
valid_sources[0x56]	2255	1			T9	70		T20	319		T134	2
valid_sources[0x57]	2094	1			T9	53		T20	288		T33	657
valid_sources[0x58]	2012	1			T9	71		T20	323		T33	744
valid_sources[0x59]	2126	1			T9	77		T20	319		T173	1
valid_sources[0x5a]	2213	1			T9	69		T20	306		T33	824
valid_sources[0x5b]	2053	1			T9	73		T20	344		T166	1
valid_sources[0x5c]	2324	1			T5	1		T9	61		T7	3
valid_sources[0x5d]	1990	1			T9	58		T20	335		T174	1
valid_sources[0x5e]	2015	1			T9	55		T20	315		T33	758
valid_sources[0x5f]	2118	1			T9	74		T60	1		T20	319
valid_sources[0x60]	2381	1			T9	77		T39	1		T20	317
valid_sources[0x61]	2075	1			T9	70		T15	1		T20	311
valid_sources[0x62]	2022	1			T9	78		T61	1		T57	2
valid_sources[0x63]	1764	1			T9	55		T20	281		T33	710
valid_sources[0x64]	1891	1			T9	69		T20	319		T33	596
valid_sources[0x65]	1702	1			T9	73		T20	291		T33	612
valid_sources[0x66]	2427	1			T1	1		T9	70		T20	332
valid_sources[0x67]	2007	1			T9	80		T20	334		T33	559
valid_sources[0x68]	2404	1			T45	1		T9	65		T57	1
valid_sources[0x69]	2107	1			T9	56		T20	337		T33	616
valid_sources[0x6a]	2308	1			T9	74		T20	304		T33	642
valid_sources[0x6b]	1914	1			T9	69		T20	341		T33	608
valid_sources[0x6c]	2354	1			T9	60		T20	321		T119	3
valid_sources[0x6d]	1997	1			T9	72		T20	345		T172	2
valid_sources[0x6e]	1825	1			T6	6		T9	60		T20	314
valid_sources[0x6f]	1797	1			T9	75		T20	302		T33	594
valid_sources[0x70]	2074	1			T9	78		T57	1		T20	326
valid_sources[0x71]	1760	1			T9	65		T20	325		T33	579
valid_sources[0x72]	2198	1			T1	1		T9	79		T20	319
valid_sources[0x73]	2346	1			T3	1		T9	72		T20	276
valid_sources[0x74]	1811	1			T9	70		T46	2		T20	340
valid_sources[0x75]	1892	1			T9	69		T7	1		T20	320
valid_sources[0x76]	1890	1			T9	65		T20	323		T175	1
valid_sources[0x77]	1985	1			T9	65		T20	316		T33	589
valid_sources[0x78]	1827	1			T9	68		T57	1		T20	287
valid_sources[0x79]	1891	1			T9	79		T65	2		T20	307
valid_sources[0x7a]	2081	1			T9	77		T20	335		T167	1
valid_sources[0x7b]	2059	1			T9	84		T34	1		T20	320
valid_sources[0x7c]	2105	1			T9	57		T20	301		T23	2
valid_sources[0x7d]	2065	1			T9	69		T20	333		T146	1
valid_sources[0x7e]	2271	1			T9	78		T20	351		T33	644
valid_sources[0x7f]	2071	1			T9	78		T176	11		T20	279
valid_sources[0x80]	2135	1			T9	75		T49	1		T20	288

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

128572

1

T9

4170

T20

19068

T33

41242

values[0x0]

all_enables

biggest_size

190446

1

T1

4

T2

6

T29

1

values[0x1]

all_enables

biggest_size

191145

1

T1

3

T2

2

T3

1