SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 96.43 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 92.86 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
92.86 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 92.86 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 3038226 | 1 | T1 | 23 | T2 | 26 | T3 | 2 | ||||
auto[1] | 960049 | 1 | T9 | 31992 | T20 | 149009 | T31 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3998079 | 1 | T1 | 23 | T2 | 26 | T3 | 2 | ||||
values[1] | 19 | 1 | T110 | 2 | T107 | 1 | T148 | 1 | ||||
values[2] | 7 | 1 | T149 | 1 | T150 | 1 | T151 | 1 | ||||
values[3] | 106 | 1 | T110 | 3 | T107 | 8 | T111 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3998075 | 1 | T1 | 23 | T2 | 26 | T3 | 2 | ||||
values[1] | 25 | 1 | T110 | 1 | T107 | 5 | T111 | 1 | ||||
values[3] | 90 | 1 | T107 | 9 | T111 | 3 | T148 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3997975 | 1 | T1 | 23 | T2 | 26 | T3 | 2 | ||||
auto[TlIntgErrCmd] | 100 | 1 | T110 | 6 | T107 | 4 | T111 | 4 | ||||
auto[TlIntgErrData] | 104 | 1 | T110 | 2 | T107 | 6 | T148 | 6 | ||||
auto[TlIntgErrBoth] | 96 | 1 | T110 | 2 | T107 | 10 | T111 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 1494120 | 0 | T1 | 7 | T2 | 8 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1493915 | 1 | T1 | 7 | T2 | 8 | T3 | 1 | ||||
values[1] | 28 | 1 | T107 | 2 | T148 | 1 | T152 | 1 | ||||
values[2] | 4 | 1 | T110 | 1 | T153 | 1 | T154 | 1 | ||||
values[3] | 95 | 1 | T110 | 1 | T107 | 2 | T111 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1493916 | 1 | T1 | 7 | T2 | 8 | T3 | 1 | ||||
values[1] | 19 | 1 | T110 | 2 | T107 | 2 | T148 | 1 | ||||
values[2] | 11 | 1 | T107 | 1 | T148 | 1 | T155 | 1 | ||||
values[3] | 91 | 1 | T110 | 2 | T107 | 7 | T111 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1493820 | 1 | T1 | 7 | T2 | 8 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 96 | 1 | T110 | 1 | T107 | 3 | T111 | 5 | ||||
auto[TlIntgErrData] | 95 | 1 | T110 | 5 | T107 | 10 | T111 | 2 | ||||
auto[TlIntgErrBoth] | 109 | 1 | T110 | 4 | T107 | 7 | T111 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |