Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

2994257

1

T1

19

T2

19

T3

1

full_word

1004018

1

T1

4

T2

7

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3997975	1			T1	23		T2	26		T3	2
auto[TlIntgErrCmd]	100	1			T110	6		T107	4		T111	4
auto[TlIntgErrData]	104	1			T110	2		T107	6		T148	6
auto[TlIntgErrBoth]	96	1			T110	2		T107	10		T111	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

706636

1

T1

3

T2

4

T4

3

auto[1]

3291639

1

T1

20

T2

22

T3

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	309487	1			T2	2		T4	2		T28	1
auto[TlIntgErrNone]	partial	auto[1]	2684500	1			T1	19		T2	17		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	397015	1			T1	3		T2	2		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	606973	1			T1	1		T2	5		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T110	3		T107	2		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T110	3		T107	2		T111	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T152	1		T151	1		T154	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T152	1		T156	1		T154	2
auto[TlIntgErrData]	partial	auto[0]	41	1			T107	2		T148	4		T152	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T110	1		T107	4		T148	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T110	1		T152	1		T155	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T156	1		T157	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T110	2		T107	2		T111	4
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T107	6		T111	2		T148	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T107	1		T158	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T107	1		T148	1		T152	1