Assert Coverage for Module :
rv_dm_regs_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165728700 |
714668 |
0 |
0 |
T9 |
692719 |
22792 |
0 |
0 |
T18 |
0 |
260264 |
0 |
0 |
T20 |
0 |
110826 |
0 |
0 |
T24 |
106667 |
0 |
0 |
0 |
T33 |
0 |
234568 |
0 |
0 |
T34 |
32982 |
0 |
0 |
0 |
T39 |
5964 |
0 |
0 |
0 |
T40 |
3730 |
0 |
0 |
0 |
T46 |
783647 |
0 |
0 |
0 |
T47 |
193804 |
0 |
0 |
0 |
T48 |
558962 |
0 |
0 |
0 |
T52 |
0 |
155 |
0 |
0 |
T67 |
0 |
31231 |
0 |
0 |
T68 |
0 |
289 |
0 |
0 |
T69 |
0 |
61 |
0 |
0 |
T70 |
0 |
53 |
0 |
0 |
T71 |
0 |
33 |
0 |
0 |
T72 |
48478 |
0 |
0 |
0 |
T73 |
69954 |
0 |
0 |
0 |
late_debug_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165728700 |
2669 |
0 |
0 |
T52 |
439389 |
52 |
0 |
0 |
T53 |
334725 |
188 |
0 |
0 |
T71 |
18597 |
27 |
0 |
0 |
T74 |
30736 |
7 |
0 |
0 |
T75 |
62531 |
33 |
0 |
0 |
T105 |
34005 |
233 |
0 |
0 |
T106 |
9698 |
137 |
0 |
0 |
T107 |
500952 |
89 |
0 |
0 |
T108 |
12022 |
16 |
0 |
0 |
T109 |
22023 |
204 |
0 |
0 |
late_debug_enable_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165728700 |
3104 |
0 |
0 |
T52 |
439389 |
63 |
0 |
0 |
T53 |
334725 |
135 |
0 |
0 |
T71 |
18597 |
23 |
0 |
0 |
T74 |
30736 |
13 |
0 |
0 |
T75 |
62531 |
36 |
0 |
0 |
T105 |
34005 |
187 |
0 |
0 |
T106 |
9698 |
98 |
0 |
0 |
T107 |
500952 |
83 |
0 |
0 |
T108 |
12022 |
7 |
0 |
0 |
T109 |
22023 |
211 |
0 |
0 |