Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80134662 |
80087629 |
0 |
0 |
T1 |
632559 |
632357 |
0 |
0 |
T2 |
286019 |
285824 |
0 |
0 |
T3 |
11552 |
11484 |
0 |
0 |
T4 |
40848 |
40760 |
0 |
0 |
T12 |
161170 |
161100 |
0 |
0 |
T13 |
94254 |
93926 |
0 |
0 |
T14 |
40584 |
40318 |
0 |
0 |
T26 |
49072 |
49000 |
0 |
0 |
T28 |
68767 |
68707 |
0 |
0 |
T29 |
13613 |
13548 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80134662 |
80087629 |
0 |
0 |
T1 |
632559 |
632357 |
0 |
0 |
T2 |
286019 |
285824 |
0 |
0 |
T3 |
11552 |
11484 |
0 |
0 |
T4 |
40848 |
40760 |
0 |
0 |
T12 |
161170 |
161100 |
0 |
0 |
T13 |
94254 |
93926 |
0 |
0 |
T14 |
40584 |
40318 |
0 |
0 |
T26 |
49072 |
49000 |
0 |
0 |
T28 |
68767 |
68707 |
0 |
0 |
T29 |
13613 |
13548 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80134662 |
80087629 |
0 |
0 |
T1 |
632559 |
632357 |
0 |
0 |
T2 |
286019 |
285824 |
0 |
0 |
T3 |
11552 |
11484 |
0 |
0 |
T4 |
40848 |
40760 |
0 |
0 |
T12 |
161170 |
161100 |
0 |
0 |
T13 |
94254 |
93926 |
0 |
0 |
T14 |
40584 |
40318 |
0 |
0 |
T26 |
49072 |
49000 |
0 |
0 |
T28 |
68767 |
68707 |
0 |
0 |
T29 |
13613 |
13548 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80134662 |
80087629 |
0 |
0 |
T1 |
632559 |
632357 |
0 |
0 |
T2 |
286019 |
285824 |
0 |
0 |
T3 |
11552 |
11484 |
0 |
0 |
T4 |
40848 |
40760 |
0 |
0 |
T12 |
161170 |
161100 |
0 |
0 |
T13 |
94254 |
93926 |
0 |
0 |
T14 |
40584 |
40318 |
0 |
0 |
T26 |
49072 |
49000 |
0 |
0 |
T28 |
68767 |
68707 |
0 |
0 |
T29 |
13613 |
13548 |
0 |
0 |