SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.16 | 100.00 | 85.71 | 97.60 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
70.34 | 86.27 | 76.47 | 57.14 | 81.82 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.14 | 100.00 | 100.00 | 85.71 | 100.00 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1458 | 1458 | 0 | 0 |
OutputsKnown_A | 480807972 | 480525774 | 0 | 0 |
gen_flops.OutputDelay_A | 240403986 | 240256695 | 0 | 2187 |
gen_no_flops.OutputDelay_A | 240403986 | 240262887 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1458 | 1458 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T14 | 6 | 6 | 0 | 0 |
T26 | 6 | 6 | 0 | 0 |
T28 | 6 | 6 | 0 | 0 |
T29 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 480807972 | 480525774 | 0 | 0 |
T1 | 3795354 | 3794142 | 0 | 0 |
T2 | 1716114 | 1714944 | 0 | 0 |
T3 | 69312 | 68904 | 0 | 0 |
T4 | 245088 | 244560 | 0 | 0 |
T12 | 967020 | 966600 | 0 | 0 |
T13 | 565524 | 563556 | 0 | 0 |
T14 | 243504 | 241908 | 0 | 0 |
T26 | 294432 | 294000 | 0 | 0 |
T28 | 412602 | 412242 | 0 | 0 |
T29 | 81678 | 81288 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 240403986 | 240256695 | 0 | 2187 |
T1 | 1897677 | 1897044 | 0 | 9 |
T2 | 858057 | 857445 | 0 | 9 |
T3 | 34656 | 34443 | 0 | 9 |
T4 | 122544 | 122271 | 0 | 9 |
T12 | 483510 | 483291 | 0 | 9 |
T13 | 282762 | 281733 | 0 | 9 |
T14 | 121752 | 120918 | 0 | 9 |
T26 | 147216 | 146991 | 0 | 9 |
T28 | 206301 | 206112 | 0 | 9 |
T29 | 40839 | 40635 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 240403986 | 240262887 | 0 | 0 |
T1 | 1897677 | 1897071 | 0 | 0 |
T2 | 858057 | 857472 | 0 | 0 |
T3 | 34656 | 34452 | 0 | 0 |
T4 | 122544 | 122280 | 0 | 0 |
T12 | 483510 | 483300 | 0 | 0 |
T13 | 282762 | 281778 | 0 | 0 |
T14 | 121752 | 120954 | 0 | 0 |
T26 | 147216 | 147000 | 0 | 0 |
T28 | 206301 | 206121 | 0 | 0 |
T29 | 40839 | 40644 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_flops.OutputDelay_A | 80134662 | 80085565 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80085565 | 0 | 729 |
T1 | 632559 | 632348 | 0 | 3 |
T2 | 286019 | 285815 | 0 | 3 |
T3 | 11552 | 11481 | 0 | 3 |
T4 | 40848 | 40757 | 0 | 3 |
T12 | 161170 | 161097 | 0 | 3 |
T13 | 94254 | 93911 | 0 | 3 |
T14 | 40584 | 40306 | 0 | 3 |
T26 | 49072 | 48997 | 0 | 3 |
T28 | 68767 | 68704 | 0 | 3 |
T29 | 13613 | 13545 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_flops.OutputDelay_A | 80134662 | 80085565 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80085565 | 0 | 729 |
T1 | 632559 | 632348 | 0 | 3 |
T2 | 286019 | 285815 | 0 | 3 |
T3 | 11552 | 11481 | 0 | 3 |
T4 | 40848 | 40757 | 0 | 3 |
T12 | 161170 | 161097 | 0 | 3 |
T13 | 94254 | 93911 | 0 | 3 |
T14 | 40584 | 40306 | 0 | 3 |
T26 | 49072 | 48997 | 0 | 3 |
T28 | 68767 | 68704 | 0 | 3 |
T29 | 13613 | 13545 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80134662 | 80087629 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_flops.OutputDelay_A | 80134662 | 80085565 | 0 | 729 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80085565 | 0 | 729 |
T1 | 632559 | 632348 | 0 | 3 |
T2 | 286019 | 285815 | 0 | 3 |
T3 | 11552 | 11481 | 0 | 3 |
T4 | 40848 | 40757 | 0 | 3 |
T12 | 161170 | 161097 | 0 | 3 |
T13 | 94254 | 93911 | 0 | 3 |
T14 | 40584 | 40306 | 0 | 3 |
T26 | 49072 | 48997 | 0 | 3 |
T28 | 68767 | 68704 | 0 | 3 |
T29 | 13613 | 13545 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80134662 | 80087629 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 243 | 243 | 0 | 0 |
OutputsKnown_A | 80134662 | 80087629 | 0 | 0 |
gen_no_flops.OutputDelay_A | 80134662 | 80087629 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 243 | 243 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 80134662 | 80087629 | 0 | 0 |
T1 | 632559 | 632357 | 0 | 0 |
T2 | 286019 | 285824 | 0 | 0 |
T3 | 11552 | 11484 | 0 | 0 |
T4 | 40848 | 40760 | 0 | 0 |
T12 | 161170 | 161100 | 0 | 0 |
T13 | 94254 | 93926 | 0 | 0 |
T14 | 40584 | 40318 | 0 | 0 |
T26 | 49072 | 49000 | 0 | 0 |
T28 | 68767 | 68707 | 0 | 0 |
T29 | 13613 | 13548 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |