Unified Coverage Report :: Module :: dm_sba

Module : dm_sba

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.43	94.81	94.44		100.00	76.47

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dm_top.i_dm_sba	92.62	94.81	94.44		100.00	81.25

---

Module Instance : tb.dut.u_dm_top.i_dm_sba

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	94.81	94.44		100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.62	94.81	94.44		100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_dm_top

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : dm_sba

	Line No.	Total	Covered	Percent
TOTAL		77	73	94.81
CONT_ASSIGN	69	1	1	100.00
ALWAYS	72	7	7	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	101	54	50	92.59
ALWAYS	193	3	3	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
72	1	1
75	1	1
77	1	1
80	1	1
83	1	1(1 unreachable)
84	1	1
86	1	1
92	1	1
96	1	1
97	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
107	1	1
108	1	1
110	1	1
112	1	1
114	1	1
117	2	2
			MISSING_ELSE
119	2	2
			MISSING_ELSE
121	2	2
			MISSING_ELSE
125	1	1
126	2	2
			==> MISSING_ELSE
127	2	2
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	2	2
			==> MISSING_ELSE
138	1	1
139	1	1
141	1	1
143	1	1
144	0	1
145	0	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
			MISSING_ELSE
155	1	1
156	1	1
158	1	1
160	1	1
161	0	1
162	0	1
164	1	1
165	1	1
166	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
			MISSING_ELSE
193	1	1
194	1	1
196	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1

---

Cond Coverage for Module : dm_sba

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (addr_incr_en ? ((32'(1'b1) << sbaccess_i)) : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       117
 EXPRESSION (sbaddress_write_valid_i && sbreadonaddr_i)
             -----------1-----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T11,T12,T13

 LINE       121
 EXPRESSION (sbdata_read_valid_i && sbreadondata_i)
             ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T26,T27

 LINE       175
 EXPRESSION ((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle))
             ---------------1--------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T26,T27

 LINE       175
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       183
 EXPRESSION (((|(sbaddress_i & (~sbaccess_mask)))) && (state_q != Idle))
             ------------------1------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T26,T27

 LINE       183
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

---

FSM Coverage for Module : dm_sba

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Idle	139	Covered	T1,T2,T3
Read	117	Covered	T11,T12,T13
WaitRead	127	Covered	T11,T12,T13
WaitWrite	134	Covered	T26
Write	119	Covered	T26,T27

transitions	Line No.	Covered	Tests
Idle->Read	117	Covered	T11,T12,T13
Idle->Write	119	Covered	T26,T27
Read->Idle	177	Covered	T26,T27
Read->WaitRead	127	Covered	T11,T12,T13
WaitRead->Idle	139	Covered	T11,T12,T13
WaitWrite->Idle	156	Covered	T26
Write->Idle	177	Covered	T26,T27
Write->WaitWrite	134	Covered	T26

---

Branch Coverage for Module : dm_sba

	Line No.	Total	Covered	Percent
Branches		34	26	76.47
TERNARY	96	2	1	50.00
CASE	75	5	5	100.00
CASE	114	21	14	66.67
IF	175	2	2	100.00
IF	183	2	2	100.00
IF	193	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	(addr_incr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	case (sbaccess_i)
-2-:	83	if ((BusWidth == 32'd64))

Branches:

-1-	-2-	Status	Tests
3'b000	-	Covered	T26
3'b001	-	Covered	T26,T27
3'b010	1	Unreachable
3'b010	0	Covered	T1,T2,T3
3'b011	-	Covered	T26,T27
default	-	Covered	T26,T27

	LineNo.	Expression
-1-:	114	case (state_q)
-2-:	117	if ((sbaddress_write_valid_i && sbreadonaddr_i))
-3-:	119	if (sbdata_write_valid_i)
-4-:	121	if ((sbdata_read_valid_i && sbreadondata_i))
-5-:	126	if (ReadByteEnable)
-6-:	127	if (gnt)
-7-:	134	if (gnt)
-8-:	138	if (sbdata_valid_o)
-9-:	143	if (master_r_other_err_i)
-10-:	147	if (master_r_err_i)
-11-:	155	if (sbdata_valid_o)
-12-:	160	if (master_r_other_err_i)
-13-:	164	if (master_r_err_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
Idle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27
Idle	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T26,T27
Idle	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Read	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
Read	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
Read	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T11,T12,T13
Read	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13
Write	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27
Write	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
WaitRead	-	-	-	-	-	-	1	1	-	-	-	-	Not Covered
WaitRead	-	-	-	-	-	-	1	0	1	-	-	-	Covered	T11,T12,T25
WaitRead	-	-	-	-	-	-	1	0	0	-	-	-	Covered	T13,T59
WaitRead	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T13,T59
WaitWrite	-	-	-	-	-	-	-	-	-	1	1	-	Not Covered
WaitWrite	-	-	-	-	-	-	-	-	-	1	0	1	Covered	T26
WaitWrite	-	-	-	-	-	-	-	-	-	1	0	0	Not Covered
WaitWrite	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	175	if (((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle)))

Branches:

-1-	Status	Tests
1	Covered	T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (((|(sbaddress_i & (~sbaccess_mask))) && (state_q != Idle)))

Branches:

-1-	Status	Tests
1	Covered	T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_dm_top.i_dm_sba

	Line No.	Total	Covered	Percent
TOTAL		77	73	94.81
CONT_ASSIGN	69	1	1	100.00
ALWAYS	72	7	7	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	101	54	50	92.59
ALWAYS	193	3	3	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	209	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
72	1	1
75	1	1
77	1	1
80	1	1
83	1	1(1 unreachable)
84	1	1
86	1	1
92	1	1
96	1	1
97	1	1
101	1	1
102	1	1
103	1	1
104	1	1
105	1	1
107	1	1
108	1	1
110	1	1
112	1	1
114	1	1
117	2	2
			MISSING_ELSE
119	2	2
			MISSING_ELSE
121	2	2
			MISSING_ELSE
125	1	1
126	2	2
			==> MISSING_ELSE
127	2	2
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	2	2
			==> MISSING_ELSE
138	1	1
139	1	1
141	1	1
143	1	1
144	0	1
145	0	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
			MISSING_ELSE
155	1	1
156	1	1
158	1	1
160	1	1
161	0	1
162	0	1
164	1	1
165	1	1
166	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
175	1	1
176	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
			MISSING_ELSE
193	1	1
194	1	1
196	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1

---

Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_sba

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (addr_incr_en ? ((32'(1'b1) << sbaccess_i)) : '0)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       117
 EXPRESSION (sbaddress_write_valid_i && sbreadonaddr_i)
             -----------1-----------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T11,T12,T13

 LINE       121
 EXPRESSION (sbdata_read_valid_i && sbreadondata_i)
             ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T26,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T26,T27

 LINE       175
 EXPRESSION ((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle))
             ---------------1--------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T26,T27

 LINE       175
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       183
 EXPRESSION (((|(sbaddress_i & (~sbaccess_mask)))) && (state_q != Idle))
             ------------------1------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T26,T27
1	1	Covered	T26,T27

 LINE       183
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

---

FSM Coverage for Instance : tb.dut.u_dm_top.i_dm_sba

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Idle	139	Covered	T1,T2,T3
Read	117	Covered	T11,T12,T13
WaitRead	127	Covered	T11,T12,T13
WaitWrite	134	Covered	T26
Write	119	Covered	T26,T27

transitions	Line No.	Covered	Tests
Idle->Read	117	Covered	T11,T12,T13
Idle->Write	119	Covered	T26,T27
Read->Idle	177	Covered	T26,T27
Read->WaitRead	127	Covered	T11,T12,T13
WaitRead->Idle	139	Covered	T11,T12,T13
WaitWrite->Idle	156	Covered	T26
Write->Idle	177	Covered	T26,T27
Write->WaitWrite	134	Covered	T26

---

Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_sba

	Line No.	Total	Covered	Percent
Branches		32	26	81.25
TERNARY	96	2	1	50.00
CASE	75	5	5	100.00
CASE	114	19	14	73.68
IF	175	2	2	100.00
IF	183	2	2	100.00
IF	193	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_sba.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	(addr_incr_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	case (sbaccess_i)
-2-:	83	if ((BusWidth == 32'd64))

Branches:

-1-	-2-	Status	Tests
3'b000	-	Covered	T26
3'b001	-	Covered	T26,T27
3'b010	1	Unreachable
3'b010	0	Covered	T1,T2,T3
3'b011	-	Covered	T26,T27
default	-	Covered	T26,T27

	LineNo.	Expression
-1-:	114	case (state_q)
-2-:	117	if ((sbaddress_write_valid_i && sbreadonaddr_i))
-3-:	119	if (sbdata_write_valid_i)
-4-:	121	if ((sbdata_read_valid_i && sbreadondata_i))
-5-:	126	if (ReadByteEnable)
-6-:	127	if (gnt)
-7-:	134	if (gnt)
-8-:	138	if (sbdata_valid_o)
-9-:	143	if (master_r_other_err_i)
-10-:	147	if (master_r_err_i)
-11-:	155	if (sbdata_valid_o)
-12-:	160	if (master_r_other_err_i)
-13-:	164	if (master_r_err_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests	Exclude Annotation
Idle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
Idle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27
Idle	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T26,T27
Idle	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Read	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
Read	-	-	-	0	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
Read	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T11,T12,T13
Read	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13
Write	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27
Write	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
WaitRead	-	-	-	-	-	-	1	1	-	-	-	-	Not Covered
WaitRead	-	-	-	-	-	-	1	0	1	-	-	-	Covered	T11,T12,T25
WaitRead	-	-	-	-	-	-	1	0	0	-	-	-	Covered	T13,T59
WaitRead	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T13,T59
WaitWrite	-	-	-	-	-	-	-	-	-	1	1	-	Not Covered
WaitWrite	-	-	-	-	-	-	-	-	-	1	0	1	Covered	T26
WaitWrite	-	-	-	-	-	-	-	-	-	1	0	0	Not Covered
WaitWrite	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	175	if (((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle)))

Branches:

-1-	Status	Tests
1	Covered	T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if (((|(sbaddress_i & (~sbaccess_mask))) && (state_q != Idle)))

Branches:

-1-	Status	Tests
1	Covered	T26,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3