Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	57.31			57.31
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.31			57.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.31			57.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T32	Yes	T2,T3,T32	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
err_o[1:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	149	57.31
Total Bits 0->1	130	76	58.46
Total Bits 1->0	130	73	56.15

Ports	4	2	50.00
Port Bits	260	149	57.31
Port Bits 0->1	130	76	58.46
Port Bits 1->0	130	73	56.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T35	INPUT
data_o[26:0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	OUTPUT
data_o[27]	No	No		Yes	T68,T69	OUTPUT
data_o[28]	Yes	Yes	*T31,*T70	Yes	T31,T70	OUTPUT
data_o[29]	No	No		No		OUTPUT
data_o[30]	Yes	Yes	*T14,*T71,*T72	Yes	T14,T71,T72	OUTPUT
data_o[31]	No	No		Yes	T73,T74	OUTPUT
data_o[39:32]	Yes	Yes	*T75,*T72,*T76	Yes	T75,T72,T77	OUTPUT
data_o[40]	No	No		Yes	T78	OUTPUT
data_o[56:41]	Yes	Yes	T79,T61,T80	Yes	T81,T79,T61	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T32	OUTPUT
err_o[1:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T32,T4,*T82	Yes	T32,T4,T82	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	INPUT
data_o[56:0]	Yes	Yes	T32,T4,T82	Yes	T32,T4,T82	OUTPUT
syndrome_o[6:0]	Yes	Yes	T32,T82,T11	Yes	T32,T82,T11	OUTPUT
err_o[1:0]	Yes	Yes	T32,T82,T83	Yes	T32,T82,T83	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,T4	Yes	T2,T3,T4	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T17,T29	Yes	T2,T17,T29	OUTPUT
err_o[1:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT

*Tests covering at least one bit in the range