Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	264681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

608935

1

T3

5

T4

2

T13

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	483077	1			T3	5		T4	3		T13	2
values[0x0]	165129	1			T7	1		T3	5		T4	2
values[0x1]	225410	1			T3	3		T4	2		T5	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	174720	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

698896

1

T3

5

T4

2

T13

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3445	1			T53	32		T48	49		T11	25
valid_sources[0x01]	3054	1			T53	20		T48	38		T11	25
valid_sources[0x02]	3151	1			T53	20		T48	36		T11	21
valid_sources[0x03]	3602	1			T10	2		T53	27		T23	2
valid_sources[0x04]	3448	1			T53	18		T48	31		T11	32
valid_sources[0x05]	3540	1			T53	18		T48	26		T11	31
valid_sources[0x06]	3230	1			T53	26		T48	31		T11	22
valid_sources[0x07]	3586	1			T15	1		T53	39		T48	34
valid_sources[0x08]	3250	1			T53	21		T48	35		T11	31
valid_sources[0x09]	3008	1			T6	3		T53	14		T16	1
valid_sources[0x0a]	3473	1			T53	22		T48	33		T11	19
valid_sources[0x0b]	3174	1			T53	30		T48	41		T11	38
valid_sources[0x0c]	2886	1			T53	24		T16	1		T48	35
valid_sources[0x0d]	3526	1			T53	20		T48	27		T56	1
valid_sources[0x0e]	3467	1			T53	22		T48	28		T56	1
valid_sources[0x0f]	3461	1			T53	31		T48	41		T11	32
valid_sources[0x10]	3117	1			T53	18		T48	43		T56	1
valid_sources[0x11]	3395	1			T53	18		T16	1		T48	25
valid_sources[0x12]	3340	1			T53	26		T48	26		T11	29
valid_sources[0x13]	3074	1			T53	27		T48	36		T11	26
valid_sources[0x14]	4919	1			T5	2		T41	2		T53	20
valid_sources[0x15]	3140	1			T53	20		T48	32		T11	31
valid_sources[0x16]	3385	1			T53	24		T16	1		T48	46
valid_sources[0x17]	3158	1			T53	21		T48	32		T11	30
valid_sources[0x18]	3527	1			T53	22		T48	36		T11	23
valid_sources[0x19]	3424	1			T58	7		T53	23		T48	26
valid_sources[0x1a]	3755	1			T53	21		T48	33		T17	1
valid_sources[0x1b]	3125	1			T53	21		T48	22		T11	22
valid_sources[0x1c]	3182	1			T53	13		T48	30		T11	32
valid_sources[0x1d]	3480	1			T53	24		T48	35		T11	28
valid_sources[0x1e]	3704	1			T53	20		T48	32		T11	12
valid_sources[0x1f]	3589	1			T4	7		T53	25		T48	30
valid_sources[0x20]	3245	1			T53	29		T48	30		T11	37
valid_sources[0x21]	3869	1			T53	23		T48	36		T11	25
valid_sources[0x22]	3998	1			T5	1		T53	12		T48	40
valid_sources[0x23]	2848	1			T53	18		T93	1		T48	24
valid_sources[0x24]	4356	1			T53	19		T48	27		T11	24
valid_sources[0x25]	3553	1			T18	2		T53	25		T48	37
valid_sources[0x26]	3572	1			T5	1		T53	22		T48	39
valid_sources[0x27]	3083	1			T53	29		T48	42		T11	29
valid_sources[0x28]	2778	1			T53	16		T48	33		T11	29
valid_sources[0x29]	2961	1			T53	21		T48	36		T11	33
valid_sources[0x2a]	3904	1			T53	22		T48	32		T11	27
valid_sources[0x2b]	3966	1			T46	2		T53	23		T48	29
valid_sources[0x2c]	3298	1			T53	25		T48	21		T11	29
valid_sources[0x2d]	3469	1			T53	20		T48	36		T11	33
valid_sources[0x2e]	3366	1			T5	2		T53	15		T48	41
valid_sources[0x2f]	3746	1			T53	21		T48	36		T11	33
valid_sources[0x30]	3502	1			T53	16		T48	37		T11	24
valid_sources[0x31]	3821	1			T98	2		T53	20		T23	1
valid_sources[0x32]	4359	1			T6	3		T53	22		T48	32
valid_sources[0x33]	3117	1			T53	19		T48	26		T184	1
valid_sources[0x34]	3550	1			T53	26		T48	39		T11	26
valid_sources[0x35]	3652	1			T53	20		T16	1		T48	31
valid_sources[0x36]	2837	1			T53	15		T48	38		T11	26
valid_sources[0x37]	3005	1			T53	21		T48	52		T11	29
valid_sources[0x38]	3204	1			T53	26		T48	38		T11	21
valid_sources[0x39]	3107	1			T53	19		T48	45		T11	18
valid_sources[0x3a]	3479	1			T53	31		T48	27		T11	22
valid_sources[0x3b]	2780	1			T53	26		T48	24		T11	28
valid_sources[0x3c]	3353	1			T53	19		T48	41		T11	28
valid_sources[0x3d]	3594	1			T53	21		T167	2		T48	34
valid_sources[0x3e]	3162	1			T53	17		T48	29		T17	1
valid_sources[0x3f]	3366	1			T38	2		T53	23		T48	32
valid_sources[0x40]	3349	1			T10	1		T53	19		T48	29
valid_sources[0x41]	2942	1			T53	28		T48	43		T11	33
valid_sources[0x42]	3749	1			T53	21		T48	36		T11	28
valid_sources[0x43]	3280	1			T53	20		T48	34		T11	17
valid_sources[0x44]	3692	1			T53	19		T48	28		T11	24
valid_sources[0x45]	3902	1			T68	2		T53	27		T48	31
valid_sources[0x46]	3331	1			T53	16		T48	38		T11	28
valid_sources[0x47]	3131	1			T53	19		T48	42		T11	22
valid_sources[0x48]	3898	1			T53	19		T48	33		T11	25
valid_sources[0x49]	3148	1			T53	33		T48	31		T11	22
valid_sources[0x4a]	3541	1			T53	23		T48	34		T11	27
valid_sources[0x4b]	3573	1			T53	23		T48	29		T11	26
valid_sources[0x4c]	3121	1			T5	1		T53	23		T48	34
valid_sources[0x4d]	2799	1			T53	28		T48	29		T11	21
valid_sources[0x4e]	3218	1			T53	19		T48	28		T11	21
valid_sources[0x4f]	2974	1			T53	17		T48	36		T11	29
valid_sources[0x50]	3187	1			T53	26		T52	7		T48	33
valid_sources[0x51]	3424	1			T53	20		T48	37		T11	22
valid_sources[0x52]	3347	1			T53	30		T48	32		T11	24
valid_sources[0x53]	2877	1			T53	17		T48	33		T11	31
valid_sources[0x54]	4377	1			T8	4		T53	17		T48	37
valid_sources[0x55]	4028	1			T53	19		T48	35		T11	26
valid_sources[0x56]	2986	1			T53	22		T48	38		T11	30
valid_sources[0x57]	3350	1			T53	32		T75	1		T48	29
valid_sources[0x58]	3305	1			T53	15		T48	31		T11	21
valid_sources[0x59]	3066	1			T53	25		T48	36		T11	29
valid_sources[0x5a]	3924	1			T53	14		T48	28		T11	33
valid_sources[0x5b]	3291	1			T13	1		T53	28		T48	39
valid_sources[0x5c]	3257	1			T53	26		T182	1		T48	25
valid_sources[0x5d]	3521	1			T53	27		T48	26		T11	23
valid_sources[0x5e]	3062	1			T53	24		T183	6		T48	32
valid_sources[0x5f]	3674	1			T53	16		T48	28		T11	26
valid_sources[0x60]	3275	1			T6	1		T53	27		T48	36
valid_sources[0x61]	3384	1			T53	26		T48	33		T11	26
valid_sources[0x62]	4026	1			T53	23		T48	42		T11	34
valid_sources[0x63]	4088	1			T5	1		T53	19		T48	34
valid_sources[0x64]	3314	1			T53	21		T48	35		T56	4
valid_sources[0x65]	3069	1			T53	26		T48	43		T11	20
valid_sources[0x66]	3231	1			T53	29		T21	1		T48	49
valid_sources[0x67]	3315	1			T53	20		T48	50		T11	24
valid_sources[0x68]	3530	1			T53	29		T48	39		T11	34
valid_sources[0x69]	3204	1			T53	19		T48	20		T11	26
valid_sources[0x6a]	3152	1			T38	1		T53	32		T48	43
valid_sources[0x6b]	2915	1			T53	31		T23	1		T48	22
valid_sources[0x6c]	3801	1			T53	22		T48	29		T11	24
valid_sources[0x6d]	3005	1			T47	2		T53	16		T48	39
valid_sources[0x6e]	4183	1			T7	1		T10	1		T53	18
valid_sources[0x6f]	3684	1			T53	23		T48	33		T11	30
valid_sources[0x70]	3349	1			T53	16		T48	44		T11	34
valid_sources[0x71]	4214	1			T53	17		T48	37		T11	20
valid_sources[0x72]	3201	1			T53	27		T48	32		T11	22
valid_sources[0x73]	3423	1			T53	31		T48	30		T56	1
valid_sources[0x74]	3251	1			T53	14		T48	29		T11	36
valid_sources[0x75]	3571	1			T53	27		T48	40		T11	26
valid_sources[0x76]	3527	1			T5	1		T53	17		T48	38
valid_sources[0x77]	3868	1			T53	22		T16	2		T48	29
valid_sources[0x78]	3708	1			T53	23		T48	40		T11	31
valid_sources[0x79]	3391	1			T53	27		T48	36		T11	18
valid_sources[0x7a]	3022	1			T53	25		T48	39		T11	32
valid_sources[0x7b]	3603	1			T53	14		T48	32		T17	18
valid_sources[0x7c]	3884	1			T6	1		T53	20		T93	1
valid_sources[0x7d]	3583	1			T53	31		T48	32		T11	28
valid_sources[0x7e]	3362	1			T53	20		T48	40		T11	30
valid_sources[0x7f]	3919	1			T53	26		T48	31		T11	20
valid_sources[0x80]	3192	1			T53	21		T95	1		T48	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

294565

1

T3

2

T4

1

T13

1

values[0x0]

all_enables

biggest_size

157260

1

T3

2

T4

1

T5

1

values[0x1]

all_enables

biggest_size

157110

1

T3

1

T5

2

T40

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113988

1

T1

2

T2

1

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33887	1			T53	720		T48	1391		T11	1321
values[0x0]	43182	1			T1	10		T2	1		T3	2
values[0x1]	45295	1			T1	3		T7	1		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

116916

1

T1

2

T2

1

T7

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	388	1			T53	10		T48	22		T11	30
valid_sources[0x01]	541	1			T53	8		T48	20		T11	23
valid_sources[0x02]	498	1			T1	2		T53	12		T48	23
valid_sources[0x03]	549	1			T53	7		T48	27		T11	13
valid_sources[0x04]	379	1			T53	9		T48	22		T195	1
valid_sources[0x05]	538	1			T53	20		T48	24		T11	20
valid_sources[0x06]	369	1			T53	12		T48	22		T11	19
valid_sources[0x07]	636	1			T9	1		T53	12		T16	1
valid_sources[0x08]	562	1			T53	13		T48	22		T11	22
valid_sources[0x09]	506	1			T53	12		T48	28		T11	31
valid_sources[0x0a]	558	1			T53	13		T48	17		T11	19
valid_sources[0x0b]	632	1			T12	3		T53	12		T196	1
valid_sources[0x0c]	429	1			T53	12		T48	29		T87	1
valid_sources[0x0d]	429	1			T34	1		T53	9		T48	17
valid_sources[0x0e]	432	1			T53	8		T197	1		T185	1
valid_sources[0x0f]	452	1			T5	3		T53	10		T48	27
valid_sources[0x10]	397	1			T53	11		T48	24		T11	16
valid_sources[0x11]	379	1			T53	14		T48	26		T11	46
valid_sources[0x12]	435	1			T13	1		T28	2		T53	15
valid_sources[0x13]	380	1			T58	1		T53	11		T48	20
valid_sources[0x14]	441	1			T46	1		T53	6		T198	1
valid_sources[0x15]	384	1			T33	1		T39	1		T53	11
valid_sources[0x16]	494	1			T53	9		T48	26		T11	19
valid_sources[0x17]	343	1			T53	12		T48	20		T11	8
valid_sources[0x18]	359	1			T53	11		T48	16		T11	16
valid_sources[0x19]	567	1			T53	8		T16	1		T31	1
valid_sources[0x1a]	1235	1			T53	16		T48	18		T11	27
valid_sources[0x1b]	440	1			T53	10		T48	25		T11	15
valid_sources[0x1c]	512	1			T139	1		T53	6		T48	16
valid_sources[0x1d]	425	1			T5	1		T15	7		T53	8
valid_sources[0x1e]	480	1			T53	12		T183	8		T48	22
valid_sources[0x1f]	423	1			T10	1		T53	10		T48	21
valid_sources[0x20]	373	1			T53	15		T48	39		T11	13
valid_sources[0x21]	483	1			T53	17		T48	13		T199	1
valid_sources[0x22]	376	1			T53	17		T200	1		T197	2
valid_sources[0x23]	413	1			T53	17		T54	1		T78	2
valid_sources[0x24]	469	1			T10	3		T53	7		T99	1
valid_sources[0x25]	368	1			T139	7		T53	12		T48	25
valid_sources[0x26]	825	1			T33	1		T53	12		T48	11
valid_sources[0x27]	470	1			T53	13		T48	18		T11	34
valid_sources[0x28]	504	1			T53	7		T201	1		T48	25
valid_sources[0x29]	424	1			T6	1		T53	10		T48	22
valid_sources[0x2a]	379	1			T38	2		T53	13		T16	1
valid_sources[0x2b]	396	1			T53	15		T197	1		T48	28
valid_sources[0x2c]	462	1			T53	11		T48	28		T11	35
valid_sources[0x2d]	465	1			T139	1		T53	11		T48	14
valid_sources[0x2e]	415	1			T68	1		T53	12		T201	2
valid_sources[0x2f]	534	1			T53	12		T48	23		T11	33
valid_sources[0x30]	405	1			T53	12		T99	1		T48	19
valid_sources[0x31]	466	1			T53	10		T48	14		T11	3
valid_sources[0x32]	551	1			T53	13		T48	19		T11	15
valid_sources[0x33]	662	1			T53	10		T48	26		T11	16
valid_sources[0x34]	385	1			T6	1		T53	13		T48	16
valid_sources[0x35]	457	1			T53	11		T201	1		T48	14
valid_sources[0x36]	421	1			T53	8		T48	11		T11	18
valid_sources[0x37]	494	1			T53	21		T16	1		T202	1
valid_sources[0x38]	468	1			T53	12		T48	26		T11	43
valid_sources[0x39]	509	1			T7	1		T33	1		T53	9
valid_sources[0x3a]	373	1			T53	12		T202	2		T48	22
valid_sources[0x3b]	466	1			T53	13		T48	24		T11	19
valid_sources[0x3c]	374	1			T53	12		T124	1		T48	13
valid_sources[0x3d]	434	1			T38	1		T53	12		T48	17
valid_sources[0x3e]	446	1			T47	1		T53	10		T42	1
valid_sources[0x3f]	628	1			T5	1		T53	7		T48	15
valid_sources[0x40]	393	1			T53	7		T48	21		T11	13
valid_sources[0x41]	342	1			T53	11		T124	2		T48	24
valid_sources[0x42]	350	1			T53	9		T48	19		T17	2
valid_sources[0x43]	356	1			T53	10		T48	25		T11	11
valid_sources[0x44]	425	1			T53	10		T48	23		T11	21
valid_sources[0x45]	374	1			T33	1		T53	18		T48	32
valid_sources[0x46]	430	1			T53	7		T48	21		T11	34
valid_sources[0x47]	483	1			T33	1		T53	11		T48	16
valid_sources[0x48]	537	1			T139	2		T53	13		T48	26
valid_sources[0x49]	377	1			T53	11		T48	23		T11	4
valid_sources[0x4a]	395	1			T98	1		T53	14		T179	1
valid_sources[0x4b]	417	1			T1	1		T34	1		T53	13
valid_sources[0x4c]	372	1			T53	12		T201	1		T48	21
valid_sources[0x4d]	481	1			T53	6		T48	27		T11	18
valid_sources[0x4e]	629	1			T53	10		T48	13		T11	16
valid_sources[0x4f]	799	1			T14	1		T53	17		T202	1
valid_sources[0x50]	421	1			T53	6		T48	18		T11	21
valid_sources[0x51]	394	1			T9	1		T53	10		T48	24
valid_sources[0x52]	481	1			T34	2		T53	12		T48	15
valid_sources[0x53]	455	1			T53	21		T48	29		T11	33
valid_sources[0x54]	579	1			T53	9		T48	14		T11	26
valid_sources[0x55]	534	1			T53	18		T198	1		T21	4
valid_sources[0x56]	349	1			T53	14		T48	21		T11	13
valid_sources[0x57]	480	1			T53	11		T48	27		T11	35
valid_sources[0x58]	458	1			T53	11		T123	2		T202	1
valid_sources[0x59]	800	1			T53	19		T49	4		T48	16
valid_sources[0x5a]	451	1			T29	5		T53	15		T48	17
valid_sources[0x5b]	522	1			T53	12		T31	1		T48	24
valid_sources[0x5c]	422	1			T53	20		T48	27		T11	13
valid_sources[0x5d]	468	1			T53	7		T48	22		T11	14
valid_sources[0x5e]	431	1			T33	1		T53	7		T203	1
valid_sources[0x5f]	355	1			T40	1		T53	5		T48	17
valid_sources[0x60]	523	1			T53	8		T48	22		T11	16
valid_sources[0x61]	622	1			T53	8		T202	1		T48	28
valid_sources[0x62]	545	1			T1	1		T53	12		T204	2
valid_sources[0x63]	377	1			T53	15		T201	1		T48	20
valid_sources[0x64]	475	1			T53	14		T205	1		T48	23
valid_sources[0x65]	607	1			T53	11		T205	1		T48	19
valid_sources[0x66]	510	1			T1	1		T139	1		T53	13
valid_sources[0x67]	331	1			T5	1		T53	12		T48	21
valid_sources[0x68]	459	1			T53	10		T77	2		T32	1
valid_sources[0x69]	390	1			T53	13		T48	13		T11	29
valid_sources[0x6a]	396	1			T53	9		T48	23		T11	6
valid_sources[0x6b]	391	1			T53	13		T198	1		T48	21
valid_sources[0x6c]	685	1			T39	2		T53	14		T206	2
valid_sources[0x6d]	623	1			T139	3		T53	11		T48	17
valid_sources[0x6e]	390	1			T53	11		T48	17		T11	32
valid_sources[0x6f]	723	1			T6	1		T53	18		T16	1
valid_sources[0x70]	501	1			T1	1		T53	11		T48	25
valid_sources[0x71]	538	1			T2	1		T53	17		T48	42
valid_sources[0x72]	424	1			T53	11		T48	20		T11	18
valid_sources[0x73]	622	1			T53	12		T48	24		T89	9
valid_sources[0x74]	467	1			T53	11		T205	2		T202	1
valid_sources[0x75]	378	1			T1	1		T6	1		T53	14
valid_sources[0x76]	554	1			T53	16		T48	18		T11	13
valid_sources[0x77]	535	1			T53	10		T202	1		T48	23
valid_sources[0x78]	501	1			T53	4		T48	12		T184	1
valid_sources[0x79]	532	1			T53	6		T205	1		T48	17
valid_sources[0x7a]	361	1			T53	16		T74	1		T198	1
valid_sources[0x7b]	665	1			T53	10		T48	18		T17	1
valid_sources[0x7c]	512	1			T53	14		T201	1		T48	25
valid_sources[0x7d]	457	1			T53	13		T48	14		T36	2
valid_sources[0x7e]	442	1			T53	11		T48	24		T11	16
valid_sources[0x7f]	613	1			T53	8		T200	1		T48	22
valid_sources[0x80]	655	1			T53	14		T16	1		T48	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29964

1

T53

667

T48

1310

T11

1255

values[0x0]

all_enables

biggest_size

42121

1

T1

1

T2

1

T3

2

values[0x1]

all_enables

biggest_size

41903

1

T1

1

T7

1

T3

7