Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

735136

1

T3

8

T4

5

T5

15

full_word

625870

1

T3

5

T4

2

T5

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1360696	1			T3	13		T4	7		T5	20
auto[TlIntgErrCmd]	102	1			T163	6		T164	8		T165	4
auto[TlIntgErrData]	104	1			T163	10		T164	7		T165	8
auto[TlIntgErrBoth]	104	1			T163	4		T164	5		T165	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

503114

1

T3

5

T4

3

T5

5

auto[1]

857892

1

T3

8

T4

4

T5

15

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	206487	1			T3	3		T4	2		T5	3
auto[TlIntgErrNone]	partial	auto[1]	528370	1			T3	5		T4	3		T5	12
auto[TlIntgErrNone]	full_word	auto[0]	296475	1			T3	2		T4	1		T5	2
auto[TlIntgErrNone]	full_word	auto[1]	329364	1			T3	3		T4	1		T5	3
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T163	4		T164	2		T165	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T163	2		T164	5		T165	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T164	1		T188	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T194	1		T191	1		-	-
auto[TlIntgErrData]	partial	auto[0]	47	1			T163	2		T164	3		T165	5
auto[TlIntgErrData]	partial	auto[1]	44	1			T163	5		T164	3		T165	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T163	1		T164	1		T192	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T163	2		T192	1		T187	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T163	2		T165	2		T192	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T163	2		T164	4		T165	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T164	1		T192	1		T190	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T165	2		T194	2		T193	1