Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 735136 1 T3 8 T4 5 T5 15
full_word 625870 1 T3 5 T4 2 T5 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 1360696 1 T3 13 T4 7 T5 20
auto[TlIntgErrCmd] 102 1 T163 6 T164 8 T165 4
auto[TlIntgErrData] 104 1 T163 10 T164 7 T165 8
auto[TlIntgErrBoth] 104 1 T163 4 T164 5 T165 8



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 503114 1 T3 5 T4 3 T5 5
auto[1] 857892 1 T3 8 T4 4 T5 15



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 206487 1 T3 3 T4 2 T5 3
auto[TlIntgErrNone] partial auto[1] 528370 1 T3 5 T4 3 T5 12
auto[TlIntgErrNone] full_word auto[0] 296475 1 T3 2 T4 1 T5 2
auto[TlIntgErrNone] full_word auto[1] 329364 1 T3 3 T4 1 T5 3
auto[TlIntgErrCmd] partial auto[0] 44 1 T163 4 T164 2 T165 1
auto[TlIntgErrCmd] partial auto[1] 51 1 T163 2 T164 5 T165 3
auto[TlIntgErrCmd] full_word auto[0] 5 1 T164 1 T188 1 T189 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T194 1 T191 1 - -
auto[TlIntgErrData] partial auto[0] 47 1 T163 2 T164 3 T165 5
auto[TlIntgErrData] partial auto[1] 44 1 T163 5 T164 3 T165 3
auto[TlIntgErrData] full_word auto[0] 6 1 T163 1 T164 1 T192 1
auto[TlIntgErrData] full_word auto[1] 7 1 T163 2 T192 1 T187 2
auto[TlIntgErrBoth] partial auto[0] 46 1 T163 2 T165 2 T192 1
auto[TlIntgErrBoth] partial auto[1] 47 1 T163 2 T164 4 T165 4
auto[TlIntgErrBoth] full_word auto[0] 4 1 T164 1 T192 1 T190 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T165 2 T194 2 T193 1

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