Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_csrs.i_fifo 92.86 100.00 71.43 100.00 100.00



Module Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.20 100.00 82.35 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
70.07 86.28 62.67 61.25 i_dm_csrs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T7
10Not Covered
11CoveredT1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T7
101Not Covered
110Not Covered
111CoveredT1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T7
101Not Covered
110Not Covered
111CoveredT1,T2,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T7
1CoveredT1,T2,T7

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T7


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T7
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T7


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T7


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 36130693 18319 0 0
DepthKnown_A 36130693 35611138 0 0
RvalidKnown_A 36130693 35611138 0 0
WreadyKnown_A 36130693 35611138 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 36130693 18319 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 18319 0 0
T1 3250 1 0 0
T2 13267 3 0 0
T3 634673 75 0 0
T4 11854 12 0 0
T5 247790 84 0 0
T7 1727 1 0 0
T12 88096 53 0 0
T13 2945 6 0 0
T14 371177 132 0 0
T28 226372 136 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 18319 0 0
T1 3250 1 0 0
T2 13267 3 0 0
T3 634673 75 0 0
T4 11854 12 0 0
T5 247790 84 0 0
T7 1727 1 0 0
T12 88096 53 0 0
T13 2945 6 0 0
T14 371177 132 0 0
T28 226372 136 0 0

Line Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T7
11CoveredT1,T2,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T7
10Not Covered
11CoveredT1,T2,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T7
101Not Covered
110Excluded VC_COV_UNR
111CoveredT1,T2,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T7
101Not Covered
110Excluded VC_COV_UNR
111CoveredT1,T2,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (34'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T7
1CoveredT1,T2,T7

Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T7


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T7
0 1 Covered T1,T2,T7
0 0 Covered T1,T2,T7


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T7
0 Covered T1,T2,T7


Assert Coverage for Instance : tb.dut.u_dm_top.i_dm_csrs.i_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 36130693 18319 0 0
DepthKnown_A 36130693 35611138 0 0
RvalidKnown_A 36130693 35611138 0 0
WreadyKnown_A 36130693 35611138 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 36130693 18319 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 18319 0 0
T1 3250 1 0 0
T2 13267 3 0 0
T3 634673 75 0 0
T4 11854 12 0 0
T5 247790 84 0 0
T7 1727 1 0 0
T12 88096 53 0 0
T13 2945 6 0 0
T14 371177 132 0 0
T28 226372 136 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 35611138 0 0
T1 3250 2962 0 0
T2 13267 12866 0 0
T3 634673 607440 0 0
T4 11854 11673 0 0
T5 247790 246092 0 0
T7 1727 1642 0 0
T12 88096 87154 0 0
T13 2945 2862 0 0
T14 371177 370815 0 0
T28 226372 225871 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 36130693 18319 0 0
T1 3250 1 0 0
T2 13267 3 0 0
T3 634673 75 0 0
T4 11854 12 0 0
T5 247790 84 0 0
T7 1727 1 0 0
T12 88096 53 0 0
T13 2945 6 0 0
T14 371177 132 0 0
T28 226372 136 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%