Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T7 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7443388 |
7441900 |
0 |
0 |
selKnown1 |
41475226 |
41473738 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7443388 |
7441900 |
0 |
0 |
T1 |
236 |
234 |
0 |
0 |
T2 |
696 |
694 |
0 |
0 |
T3 |
17627 |
17623 |
0 |
0 |
T4 |
2714 |
2710 |
0 |
0 |
T5 |
19054 |
19050 |
0 |
0 |
T6 |
0 |
14 |
0 |
0 |
T7 |
240 |
238 |
0 |
0 |
T8 |
0 |
9 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T12 |
11704 |
11700 |
0 |
0 |
T13 |
1274 |
1270 |
0 |
0 |
T14 |
30116 |
30112 |
0 |
0 |
T28 |
29592 |
29588 |
0 |
0 |
T29 |
0 |
13 |
0 |
0 |
T33 |
2 |
0 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T39 |
0 |
6 |
0 |
0 |
T40 |
2 |
0 |
0 |
0 |
T41 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
41475226 |
41473738 |
0 |
0 |
T1 |
3368 |
3366 |
0 |
0 |
T2 |
13615 |
13613 |
0 |
0 |
T3 |
643493 |
643489 |
0 |
0 |
T4 |
13212 |
13208 |
0 |
0 |
T5 |
257323 |
257319 |
0 |
0 |
T6 |
0 |
12 |
0 |
0 |
T7 |
1847 |
1845 |
0 |
0 |
T8 |
0 |
8 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T12 |
93952 |
93948 |
0 |
0 |
T13 |
3583 |
3579 |
0 |
0 |
T14 |
386236 |
386232 |
0 |
0 |
T28 |
241170 |
241166 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T33 |
2 |
0 |
0 |
0 |
T38 |
0 |
6 |
0 |
0 |
T39 |
0 |
6 |
0 |
0 |
T40 |
2 |
0 |
0 |
0 |
T41 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T7 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2098778 |
2098516 |
0 |
0 |
selKnown1 |
36130693 |
36130431 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2098778 |
2098516 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
348 |
347 |
0 |
0 |
T3 |
8804 |
8803 |
0 |
0 |
T4 |
1356 |
1355 |
0 |
0 |
T5 |
9521 |
9520 |
0 |
0 |
T7 |
120 |
119 |
0 |
0 |
T12 |
5848 |
5847 |
0 |
0 |
T13 |
636 |
635 |
0 |
0 |
T14 |
15057 |
15056 |
0 |
0 |
T28 |
14794 |
14793 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
36130693 |
36130431 |
0 |
0 |
T1 |
3250 |
3249 |
0 |
0 |
T2 |
13267 |
13266 |
0 |
0 |
T3 |
634673 |
634672 |
0 |
0 |
T4 |
11854 |
11853 |
0 |
0 |
T5 |
247790 |
247789 |
0 |
0 |
T7 |
1727 |
1726 |
0 |
0 |
T12 |
88096 |
88095 |
0 |
0 |
T13 |
2945 |
2944 |
0 |
0 |
T14 |
371177 |
371176 |
0 |
0 |
T28 |
226372 |
226371 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T7 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
758 |
496 |
0 |
0 |
T3 |
9 |
8 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
7 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T12 |
4 |
3 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T28 |
2 |
1 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
723 |
461 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T12 |
4 |
3 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T28 |
2 |
1 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T7 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5342111 |
5341629 |
0 |
0 |
selKnown1 |
5342111 |
5341629 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5342111 |
5341629 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
348 |
347 |
0 |
0 |
T3 |
8804 |
8803 |
0 |
0 |
T4 |
1356 |
1355 |
0 |
0 |
T5 |
9521 |
9520 |
0 |
0 |
T7 |
120 |
119 |
0 |
0 |
T12 |
5848 |
5847 |
0 |
0 |
T13 |
636 |
635 |
0 |
0 |
T14 |
15057 |
15056 |
0 |
0 |
T28 |
14794 |
14793 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5342111 |
5341629 |
0 |
0 |
T1 |
118 |
117 |
0 |
0 |
T2 |
348 |
347 |
0 |
0 |
T3 |
8804 |
8803 |
0 |
0 |
T4 |
1356 |
1355 |
0 |
0 |
T5 |
9521 |
9520 |
0 |
0 |
T7 |
120 |
119 |
0 |
0 |
T12 |
5848 |
5847 |
0 |
0 |
T13 |
636 |
635 |
0 |
0 |
T14 |
15057 |
15056 |
0 |
0 |
T28 |
14794 |
14793 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T7 |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T7 |
1 | 1 | Covered | T1,T2,T7 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1741 |
1259 |
0 |
0 |
selKnown1 |
1699 |
1217 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1741 |
1259 |
0 |
0 |
T3 |
10 |
9 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
7 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T12 |
4 |
3 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T28 |
2 |
1 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1699 |
1217 |
0 |
0 |
T3 |
8 |
7 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T12 |
4 |
3 |
0 |
0 |
T13 |
1 |
0 |
0 |
0 |
T14 |
1 |
0 |
0 |
0 |
T28 |
2 |
1 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T38 |
0 |
3 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |